// Transmit a PCIE TLP packet waiting for ACK
void pciePktSend(const u32 *pkt, int len)
{
    u32 pciePktSeq = regRead(0x7d10);
    u32 nextPciePktSeq = (pciePktSeq + 1) & 0xfff;

    while(len--) regWrite(0x7d38, *pkt++);

    int timeout = 10000;
    regWrite(0x7d10, nextPciePktSeq);
    while(((regRead(0x7d18) & 0xfff) != pciePktSeq) && timeout--);
}

// Write to remote PCIe device memory
void pcieHostMemWrite(u32 addr, u32 data)
{
    u32 pkt[] = { 0x40000001, 0x0000000f, addr, __builtin_bswap32(data)};
    pciePktSend(pkt, ARRAY_SIZE(pkt));
}

// Write to remote PCIe device config space
void pcieHostConfWrite(u32 addr, u32 data)
{
    u32 pkt[] = { 0x44000001, 0x0000000f, addr & 0xfff, __builtin_bswap32(data)};
    pciePktSend(pkt, ARRAY_SIZE(pkt));
}

// Act as upstream device - send config and memory access requests!!!
void pcieHostInit()
{
    int timeout;

#if CONFIG_PCIE_HOST_INIT2
    regWrite(0x7e08, BIT(0)); // go to disable state
    timeout = 1<<22;
    while((regRead(0x7e08) & BIT(0)) && --timeout);
    // reset PCIE PHY
    regWrite(0x7e00, BIT(0));
#endif

    // enable internal loopback mode
        regWrite(0x7e2c,BIT(11)|BIT(9)|BIT(8)|BIT(0));

        // wait for link up
    timeout = 1<<22;
    while(!(regRead(0x7d04) & BIT(16)) && --timeout);

        // set config request packets
        for(int i = 0; i < 10; i++)
                pcieHostConfWrite(0, 0);

//    regModify(0x7c00, 0,BIT(29)|BIT(25));

    regWrite(0x7c00, BIT(31)|BIT(29)|BIT(27)|BIT(26)|BIT(25)|BIT(22)|0x2f);
    regWrite(0x7c04, BIT(8)|BIT(7)|BIT(3)|BIT(2)|BIT(1)|BIT(0));
//    regWrite(0x7d00, 0x100);
//    while(regRead(0x7e00) & BIT(0));

    // enable downstream lane mode
    regWrite(0x7e2c,BIT(11)|BIT(9)|BIT(8)|BIT(3));
    // enable copying of received TLPs into retry buffer
//    regWrite(0x7d4c,BIT(15)); // |BIT(14));
//    regWrite(0x7d4c, 0xffffc000);

    pcieReadTag = 0;
#if CONFIG_PCIE_HOST_INIT2
    regWrite(0x7e08, BIT(6)); // go to detect state
    while(regRead(0x7e08) & BIT(6));
#endif

    // wait for link up
    timeout = 1<<22;
    while(!(regRead(0x7d04) & BIT(16)) && --timeout);

    // Timeout exceeded, probably due to reset or clock glitches, try and force
reset
    if(timeout == 0) {
        errFail(LED_FAIL_PCIE_LINK_UP);
        //oledPrintFail("Link Up Timeout");
        //delay_ms(100);
        //regWrite(0x7e08, BIT(1)); // via hot reset
        //delay_ms(100);
        //regWrite(0x7e00, BIT(1)); // now reset pcie
        //delay_ms(100);
        //regModify(0x68d, 0, BIT(0)); // reset entire system
    }

    // configure NIC to be visible from GPU
    regWrite(0x10, 0xf0000000); // base address register
    regWrite(0x14, 0);
    regWrite(0x18, 0xe0000000); // base address register
    regWrite(0x1c, 0);
    regWrite(0x30, 0xd0000000); // ROM base address register
    regWrite(0x04, BIT(2)|BIT(1));
}