`define SW 3
`define WAIT    3'b000
`define DECODE  3'b001
`define ALU_CLR 3'b010
`define ALU_ADD 3'b011
`define ALU_SH  3'b100
`define GET_A   3'b101
`define DONE    3'b110

module calc(clk, reset, s, in, op, out, ovf, done);
 input clk, reset, s;
 input [7:0] in;
 input [1:0] op;
 output [7:0] out;
 output ovf, done;

 reg done;

 reg selA, loadA, loadB, loadV;
 wire [7:0] ALUout, outB, outC;

 wire outV;
 wire zero;

 wire [2:0] presentState, nextStateReset;
 reg  [2:0] nextState;

 counter C(clk, selA, loadA, in, outC);
 ALU #(8) alu(outC, op, outB, ALUout, outV);

 RegLoad #(8) B(clk, loadB, ALUout, outB);
 RegLoad #(1) V(clk, loadV, outV, ovf);

 assign out = outB;
 assign zero = ~outC[0] & ~outC[1] & ~outC[2] & ~outC[3] & ~outC[4] & ~outC[5] & ~outC[6] & ~outC[7];

 vDFF #(`SW) STATE(clk, nextStateReset, presentState);
 assign nextStateReset = reset ? `WAIT : nextState;

 always @(*) begin
    case(presentState)
        `WAIT       : begin
                        done = 0;
                        loadB = 0;
                        loadV = 0;
                        selA = 1;
                        loadA = 0;
                        nextState = s ? `DECODE : `WAIT;

                        end
        `DECODE     : begin
                        done = 0;
                        loadB = 0;
                        loadV = 0;
                        selA = 1;
                        loadA = 0;
                        case(op)
                            2'b00 : nextState = `ALU_CLR;
                            2'b01 : nextState = `GET_A;
                            2'b10 : nextState = `GET_A;
                            default : nextState = 3'bxxx;
                        endcase
                    end
        `ALU_CLR    : begin
                        loadB = 1;
                        done = 0;
                        selA = 1;
                        loadV = 0;
                        loadA = 0;
                        nextState = `DONE;
                    end
        `ALU_ADD    : begin
                        loadB = 1;
                        loadV = 1;
                        done = 0;
                        selA = 1;
                        loadA = 0;
                        nextState = `DONE;
                    end
        `ALU_SH     : begin
                        loadB = 1;
                        done = 0;
                        selA = 1;
                        loadV = 0;
                        loadA = 0;
                        nextState = `DONE;
                    end
        `GET_A      : begin
                        selA = 1;
                        loadA = 1;
                        loadB = 0;
                        loadV = 0;
                        done = 0;

                        case(op)
                            2'b01 : nextState = `ALU_ADD;
                            2'b10 : nextState = `ALU_SH;
                            default : nextState = 3'bxxx;
                        endcase
                    end
        `DONE       : begin
                        loadB = 0;
                        done = 1;
                        selA = 1;
                        loadV = 0;
                        loadA = 0;
                        nextState = `WAIT;
                    end
        default : begin
                    done = 0;
                    loadB = 0;
                    loadV = 0;
                    selA = 1;
                    loadA = 0;
                    nextState = 3'bxxx;
                end
    endcase
 end



endmodule


module RegLoad( clk, load, in, out) ;
  parameter n = 1;  // width
  input load, clk;
  input     [n-1:0] in ;
  output    [n-1:0] out;
  reg       [n-1:0] out;
  wire      [n-1:0] next;

  // Flip flop, assigns output on rising edge of clk
  always @(posedge clk)
    out = next ;
  // Multiplexer using ? operator, assigns next to in if load is 1, and out if load is 0
  assign next = load ? in : out;
endmodule // RegLoad

module counter(clk, selA, loadA, in, outC);
    input clk, selA, loadA;
    input [7:0] in;
    output [7:0] outC;

    wire [7:0] muxOut;


    RegLoad #(8) A(clk, loadA, muxOut, outC);

    assign muxOut = selA ? in : outC - 8'b0000_0001;

endmodule

module ALU(in, op, outB, ALUout, outV);
    parameter n = 8;
    input [n-1:0] in;
    input [1:0] op;
    input [n-1:0] outB;
    output reg [n-1:0] ALUout;
    output outV;

    wire [7:0] addedR;

    AddSub add(outB, in, 1'b0, addedR, outV);

    always @(*) begin
        case (op)
            2'b00 : ALUout = 0;  // CLEAR
            2'b01 : ALUout = addedR;
            2'b10 : begin
                        ALUout = outB >>> in;
                    end
        endcase
    end

endmodule

// from slide set 6
// add a+b or subtract a-b, check for overflow
module AddSub(a,b,sub,s,ovf) ;
  parameter n = 8 ;
  input [n-1:0] a, b ;
  input sub ;           // subtract if sub=1, otherwise add
  output [n-1:0] s ;
  output ovf ;          // 1 if overflow
  wire c1, c2 ;         // carry out of last two bits
  wire ovf = c1 ^ c2 ;  // overflow if signs don't match

  // add non sign bits
  Adder1 #(n-1) ai(a[n-2:0],b[n-2:0]^{n-1{sub}},sub,c1,s[n-2:0]) ;
  // add sign bits
  Adder1 #(1)   as(a[n-1],b[n-1]^sub,c1,c2,s[n-1]) ;
endmodule

// from slide set 6
// multi-bit adder - behavioral
module Adder1(a,b,cin,cout,s) ;
  parameter n = 8 ;
  input [n-1:0] a, b ;
  input cin ;
  output [n-1:0] s ;
  output cout ;
  wire [n-1:0] s;
  wire cout ;

  assign {cout, s} = a + b + cin ;
endmodule