LiteX no clock constraint

#!/usr/bin/env python3

from migen import *

from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform

# Declare IOs

_io = [
    ("clk50", 0, Pins("P123"), IOStandard("LVCMOS33")),
    ("user_led", 0, Pins("P119"), IOStandard("LVCMOS33"), Drive(8)),
    ("user_led", 1, Pins("P118"), IOStandard("LVCMOS33"), Drive(8)),
    ("user_led", 2, Pins("P117"), IOStandard("LVCMOS33"), Drive(8)),
]

# Platform
class Platform(XilinxPlatform):
    default_clk_name    = "clk50"
    default_clk_period  = 20        # period in ns

    # W25Q16DV - component U1
    # 16Mb - 75 MHz clock frequency
    spiflash_model = "w25q16dw"
    spiflash_read_dummy_bits = 8
    spiflash_clock_div = 4
    spiflash_total_size = int((16/8)*1024*1024) # 16Mbit
    spiflash_page_size = 256
    spiflash_sector_size = 0x10000

    def __init__(self):
        XilinxPlatform.__init__(self, "xc6slx9-tqg144-2", _io, toolchain="ise")

    def do_finalize(self, fragment):
        XilinxPlatform.do_finalize(self, fragment)

    def create_programmer(self):
        raise NotImplementedError

platform = Platform()
ledb = platform.request("user_led", 0)
ledg = platform.request("user_led", 1)
ledr = platform.request("user_led", 2)

module = Module()
counter = Signal(32)

module.sync += [
    counter.eq(counter + 1),
    If(counter == int(50e6),
        counter.eq(0)
        ),
    ledb.eq(counter[23]),
    ledg.eq(counter[24]),
    ledr.eq(counter[25])
]

platform.build(module)