module cntrl_7seg(
    input clk,
    input rst,
    input [3:0] din0,
    input [3:0] din1,
    output [3:0] AN,
    output [7:0] SEG,
    output dbg_en,
    output [1:0] dbg_cntr,
    output [3:0] dbg_dmux
);


// ~kHz periódusidejû engedélyezõjel generálása
wire en;
reg [15:0] cnt;

always @ (posedge clk)
   if(en | rst)
      cnt <= 0;
   else
      cnt <= cnt + 1;

//assign en = (cnt == 49999);
assign en = (cnt == 1);

// 4 bites shift regiszter
reg [3:0] shr;

always @ (posedge clk)
   if(rst)
      shr <= 4'b1110;
   else
      if(en)
         shr <= {shr[2:0], shr[3]};

assign AN = shr;

// 2 bites számláló
reg [1:0] cntr;

always @ (posedge clk)
   if(rst)
      cntr <= 0;
   else
      if(en)
      cntr <= cntr + 1;

// 4 bites, 4:1 multiplexer
reg [3:0] dmux;

always @ (*)
case (cntr)
   2'b00: dmux <= din0;
   2'b01: dmux <= din1;
   2'b10: dmux <= 0;
   2'b11: dmux <= 0;
endcase


// szegmens dekóder
reg [7:0] SEG_DEC;
always @(dmux)
    case (dmux)
        4'h0:    SEG_DEC <= 8'b00000011;
        4'h1:    SEG_DEC <= 8'b10011111;
        4'h2:    SEG_DEC <= 8'b00100101;
        4'h3:    SEG_DEC <= 8'b00001101;
        4'h4:    SEG_DEC <= 8'b10011001;
        4'h5:    SEG_DEC <= 8'b01001001;
        4'h6:    SEG_DEC <= 8'b01000001;
        4'h7:    SEG_DEC <= 8'b00011111;
        4'h8:    SEG_DEC <= 8'b00000001;
        4'h9:    SEG_DEC <= 8'b00001001;
        default: SEG_DEC <= 8'b11111111;
    endcase

assign SEG = SEG_DEC;

assign dbg_en = en;
assign dbg_cntr = cntr;
assign dbg_dmux = dmux;

endmodule