`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:10:19 05/17/2019
// Design Name:
// Module Name: coffe_main
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`define INIT 3'b000
`define C05 3'b001
`define C10 3'b010
`define C15 3'b011
`define C20 3'b100
`define Exprr 3'b110
`define Expr_l 3'b101
`define Capp 3'b111

module coffe_main(
input clk,rst,
input credit05,credit10,
input [1:0] coffee,
output [5:0] current_state,
output reg exprr,expr_l,capp
);
reg [2:0] state_nxt, state_reg;
always @(posedge clk or posedge rst)
begin
if(rst)
state_reg <= 0;
else
state_reg <= state_nxt;
end
assign current_state=state_nxt;
always @(state_reg, coffee, credit05, credit10)
begin

state_nxt=state_reg;
exprr=0;
expr_l=0;
capp=0;

case(state_reg)
`INIT: begin
state_nxt=`INIT;
exprr=0;
expr_l=0;
capp=0;
if(credit05)
state_nxt=`C05;
if(credit10)
state_nxt=`C10;
end
`C05: begin
state_nxt=`C05;
exprr=0;
expr_l=0;
capp=0;
if(credit05)
state_nxt=`C10;
if(credit10)
state_nxt=`C15;
end


`C10: begin
state_nxt=`C10;
exprr=0;
expr_l=0;
capp=0;
if(credit05)
state_nxt=`C15;
if(credit10)
state_nxt=`C20;
end
`C15: begin
state_nxt=`C15;
exprr=0;
expr_l=0;
capp=0;
if(credit05 | credit10)
state_nxt=`C20;
end
`C20: begin
state_nxt=`C20;
exprr=0;
expr_l=0;
capp=0;
if(coffee==2'b01)
state_nxt=`Exprr;
if(coffee==2'b10)
state_nxt=`Expr_l;
if(coffee==2'b11)
state_nxt=`Capp;
end

`Exprr: begin
state_nxt=`INIT;
exprr=1;
expr_l=0;
capp=0;
end
`Expr_l : begin
state_nxt=`INIT;
exprr=0;
expr_l=1;
capp=0;
end
`Capp: begin
state_nxt=`INIT;
exprr=0;
expr_l=0;
capp=1;
end
endcase
end


endmodule