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  1. /*
  2. * Copyright (C) 2009 Jan Weitzel, Phytec Messtechnik GmbH
  3. * based on pcm043.c
  4. * Copyright (C) 2009 Sascha Hauer, Pengutronix
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. */
  20.  
  21. #include <linux/types.h>
  22. #include <linux/init.h>
  23.  
  24. #include <linux/platform_device.h>
  25. #include <linux/mtd/physmap.h>
  26. #include <linux/mtd/plat-ram.h>
  27. #include <linux/memory.h>
  28. #include <linux/gpio.h>
  29. #include <linux/smc911x.h>
  30. #include <linux/interrupt.h>
  31. #include <linux/i2c.h>
  32. #include <linux/i2c/at24.h>
  33. #include <linux/fsl_devices.h>
  34. #include <linux/delay.h>
  35. #ifdef CONFIG_SPI
  36. #include <linux/spi/spi.h>
  37. #endif
  38. #ifdef CONFIG_GPIO_MAX7301
  39. #include <linux/spi/max7301.h>
  40. #endif
  41.  
  42. #include <asm/mach-types.h>
  43. #include <asm/mach/arch.h>
  44. #include <asm/mach/time.h>
  45. #include <asm/mach/map.h>
  46.  
  47. #include <mach/hardware.h>
  48. #include <mach/common.h>
  49. #include <mach/imx-uart.h>
  50. #if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
  51. #include <mach/i2c.h>
  52. #endif
  53. #ifdef CONFIG_SPI
  54. #include <mach/spi.h>
  55. #endif
  56. #include <mach/iomux-mx35.h>
  57. #include <mach/ipu.h>
  58. #include <mach/mx3fb.h>
  59. #include <mach/mxc_ehci.h>
  60. #include <mach/audmux.h>
  61. #include <mach/ssi.h>
  62. #include <mach/mxc_nand.h>
  63.  
  64. #include "devices.h"
  65.  
  66. static const struct fb_videomode fb_modedb[] = {
  67. {
  68. .name = "Primeview-PD050VL1",
  69. .refresh = 60,
  70. .xres = 640,
  71. .yres = 480,
  72. .pixclock = 45045, /* in ps (22,2 MHz) */
  73. .hsync_len = 32,
  74. .left_margin = 112,
  75. .right_margin = 36,
  76. .vsync_len = 2,
  77. .upper_margin = 33,
  78. .lower_margin = 33,
  79. .sync = FB_SYNC_OE_ACT_HIGH,
  80. .vmode = FB_VMODE_NONINTERLACED,
  81. .flag = 0,
  82. },
  83. };
  84.  
  85. static struct ipu_platform_data mx3_ipu_data = {
  86. .irq_base = MXC_IPU_IRQ_START,
  87. };
  88.  
  89. static struct mx3fb_platform_data mx3fb_pdata = {
  90. .dma_dev = &mx3_ipu.dev,
  91. .name = "Primeview-PD050VL1",
  92. .mode = fb_modedb,
  93. .num_modes = ARRAY_SIZE(fb_modedb),
  94. };
  95.  
  96. static struct imxuart_platform_data uart_pdata = {
  97. .flags = IMXUART_HAVE_RTSCTS,
  98. };
  99.  
  100. #if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
  101. static struct imxi2c_platform_data pca101_i2c_1_data = {
  102. .bitrate = 50000,
  103. };
  104.  
  105. static struct at24_platform_data board_eeprom = {
  106. .byte_len = 4096,
  107. .page_size = 32,
  108. .flags = AT24_FLAG_ADDR16,
  109. };
  110.  
  111. static struct i2c_board_info pca101_i2c_devices_modul[] = {
  112. {
  113. I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
  114. .platform_data = &board_eeprom,
  115. }
  116. };
  117.  
  118. static struct imxi2c_platform_data pca101_i2c_3_data = {
  119. .bitrate = 50000,
  120. };
  121.  
  122. static struct i2c_board_info pca101_i2c_devices_board[] = {
  123. {
  124. I2C_BOARD_INFO("pcf8563", 0x51),
  125. }
  126. };
  127. #endif
  128.  
  129. static struct platform_device *devices[] __initdata = {
  130. &mxc_fec_device,
  131. &mxc_w1_master_device,
  132. };
  133.  
  134. static struct pad_desc pca101_pads[] = {
  135. /* UART1 */
  136. MX35_PAD_CTS1__UART1_CTS,
  137. MX35_PAD_RTS1__UART1_RTS,
  138. MX35_PAD_TXD1__UART1_TXD_MUX,
  139. MX35_PAD_RXD1__UART1_RXD_MUX,
  140. /* FEC */
  141. MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
  142. MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
  143. MX35_PAD_FEC_RX_DV__FEC_RX_DV,
  144. MX35_PAD_FEC_COL__FEC_COL,
  145. MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
  146. MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
  147. MX35_PAD_FEC_TX_EN__FEC_TX_EN,
  148. MX35_PAD_FEC_MDC__FEC_MDC,
  149. MX35_PAD_FEC_MDIO__FEC_MDIO,
  150. MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
  151. MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
  152. MX35_PAD_FEC_CRS__FEC_CRS,
  153. MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
  154. MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
  155. MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
  156. MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
  157. MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
  158. MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
  159. /* I2C1 Module*/
  160. MX35_PAD_I2C1_CLK__I2C1_SCL,
  161. MX35_PAD_I2C1_DAT__I2C1_SDA,
  162. /* I2C3 Board */
  163. MX35_PAD_ATA_DATA12__I2C3_SCL,
  164. MX35_PAD_ATA_DATA13__I2C3_SDA,
  165. /* Display */
  166. MX35_PAD_LD0__IPU_DISPB_DAT_0,
  167. MX35_PAD_LD1__IPU_DISPB_DAT_1,
  168. MX35_PAD_LD2__IPU_DISPB_DAT_2,
  169. MX35_PAD_LD3__IPU_DISPB_DAT_3,
  170. MX35_PAD_LD4__IPU_DISPB_DAT_4,
  171. MX35_PAD_LD5__IPU_DISPB_DAT_5,
  172. MX35_PAD_LD6__IPU_DISPB_DAT_6,
  173. MX35_PAD_LD7__IPU_DISPB_DAT_7,
  174. MX35_PAD_LD8__IPU_DISPB_DAT_8,
  175. MX35_PAD_LD9__IPU_DISPB_DAT_9,
  176. MX35_PAD_LD10__IPU_DISPB_DAT_10,
  177. MX35_PAD_LD11__IPU_DISPB_DAT_11,
  178. MX35_PAD_LD12__IPU_DISPB_DAT_12,
  179. MX35_PAD_LD13__IPU_DISPB_DAT_13,
  180. MX35_PAD_LD14__IPU_DISPB_DAT_14,
  181. MX35_PAD_LD15__IPU_DISPB_DAT_15,
  182. MX35_PAD_LD16__IPU_DISPB_DAT_16,
  183. MX35_PAD_LD17__IPU_DISPB_DAT_17,
  184. MX35_PAD_LD18__IPU_DISPB_DAT_18,
  185. MX35_PAD_LD19__IPU_DISPB_DAT_19,
  186. MX35_PAD_LD20__IPU_DISPB_DAT_20,
  187. MX35_PAD_LD21__IPU_DISPB_DAT_21,
  188. MX35_PAD_LD22__IPU_DISPB_DAT_22,
  189. MX35_PAD_LD23__IPU_DISPB_DAT_23,
  190. MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
  191. MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
  192. MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
  193. MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
  194. /* USB host */
  195. MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR,
  196. MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC,
  197. /* SPI */
  198. MX35_PAD_CSPI1_SS0__CSPI1_SS0,
  199. MX35_PAD_CSPI1_SS1__CSPI1_SS1,
  200. MX35_PAD_CSPI1_MISO__CSPI1_MISO,
  201. MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
  202. MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
  203. MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY,
  204. /* SSI */
  205. MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
  206. MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
  207. MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
  208. MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
  209. /* 1-Wire*/
  210. MX35_PAD_GPIO1_0__OWIRE_LINE,
  211. /* GPIO */
  212. ///* VB
  213. MX35_PAD_ATA_CS0__GPIO2_6,
  214. MX35_PAD_ATA_CS1__GPIO2_7,
  215. MX35_PAD_ATA_DATA10__GPIO2_23, // ADD VB
  216. //MX35_PAD_SRXD5__GPIO1_1, // ADD VB
  217. MX35_PAD_CSPI1_SS0__GPIO1_18, // ADD VB
  218. MX35_PAD_CSPI1_SS1__GPIO1_19, // ADD VB
  219. //VB */
  220. };
  221.  
  222. static int pca101_usbh1_init(struct platform_device *pdev)
  223. {
  224. unsigned int tmp;
  225.  
  226. tmp = readl(IO_ADDRESS(MX35_OTG_BASE_ADDR) + 0x600);
  227. tmp &= ~((3 << 21) | (1 << 2) | (1 << 16));
  228. tmp |= (1 << 4) | (2 << 21) | (1 << 19) | (1 << 12) | (1 << 6) | (1 << 5);
  229. writel(tmp, IO_ADDRESS(MX35_OTG_BASE_ADDR) + 0x600);
  230.  
  231. tmp = readl(IO_ADDRESS(MX35_OTG_BASE_ADDR) + 0x584);
  232. tmp |= (3 << 30);
  233. writel(tmp, IO_ADDRESS(MX35_OTG_BASE_ADDR) + 0x584);
  234.  
  235. return 0;
  236. }
  237.  
  238. static struct mxc_usbh_platform_data usbh1_pdata = {
  239. .init = pca101_usbh1_init,
  240. };
  241.  
  242. static int pca101_otg_init(struct platform_device *pdev)
  243. {
  244. unsigned int tmp;
  245.  
  246. tmp = readl(IO_ADDRESS(MX35_OTG_BASE_ADDR) + 0x600);
  247. tmp &= ~(3 << 29);
  248. tmp |= (2 << 29);
  249. writel(tmp, IO_ADDRESS(MX35_OTG_BASE_ADDR) + 0x600);
  250.  
  251. tmp = readl(IO_ADDRESS(MX35_OTG_BASE_ADDR) + 0x184);
  252. tmp &= ~(3 << 30);
  253. writel(tmp, IO_ADDRESS(MX35_OTG_BASE_ADDR) + 0x184);
  254.  
  255. return 0;
  256. }
  257.  
  258. static struct mxc_usbh_platform_data otg_pdata = {
  259. .init = pca101_otg_init,
  260. };
  261.  
  262. static struct fsl_usb2_platform_data usb_data = {
  263. .operating_mode = FSL_USB2_DR_DEVICE,
  264. .phy_mode = FSL_USB2_PHY_UTMI,
  265. };
  266.  
  267. #ifdef CONFIG_SPI
  268. static unsigned int pca101_spi_cs [] = {MXC_SPI_CS(0), };
  269.  
  270. static struct spi_imx_master pca101_spi_0_data = {
  271. .chipselect = pca101_spi_cs,
  272. .num_chipselect = ARRAY_SIZE (pca101_spi_cs),
  273. };
  274. #endif /* CONFIG_SPI */
  275.  
  276. #ifdef CONFIG_GPIO_MAX7301
  277. static struct max7301_platform_data max7301_info = {
  278. .base = -1,
  279. };
  280.  
  281. // bus_num must match id in imx_spi_device struct
  282. static struct spi_board_info spi_board_info [] __initdata = {
  283. {
  284. .modalias = "max7301",
  285. .platform_data = &max7301_info,
  286. .max_speed_hz = 13000000,
  287. .bus_num = 1,
  288. .chip_select = 0,
  289. .mode = SPI_MODE_0,
  290. },
  291.  
  292.  
  293.  
  294. };
  295. #endif /* CONFIG_GPIO_MAX7301 */
  296. /* VB */
  297. static struct spi_board_info spi_board_info [] __initdata = {
  298. {
  299. .modalias = "spidev",
  300. .max_speed_hz = 10000000,
  301. .bus_num = 1,
  302. .chip_select = 0,
  303. .mode = SPI_MODE_0,
  304. },
  305. };
  306. /* VB */
  307.  
  308. static int otg_mode_host;
  309.  
  310. static int __init pca101_otg_mode(char *options)
  311. {
  312. if (!strcmp(options, "host"))
  313. otg_mode_host = 1;
  314. else if (!strcmp(options, "device"))
  315. otg_mode_host = 0;
  316. else
  317. pr_info("pca101_otg_mode neither \"host\" nor \"device\". "
  318. "Defaulting to device\n");
  319. return 0;
  320. }
  321. __setup("pca101_otg_mode=", pca101_otg_mode);
  322.  
  323. #define AC97_GPIO_TXFS (1 * 32 + 31)
  324. #define AC97_GPIO_TXD (1 * 32 + 28)
  325. #define AC97_GPIO_RESET (2 * 32 + 2)
  326.  
  327. static void pca101_ac97_warm_reset(struct snd_ac97 *ac97)
  328. {
  329. struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
  330. struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
  331. int ret;
  332.  
  333. ret = gpio_request(AC97_GPIO_TXFS, "SSI");
  334. if (ret) {
  335. printk("failed to get GPIO_TXFS: %d\n", ret);
  336. return;
  337. }
  338.  
  339. mxc_iomux_v3_setup_pad(&txfs_gpio);
  340.  
  341. /* warm reset */
  342. gpio_direction_output(AC97_GPIO_TXFS, 1);
  343. udelay(2);
  344. gpio_set_value(AC97_GPIO_TXFS, 0);
  345.  
  346. gpio_free(AC97_GPIO_TXFS);
  347. mxc_iomux_v3_setup_pad(&txfs);
  348. }
  349.  
  350. static void pca101_ac97_cold_reset(struct snd_ac97 *ac97)
  351. {
  352. struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
  353. struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
  354. struct pad_desc txd_gpio = MX35_PAD_STXD4__GPIO2_28;
  355. struct pad_desc txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD;
  356. struct pad_desc reset_gpio = MX35_PAD_ATA_DA2__GPIO3_2;
  357. int ret;
  358.  
  359. ret = gpio_request(AC97_GPIO_TXFS, "SSI");
  360. if (ret)
  361. goto err1;
  362.  
  363. ret = gpio_request(AC97_GPIO_TXD, "SSI");
  364. if (ret)
  365. goto err2;
  366.  
  367. ret = gpio_request(AC97_GPIO_RESET, "SSI");
  368. if (ret)
  369. goto err3;
  370.  
  371. mxc_iomux_v3_setup_pad(&txfs_gpio);
  372. mxc_iomux_v3_setup_pad(&txd_gpio);
  373. mxc_iomux_v3_setup_pad(&reset_gpio);
  374.  
  375. gpio_direction_output(AC97_GPIO_TXFS, 0);
  376. gpio_direction_output(AC97_GPIO_TXD, 0);
  377.  
  378. /* cold reset */
  379. gpio_direction_output(AC97_GPIO_RESET, 0);
  380. udelay(10);
  381. gpio_direction_output(AC97_GPIO_RESET, 1);
  382.  
  383. mxc_iomux_v3_setup_pad(&txd);
  384. mxc_iomux_v3_setup_pad(&txfs);
  385.  
  386. gpio_free(AC97_GPIO_RESET);
  387. err3:
  388. gpio_free(AC97_GPIO_TXD);
  389. err2:
  390. gpio_free(AC97_GPIO_TXFS);
  391. err1:
  392. if (ret)
  393. printk("%s failed with %d\n", __func__, ret);
  394. mdelay(1);
  395. }
  396.  
  397. static struct imx_ssi_platform_data pca101_ssi_pdata = {
  398. .ac97_reset = pca101_ac97_cold_reset,
  399. .ac97_warm_reset = pca101_ac97_warm_reset,
  400. .flags = IMX_SSI_USE_AC97,
  401. };
  402.  
  403. static struct mxc_nand_platform_data pca101_nand_board_info = {
  404. .width = 1,
  405. .hw_ecc = 1,
  406. };
  407.  
  408. /*
  409. * Board specific initialization.
  410. */
  411. static void __init mxc_board_init(void)
  412. {
  413. unsigned int tmp;
  414. mxc_iomux_v3_setup_multiple_pads(pca101_pads, ARRAY_SIZE(pca101_pads));
  415.  
  416. mxc_audmux_v2_configure_port(3,
  417. MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
  418. MXC_AUDMUX_V2_PTCR_TFSEL(0) |
  419. MXC_AUDMUX_V2_PTCR_TFSDIR,
  420. MXC_AUDMUX_V2_PDCR_RXDSEL(0));
  421.  
  422. mxc_audmux_v2_configure_port(0,
  423. MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
  424. MXC_AUDMUX_V2_PTCR_TCSEL(3) |
  425. MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
  426. MXC_AUDMUX_V2_PDCR_RXDSEL(3));
  427.  
  428. platform_add_devices(devices, ARRAY_SIZE(devices));
  429.  
  430. mxc_register_device(&mxc_uart_device0, &uart_pdata);
  431.  
  432. mxc_register_device(&imx_ssi_device0, &pca101_ssi_pdata);
  433.  
  434. #if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
  435. i2c_register_board_info(0, pca101_i2c_devices_modul,
  436. ARRAY_SIZE(pca101_i2c_devices_modul));
  437.  
  438. mxc_register_device(&mxc_i2c_device0, &pca101_i2c_1_data);
  439.  
  440. i2c_register_board_info(2, pca101_i2c_devices_board,
  441. ARRAY_SIZE(pca101_i2c_devices_board));
  442.  
  443. mxc_register_device(&mxc_i2c_device2, &pca101_i2c_3_data);
  444. #endif
  445.  
  446. mxc_register_device(&mxc_nand_device, &pca101_nand_board_info);
  447. mxc_register_device(&mx3_ipu, &mx3_ipu_data);
  448. mxc_register_device(&mx3_fb, &mx3fb_pdata);
  449.  
  450. tmp = readl(IO_ADDRESS(MX35_OTG_BASE_ADDR) + 0x600);
  451. tmp &= ~(3 << 29);
  452. tmp |= (2 << 29);
  453. writel(tmp, IO_ADDRESS(MX35_OTG_BASE_ADDR) + 0x600);
  454.  
  455. mxc_register_device(&mxc_usbh1, &usbh1_pdata);
  456. if (otg_mode_host)
  457. mxc_register_device(&mxc_otg_host, &otg_pdata);
  458. else
  459. mxc_register_device(&mxc_otg_udc_device, &usb_data);
  460. #ifdef CONFIG_SPI
  461. mxc_register_device (&mxc_spi_device0, &pca101_spi_0_data);
  462. #endif
  463. #ifdef CONFIG_GPIO_MAX7301
  464. spi_register_board_info (spi_board_info,
  465. ARRAY_SIZE (spi_board_info));
  466. #endif
  467. /* VB */
  468. printk("** VB spi_register_board_info...\n");
  469. tmp=spi_register_board_info (spi_board_info,
  470. ARRAY_SIZE (spi_board_info));
  471. printk("** VB tmp=%d\n", tmp);
  472. /* VB */
  473. }
  474.  
  475. static void __init pca101_timer_init(void)
  476. {
  477. printk("mx35_clocks_init()\n");
  478. mx35_clocks_init();
  479. }
  480.  
  481. struct sys_timer pca101_timer = {
  482. .init = pca101_timer_init,
  483. };
  484.  
  485. MACHINE_START(PCA101, "Phytec PhyCARD-M pca101 VB")
  486. /* Maintainer: Phytec */
  487. .phys_io = AIPS1_BASE_ADDR,
  488. .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
  489. .boot_params = PHYS_OFFSET + 0x100,
  490. .map_io = mx35_map_io,
  491. .init_irq = mx35_init_irq,
  492. .init_machine = mxc_board_init,
  493. .timer = &pca101_timer,
  494. MACHINE_END
  495.  
  496. #define BACKLIGHT_GPIO (1 * 32 + 7)
  497. static int __init pca101_baseboard_init_late(void)
  498. {
  499. int ret;
  500.  
  501. /*Switch Backligth on*/
  502. ret = gpio_request(BACKLIGHT_GPIO, "BACKLIGHT");
  503. if (!ret) {
  504. gpio_direction_output(BACKLIGHT_GPIO, 0);
  505. gpio_free(BACKLIGHT_GPIO);
  506. }
  507.  
  508. return ret;
  509. }
  510. late_initcall(pca101_baseboard_init_late);
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