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- module srl_fifo#(
- parameter DATA_WIDTH = 32,
- parameter DEPTH = 16
- )(
- input clk,
- input enq_enable,
- input [DATA_WIDTH-1:0] enq_data,
- output reg enq_ready,
- input deq_enable,
- output reg deq_ready,
- output reg [DATA_WIDTH-1:0] deq_data
- );
- localparam ADDR_WIDTH = $clog2(DEPTH);
- localparam FULL = DEPTH-1;
- localparam EMPTY = -1;
- integer i;
- reg [DATA_WIDTH-1:0] array[0:DEPTH-1];
- reg [ADDR_WIDTH:0] read_pos = EMPTY;
- always @(posedge clk) begin
- deq_data <= array[read_pos[ADDR_WIDTH-1:0]];
- if (deq_enable && deq_ready)
- read_pos = read_pos - 1;
- if (enq_enable && enq_ready) begin
- read_pos = read_pos + 1;
- array[0] <= enq_data;
- for (i = 1; i < DEPTH; i = i+1)
- array[i] <= array[i-1];
- end
- deq_ready <= read_pos != EMPTY;
- enq_ready <= read_pos != FULL;
- end
- endmodule
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