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5729-beagleboneai.dts

lorforlinux
Jun 16th, 2020
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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
  4. */
  5.  
  6. /dts-v1/;
  7.  
  8. #include "dra74x.dtsi"
  9. #include "am57xx-commercial-grade.dtsi"
  10. #include "dra74x-mmc-iodelay.dtsi"
  11. #include "dra74-ipu-dsp-common.dtsi"
  12. #include <dt-bindings/gpio/gpio.h>
  13. #include <dt-bindings/interrupt-controller/irq.h>
  14. #include <dt-bindings/pinctrl/dra.h>
  15.  
  16. / {
  17. model = "BeagleBoard.org BeagleBone AI";
  18. compatible = "beagle,am5729-beagleboneai", "ti,am5728",
  19. "ti,dra742", "ti,dra74", "ti,dra7";
  20.  
  21. aliases {
  22. rtc0 = &tps659038_rtc;
  23. rtc1 = &rtc;
  24. display0 = &hdmi_conn;
  25. };
  26.  
  27. chosen {
  28. stdout-path = &uart1;
  29. base_dtb = "am5729-beagleboneai.dts";
  30. base_dtb_timestamp = __TIMESTAMP__;
  31. };
  32.  
  33. memory@0 {
  34. device_type = "memory";
  35. reg = <0x0 0x80000000 0x0 0x40000000>;
  36. };
  37.  
  38. reserved-memory {
  39. #address-cells = <2>;
  40. #size-cells = <2>;
  41. ranges;
  42.  
  43. cmem_block_mem_1_ocmc3: cmem_block_mem@40500000 {
  44. reg = <0x0 0x40500000 0x0 0x100000>;
  45. no-map;
  46. status = "okay";
  47. };
  48.  
  49. ipu2_memory_region: ipu2-memory@95800000 {
  50. compatible = "shared-dma-pool";
  51. reg = <0x0 0x95800000 0x0 0x3800000>;
  52. reusable;
  53. status = "okay";
  54. };
  55.  
  56. dsp1_memory_region: dsp1-memory@99000000 {
  57. compatible = "shared-dma-pool";
  58. reg = <0x0 0x99000000 0x0 0x4000000>;
  59. reusable;
  60. status = "okay";
  61. };
  62.  
  63. ipu1_memory_region: ipu1-memory@9d000000 {
  64. compatible = "shared-dma-pool";
  65. reg = <0x0 0x9d000000 0x0 0x2000000>;
  66. reusable;
  67. status = "okay";
  68. };
  69.  
  70. dsp2_memory_region: dsp2-memory@9f000000 {
  71. compatible = "shared-dma-pool";
  72. reg = <0x0 0x9f000000 0x0 0x800000>;
  73. reusable;
  74. status = "okay";
  75. };
  76.  
  77. cmem_block_mem_0: cmem_block_mem@a0000000 {
  78. reg = <0x0 0xa0000000 0x0 0x18000000>;
  79. no-map;
  80. status = "okay";
  81. };
  82. };
  83.  
  84. cmem {
  85. compatible = "ti,cmem";
  86. #address-cells = <1>;
  87. #size-cells = <0>;
  88. #pool-size-cells = <2>;
  89. status = "okay";
  90.  
  91. cmem_block_0: cmem_block@0 {
  92. reg = <0>;
  93. memory-region = <&cmem_block_mem_0>;
  94. cmem-buf-pools = <1 0x0 0x18000000>;
  95. };
  96.  
  97. cmem_block_1: cmem_block@1 {
  98. reg = <1>;
  99. memory-region = <&cmem_block_mem_1_ocmc3>;
  100. };
  101. };
  102.  
  103. vdd_adc: gpioregulator-vdd_adc {
  104. compatible = "regulator-gpio";
  105. regulator-name = "vdd_adc";
  106. vin-supply = <&vdd_5v>;
  107. regulator-min-microvolt = <1800000>;
  108. regulator-max-microvolt = <3300000>;
  109. regulator-always-on;
  110. regulator-boot-on;
  111. gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
  112. states = <1800000 0
  113. 3300000 1>;
  114. };
  115.  
  116. vdd_5v: fixedregulator-vdd_5v {
  117. compatible = "regulator-fixed";
  118. regulator-name = "vdd_5v";
  119. regulator-min-microvolt = <5000000>;
  120. regulator-max-microvolt = <5000000>;
  121. regulator-always-on;
  122. regulator-boot-on;
  123. };
  124.  
  125. vtt_fixed: fixedregulator-vtt {
  126. /* TPS51200 */
  127. compatible = "regulator-fixed";
  128. regulator-name = "vtt_fixed";
  129. vin-supply = <&vdd_ddr>;
  130. regulator-min-microvolt = <3300000>;
  131. regulator-max-microvolt = <3300000>;
  132. regulator-always-on;
  133. regulator-boot-on;
  134. };
  135.  
  136. leds {
  137. compatible = "gpio-leds";
  138. pinctrl-names = "default";
  139. pinctrl-0 = <&led_pins_default>;
  140.  
  141. led0 {
  142. label = "beaglebone:green:usr0";
  143. gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
  144. linux,default-trigger = "heartbeat";
  145. default-state = "off";
  146. };
  147.  
  148. led1 {
  149. label = "beaglebone:green:usr1";
  150. gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
  151. linux,default-trigger = "mmc0";
  152. default-state = "off";
  153. };
  154.  
  155. led2 {
  156. label = "beaglebone:green:usr2";
  157. gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
  158. linux,default-trigger = "cpu";
  159. default-state = "off";
  160. };
  161.  
  162. led3 {
  163. label = "beaglebone:green:usr3";
  164. gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
  165. linux,default-trigger = "mmc1";
  166. default-state = "off";
  167. };
  168.  
  169. led4 {
  170. label = "beaglebone:green:usr4";
  171. gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;
  172. linux,default-trigger = "netdev";
  173. default-state = "off";
  174. };
  175. };
  176.  
  177. hdmi_conn: connector@0 {
  178. compatible = "hdmi-connector";
  179. label = "hdmi";
  180. type = "a";
  181.  
  182. port {
  183. hdmi_connector_in: endpoint {
  184. remote-endpoint = <&hdmi_encoder_out>;
  185. };
  186. };
  187. };
  188.  
  189. hdmi_enc: encoder@0 {
  190. /* "ti,tpd12s016" software compatible with "ti,tpd12s015"
  191. * no need for individual driver
  192. */
  193. compatible = "ti,tpd12s015";
  194. gpios = <0>,
  195. <0>,
  196. <&gpio7 12 GPIO_ACTIVE_HIGH>;
  197.  
  198. ports {
  199. #address-cells = <0x1>;
  200. #size-cells = <0x0>;
  201.  
  202. port@0 {
  203. reg = <0x0>;
  204.  
  205. hdmi_encoder_in: endpoint@0 {
  206. remote-endpoint = <&hdmi_out>;
  207. };
  208. };
  209.  
  210. port@1 {
  211. reg = <0x1>;
  212.  
  213. hdmi_encoder_out: endpoint@0 {
  214. remote-endpoint = <&hdmi_connector_in>;
  215. };
  216. };
  217. };
  218. };
  219.  
  220. emmc_pwrseq: emmc_pwrseq {
  221. compatible = "mmc-pwrseq-emmc";
  222. reset-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>;
  223. pinctrl-names = "default";
  224. pinctrl-0 = <&emmc_pwrseq_pins_default>;
  225. };
  226.  
  227. brcmf_pwrseq: brcmf_pwrseq {
  228. compatible = "mmc-pwrseq-simple";
  229. pinctrl-names = "default";
  230. pinctrl-0 = <&brcmf_pwrseq_pins_default>;
  231. reset-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>, /* BT-REG-ON */
  232. <&gpio3 18 GPIO_ACTIVE_LOW>; /* WL-REG-ON */
  233. };
  234.  
  235. unused_pins: unused_pins {
  236. compatible = "gpio-leds";
  237. pinctrl-names = "default";
  238. pinctrl-0 = <&unused_pins_default>;
  239. };
  240.  
  241. cape_pins: cape_pins {
  242. compatible = "gpio-leds";
  243. pinctrl-names = "default";
  244. pinctrl-0 = <&cape_pins_default>;
  245. };
  246.  
  247. extcon_usb1: extcon_usb1 {
  248. compatible = "linux,extcon-usb-gpio";
  249. ti,enable-id-detection;
  250. id-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>;
  251. pinctrl-names = "default";
  252. pinctrl-0 = <&extcon_usb1_pins_default>;
  253. };
  254. };
  255.  
  256. &ocp {
  257. pruss1_shmem: pruss_shmem@4b200000 {
  258. status = "okay";
  259. compatible = "ti,pruss-shmem";
  260. reg = <0x4b200000 0x020000>;
  261. };
  262.  
  263. pruss2_shmem: pruss_shmem@4b280000 {
  264. status = "okay";
  265. compatible = "ti,pruss-shmem";
  266. reg = <0x4b280000 0x020000>;
  267. };
  268.  
  269. cape-universal {
  270. compatible = "gpio-of-helper";
  271. status = "okay";
  272. pinctrl-names = "default";
  273. pinctrl-0 = <>;
  274.  
  275. P8_03 {
  276. gpio-name = "P8_03";
  277. gpio = <&gpio1 24 0>;
  278. input;
  279. dir-changeable;
  280. };
  281.  
  282. P8_04 {
  283. gpio-name = "P8_04";
  284. gpio = <&gpio1 25 0>;
  285. input;
  286. dir-changeable;
  287. };
  288.  
  289. P8_05 {
  290. gpio-name = "P8_05";
  291. gpio = <&gpio7 1 0>;
  292. input;
  293. dir-changeable;
  294. };
  295.  
  296. P8_06 {
  297. gpio-name = "P8_06";
  298. gpio = <&gpio7 2 0>;
  299. input;
  300. dir-changeable;
  301. };
  302.  
  303. P8_07 {
  304. gpio-name = "P8_07";
  305. gpio = <&gpio6 5 0>;
  306. input;
  307. dir-changeable;
  308. };
  309.  
  310. P8_08 {
  311. gpio-name = "P8_08";
  312. gpio = <&gpio6 6 0>;
  313. input;
  314. dir-changeable;
  315. };
  316.  
  317. P8_09 {
  318. gpio-name = "P8_09";
  319. gpio = <&gpio6 18 0>;
  320. input;
  321. dir-changeable;
  322. };
  323.  
  324. P8_10 {
  325. gpio-name = "P8_10";
  326. gpio = <&gpio6 4 0>;
  327. input;
  328. dir-changeable;
  329. };
  330.  
  331. P8_11 {
  332. gpio-name = "P8_11";
  333. gpio = <&gpio3 11 0>;
  334. input;
  335. dir-changeable;
  336. };
  337.  
  338. P8_12 {
  339. gpio-name = "P8_12";
  340. gpio = <&gpio3 10 0>;
  341. input;
  342. dir-changeable;
  343. };
  344.  
  345. P8_13 {
  346. gpio-name = "P8_13";
  347. gpio = <&gpio4 11 0>;
  348. input;
  349. dir-changeable;
  350. };
  351.  
  352. P8_14 {
  353. gpio-name = "P8_14";
  354. gpio = <&gpio4 13 0>;
  355. input;
  356. dir-changeable;
  357. };
  358.  
  359. P8_15 {
  360. gpio-name = "P8_15";
  361. gpio = <&gpio4 3 0>;
  362. input;
  363. dir-changeable;
  364. };
  365.  
  366. P8_16 {
  367. gpio-name = "P8_16";
  368. gpio = <&gpio4 29 0>;
  369. input;
  370. dir-changeable;
  371. };
  372.  
  373. P8_17 {
  374. gpio-name = "P8_17";
  375. gpio = <&gpio8 18 0>;
  376. input;
  377. dir-changeable;
  378. };
  379.  
  380. P8_18 {
  381. gpio-name = "P8_18";
  382. gpio = <&gpio4 9 0>;
  383. input;
  384. dir-changeable;
  385. };
  386.  
  387. P8_19 {
  388. gpio-name = "P8_19";
  389. gpio = <&gpio4 10 0>;
  390. input;
  391. dir-changeable;
  392. };
  393.  
  394. P8_20 {
  395. gpio-name = "P8_20";
  396. gpio = <&gpio6 30 0>;
  397. input;
  398. dir-changeable;
  399. };
  400.  
  401. P8_21 {
  402. gpio-name = "P8_21";
  403. gpio = <&gpio6 29 0>;
  404. input;
  405. dir-changeable;
  406. };
  407.  
  408. P8_22 {
  409. gpio-name = "P8_22";
  410. gpio = <&gpio1 23 0>;
  411. input;
  412. dir-changeable;
  413. };
  414.  
  415. P8_23 {
  416. gpio-name = "P8_23";
  417. gpio = <&gpio1 22 0>;
  418. input;
  419. dir-changeable;
  420. };
  421.  
  422. P8_24 {
  423. gpio-name = "P8_24";
  424. gpio = <&gpio7 0 0>;
  425. input;
  426. dir-changeable;
  427. };
  428.  
  429. P8_25 {
  430. gpio-name = "P8_25";
  431. gpio = <&gpio6 31 0>;
  432. input;
  433. dir-changeable;
  434. };
  435.  
  436. P8_26 {
  437. gpio-name = "P8_26";
  438. gpio = <&gpio4 28 0>;
  439. input;
  440. dir-changeable;
  441. };
  442.  
  443. P8_27 {
  444. gpio-name = "P8_27";
  445. gpio = <&gpio4 23 0>;
  446. input;
  447. dir-changeable;
  448. };
  449.  
  450. P8_28 {
  451. gpio-name = "P8_28";
  452. gpio = <&gpio4 19 0>;
  453. input;
  454. dir-changeable;
  455. };
  456.  
  457. P8_29 {
  458. gpio-name = "P8_29";
  459. gpio = <&gpio4 22 0>;
  460. input;
  461. dir-changeable;
  462. };
  463.  
  464. P8_30 {
  465. gpio-name = "P8_30";
  466. gpio = <&gpio4 20 0>;
  467. input;
  468. dir-changeable;
  469. };
  470.  
  471. P8_31 {
  472. gpio-name = "P8_31";
  473. gpio = <&gpio8 14 0>;
  474. input;
  475. dir-changeable;
  476. };
  477.  
  478. P8_32 {
  479. gpio-name = "P8_32";
  480. gpio = <&gpio8 15 0>;
  481. input;
  482. dir-changeable;
  483. };
  484.  
  485. P8_33 {
  486. gpio-name = "P8_33";
  487. gpio = <&gpio8 13 0>;
  488. input;
  489. dir-changeable;
  490. };
  491.  
  492. P8_34 {
  493. gpio-name = "P8_34";
  494. gpio = <&gpio8 11 0>;
  495. input;
  496. dir-changeable;
  497. };
  498.  
  499. P8_35 {
  500. gpio-name = "P8_35";
  501. gpio = <&gpio8 12 0>;
  502. input;
  503. dir-changeable;
  504. };
  505.  
  506. P8_36 {
  507. gpio-name = "P8_36";
  508. gpio = <&gpio8 10 0>;
  509. input;
  510. dir-changeable;
  511. };
  512.  
  513. P8_37 {
  514. gpio-name = "P8_37";
  515. gpio = <&gpio8 8 0>;
  516. input;
  517. dir-changeable;
  518. };
  519.  
  520. P8_38 {
  521. gpio-name = "P8_38";
  522. gpio = <&gpio8 9 0>;
  523. input;
  524. dir-changeable;
  525. };
  526.  
  527. P8_39 {
  528. gpio-name = "P8_39";
  529. gpio = <&gpio8 6 0>;
  530. input;
  531. dir-changeable;
  532. };
  533.  
  534. P8_40 {
  535. gpio-name = "P8_40";
  536. gpio = <&gpio8 7 0>;
  537. input;
  538. dir-changeable;
  539. };
  540.  
  541. P8_41 {
  542. gpio-name = "P8_41";
  543. gpio = <&gpio8 4 0>;
  544. input;
  545. dir-changeable;
  546. };
  547.  
  548. P8_42 {
  549. gpio-name = "P8_42";
  550. gpio = <&gpio8 5 0>;
  551. input;
  552. dir-changeable;
  553. };
  554.  
  555. P8_43 {
  556. gpio-name = "P8_43";
  557. gpio = <&gpio8 2 0>;
  558. input;
  559. dir-changeable;
  560. };
  561.  
  562. P8_44 {
  563. gpio-name = "P8_44";
  564. gpio = <&gpio8 3 0>;
  565. input;
  566. dir-changeable;
  567. };
  568.  
  569. P8_45 {
  570. gpio-name = "P8_45";
  571. gpio = <&gpio8 0 0>;
  572. input;
  573. dir-changeable;
  574. };
  575.  
  576. P8_46 {
  577. gpio-name = "P8_46";
  578. gpio = <&gpio8 1 0>;
  579. input;
  580. dir-changeable;
  581. };
  582.  
  583. P9_11 {
  584. gpio-name = "P9_11";
  585. gpio = <&gpio8 17 0>;
  586. input;
  587. dir-changeable;
  588. };
  589.  
  590. P9_12 {
  591. gpio-name = "P9_12";
  592. gpio = <&gpio5 0 0>;
  593. input;
  594. dir-changeable;
  595. };
  596.  
  597. P9_13 {
  598. gpio-name = "P9_13";
  599. gpio = <&gpio6 12 0>;
  600. input;
  601. dir-changeable;
  602. };
  603.  
  604. P9_14 {
  605. gpio-name = "P9_14";
  606. gpio = <&gpio4 25 0>;
  607. input;
  608. dir-changeable;
  609. };
  610.  
  611. P9_15 {
  612. gpio-name = "P9_15";
  613. gpio = <&gpio3 12 0>;
  614. input;
  615. dir-changeable;
  616. };
  617.  
  618. P9_16 {
  619. gpio-name = "P9_16";
  620. gpio = <&gpio4 26 0>;
  621. input;
  622. dir-changeable;
  623. };
  624.  
  625. P9_17 {
  626. gpio-name = "P9_17";
  627. gpio = <&gpio7 17 0>;
  628. input;
  629. dir-changeable;
  630. };
  631.  
  632. P9_18 {
  633. gpio-name = "P9_18";
  634. gpio = <&gpio7 16 0>;
  635. input;
  636. dir-changeable;
  637. };
  638.  
  639. P9_19 {
  640. gpio-name = "P9_19";
  641. gpio = <&gpio7 3 0>;
  642. input;
  643. dir-changeable;
  644. };
  645.  
  646. P9_20 {
  647. gpio-name = "P9_20";
  648. gpio = <&gpio7 4 0>;
  649. input;
  650. dir-changeable;
  651. };
  652.  
  653. P9_21 {
  654. gpio-name = "P9_21";
  655. gpio = <&gpio3 3 0>;
  656. input;
  657. dir-changeable;
  658. };
  659.  
  660. P9_22 {
  661. gpio-name = "P9_22";
  662. gpio = <&gpio6 19 0>;
  663. input;
  664. dir-changeable;
  665. };
  666.  
  667. P9_23 {
  668. gpio-name = "P9_23";
  669. gpio = <&gpio7 11 0>;
  670. input;
  671. dir-changeable;
  672. };
  673.  
  674. P9_24 {
  675. gpio-name = "P9_24";
  676. gpio = <&gpio6 15 0>;
  677. input;
  678. dir-changeable;
  679. };
  680.  
  681. P9_25 {
  682. gpio-name = "P9_25";
  683. gpio = <&gpio6 17 0>;
  684. input;
  685. dir-changeable;
  686. };
  687.  
  688. P9_26 {
  689. gpio-name = "P9_26";
  690. gpio = <&gpio6 14 0>;
  691. input;
  692. dir-changeable;
  693. };
  694.  
  695. P9_27 {
  696. gpio-name = "P9_27";
  697. gpio = <&gpio6 15 0>;
  698. input;
  699. dir-changeable;
  700. };
  701.  
  702. P9_28 {
  703. gpio-name = "P9_28";
  704. gpio = <&gpio4 17 0>;
  705. input;
  706. dir-changeable;
  707. };
  708.  
  709. P9_29 {
  710. gpio-name = "P9_29";
  711. gpio = <&gpio5 11 0>;
  712. input;
  713. dir-changeable;
  714. };
  715.  
  716. P9_30 {
  717. gpio-name = "P9_30";
  718. gpio = <&gpio5 12 0>;
  719. input;
  720. dir-changeable;
  721. };
  722.  
  723. P9_31 {
  724. gpio-name = "P9_31";
  725. gpio = <&gpio5 10 0>;
  726. input;
  727. dir-changeable;
  728. };
  729.  
  730. P9_41 {
  731. gpio-name = "P9_41";
  732. gpio = <&gpio6 20 0>;
  733. input;
  734. dir-changeable;
  735. };
  736.  
  737. P9_42 {
  738. gpio-name = "P9_42";
  739. gpio = <&gpio4 18 0>;
  740. input;
  741. dir-changeable;
  742. };
  743. };
  744. };
  745.  
  746. &dra7_pmx_core {
  747. /************************/
  748. /* P8 Header */
  749. /************************/
  750.  
  751. /* P8_01 GND */
  752.  
  753. /* P8_02 GND */
  754.  
  755.  
  756. /* P8_03 (ball AB8) gpio1_24 */
  757. P8_03_default_pin: pinmux_P8_03_default_pin { pinctrl-single,pins = <
  758. DRA7XX_CORE_IOPAD(0x379C, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* mmc3_dat6.gpio1_24 */
  759. P8_03_gpio_pin: pinmux_P8_03_gpio_pin { pinctrl-single,pins = <
  760. DRA7XX_CORE_IOPAD(0x379C, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* mmc3_dat6.gpio1_24 */
  761. P8_03_gpio_pu_pin: pinmux_P8_03_gpio_pu_pin { pinctrl-single,pins = <
  762. DRA7XX_CORE_IOPAD(0x379C, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* mmc3_dat6.gpio1_24 */
  763. P8_03_gpio_pd_pin: pinmux_P8_03_gpio_pd_pin { pinctrl-single,pins = <
  764. DRA7XX_CORE_IOPAD(0x379C, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* mmc3_dat6.gpio1_24 */
  765. P8_03_gpio_input_pin: pinmux_P8_03_gpio_input_pin { pinctrl-single,pins = <
  766. DRA7XX_CORE_IOPAD(0x379C, PIN_INPUT | MUX_MODE14) >; }; /* mmc3_dat6.gpio1_24 */
  767.  
  768. /* P8_04 (ball AB5) gpio1_25 */
  769. P8_04_default_pin: pinmux_P8_04_default_pin { pinctrl-single,pins = <
  770. DRA7XX_CORE_IOPAD(0x37A0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* mmc3_dat7.gpio1_25 */
  771. P8_04_gpio_pin: pinmux_P8_04_gpio_pin { pinctrl-single,pins = <
  772. DRA7XX_CORE_IOPAD(0x37A0, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* mmc3_dat7.gpio1_25 */
  773. P8_04_gpio_pu_pin: pinmux_P8_04_gpio_pu_pin { pinctrl-single,pins = <
  774. DRA7XX_CORE_IOPAD(0x37A0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* mmc3_dat7.gpio1_25 */
  775. P8_04_gpio_pd_pin: pinmux_P8_04_gpio_pd_pin { pinctrl-single,pins = <
  776. DRA7XX_CORE_IOPAD(0x37A0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* mmc3_dat7.gpio1_25 */
  777. P8_04_gpio_input_pin: pinmux_P8_04_gpio_input_pin { pinctrl-single,pins = <
  778. DRA7XX_CORE_IOPAD(0x37A0, PIN_INPUT | MUX_MODE14) >; }; /* mmc3_dat7.gpio1_25 */
  779.  
  780. /* P8_05 (ball AC9) gpio7_1 */
  781. P8_05_default_pin: pinmux_P8_05_default_pin { pinctrl-single,pins = <
  782. DRA7XX_CORE_IOPAD(0x378C, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* mmc3_dat2.gpio7_1 */
  783. P8_05_gpio_pin: pinmux_P8_05_gpio_pin { pinctrl-single,pins = <
  784. DRA7XX_CORE_IOPAD(0x378C, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* mmc3_dat2.gpio7_1 */
  785. P8_05_gpio_pu_pin: pinmux_P8_05_gpio_pu_pin { pinctrl-single,pins = <
  786. DRA7XX_CORE_IOPAD(0x378C, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* mmc3_dat2.gpio7_1 */
  787. P8_05_gpio_pd_pin: pinmux_P8_05_gpio_pd_pin { pinctrl-single,pins = <
  788. DRA7XX_CORE_IOPAD(0x378C, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* mmc3_dat2.gpio7_1 */
  789. P8_05_gpio_input_pin: pinmux_P8_05_gpio_input_pin { pinctrl-single,pins = <
  790. DRA7XX_CORE_IOPAD(0x378C, PIN_INPUT | MUX_MODE14) >; }; /* mmc3_dat2.gpio7_1 */
  791.  
  792. /* P8_06 (ball AC3) gpio7_2 */
  793. P8_06_default_pin: pinmux_P8_06_default_pin { pinctrl-single,pins = <
  794. DRA7XX_CORE_IOPAD(0x3790, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* mmc3_dat3.gpio7_2 */
  795. P8_06_gpio_pin: pinmux_P8_06_gpio_pin { pinctrl-single,pins = <
  796. DRA7XX_CORE_IOPAD(0x3790, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* mmc3_dat3.gpio7_2 */
  797. P8_06_gpio_pu_pin: pinmux_P8_06_gpio_pu_pin { pinctrl-single,pins = <
  798. DRA7XX_CORE_IOPAD(0x3790, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* mmc3_dat3.gpio7_2 */
  799. P8_06_gpio_pd_pin: pinmux_P8_06_gpio_pd_pin { pinctrl-single,pins = <
  800. DRA7XX_CORE_IOPAD(0x3790, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* mmc3_dat3.gpio7_2 */
  801. P8_06_gpio_input_pin: pinmux_P8_06_gpio_input_pin { pinctrl-single,pins = <
  802. DRA7XX_CORE_IOPAD(0x3790, PIN_INPUT | MUX_MODE14) >; }; /* mmc3_dat3.gpio7_2 */
  803.  
  804. /* P8_07 (ball G14) gpio6_5*/
  805. P8_07_default_pin: pinmux_P8_07_default_pin { pinctrl-single,pins = <
  806. DRA7XX_CORE_IOPAD(0x36EC, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_axr14.gpio6_5 */
  807. P8_07_gpio_pin: pinmux_P8_07_gpio_pin { pinctrl-single,pins = <
  808. DRA7XX_CORE_IOPAD(0x36EC, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_axr14.gpio6_5 */
  809. P8_07_gpio_pu_pin: pinmux_P8_07_gpio_pu_pin { pinctrl-single,pins = <
  810. DRA7XX_CORE_IOPAD(0x36EC, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_axr14.gpio6_5 */
  811. P8_07_gpio_pd_pin: pinmux_P8_07_gpio_pd_pin { pinctrl-single,pins = <
  812. DRA7XX_CORE_IOPAD(0x36EC, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_axr14.gpio6_5 */
  813. P8_07_gpio_input_pin: pinmux_P8_07_gpio_input_pin { pinctrl-single,pins = <
  814. DRA7XX_CORE_IOPAD(0x36EC, PIN_INPUT | MUX_MODE14) >; }; /* mcasp1_axr14.gpio6_5 */
  815. P8_07_timer_pin: pinmux_P8_07_timer_pin { pinctrl-single,pins = <
  816. DRA7XX_CORE_IOPAD(0x36EC, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE10) >; }; /* mcasp1_axr14.timer11 */
  817.  
  818. /* P8_08 (ball F14) gpio6_6 */
  819. P8_08_default_pin: pinmux_P8_08_default_pin { pinctrl-single,pins = <
  820. DRA7XX_CORE_IOPAD(0x36F0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_axr15.gpio6_6 */
  821. P8_08_gpio_pin: pinmux_P8_08_gpio_pin { pinctrl-single,pins = <
  822. DRA7XX_CORE_IOPAD(0x36F0, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_axr15.gpio6_6 */
  823. P8_08_gpio_pu_pin: pinmux_P8_08_gpio_pu_pin { pinctrl-single,pins = <
  824. DRA7XX_CORE_IOPAD(0x36F0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_axr15.gpio6_6 */
  825. P8_08_gpio_pd_pin: pinmux_P8_08_gpio_pd_pin { pinctrl-single,pins = <
  826. DRA7XX_CORE_IOPAD(0x36F0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_axr15.gpio6_6 */
  827. P8_08_gpio_input_pin: pinmux_P8_08_gpio_input_pin { pinctrl-single,pins = <
  828. DRA7XX_CORE_IOPAD(0x36F0, PIN_INPUT | MUX_MODE14) >; }; /* mcasp1_axr15.gpio6_6 */
  829. P8_08_timer_pin: pinmux_P8_08_timer_pin { pinctrl-single,pins = <
  830. DRA7XX_CORE_IOPAD(0x36F0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE10) >; }; /* mcasp1_axr15.timer12 */
  831.  
  832. /* P8_09 (ball E17) gpio6_18 */
  833. P8_09_default_pin: pinmux_P8_09_default_pin { pinctrl-single,pins = <
  834. DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* xref_clk1.gpio6_18 */
  835. P8_09_gpio_pin: pinmux_P8_09_gpio_pin { pinctrl-single,pins = <
  836. DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* xref_clk1.gpio6_18 */
  837. P8_09_gpio_pu_pin: pinmux_P8_09_gpio_pu_pin { pinctrl-single,pins = <
  838. DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* xref_clk1.gpio6_18 */
  839. P8_09_gpio_pd_pin: pinmux_P8_09_gpio_pd_pin { pinctrl-single,pins = <
  840. DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* xref_clk1.gpio6_18 */
  841. P8_09_gpio_input_pin: pinmux_P8_09_gpio_input_pin { pinctrl-single,pins = <
  842. DRA7XX_CORE_IOPAD(0x3698, PIN_INPUT | MUX_MODE14) >; }; /* xref_clk1.gpio6_18 */
  843. P8_09_timer_pin: pinmux_P8_09_timer_pin { pinctrl-single,pins = <
  844. DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE10) >; }; /* xref_clk1.timer14 */
  845.  
  846. /* P8_10 (ball A13) gpio6_4 */
  847. P8_10_default_pin: pinmux_P8_10_default_pin { pinctrl-single,pins = <
  848. DRA7XX_CORE_IOPAD(0x36E8, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_axr13.gpio6_4 */
  849. P8_10_gpio_pin: pinmux_P8_10_gpio_pin { pinctrl-single,pins = <
  850. DRA7XX_CORE_IOPAD(0x36E8, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_axr13.gpio6_4 */
  851. P8_10_gpio_pu_pin: pinmux_P8_10_gpio_pu_pin { pinctrl-single,pins = <
  852. DRA7XX_CORE_IOPAD(0x36E8, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_axr13.gpio6_4 */
  853. P8_10_gpio_pd_pin: pinmux_P8_10_gpio_pd_pin { pinctrl-single,pins = <
  854. DRA7XX_CORE_IOPAD(0x36E8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_axr13.gpio6_4 */
  855. P8_10_gpio_input_pin: pinmux_P8_10_gpio_input_pin { pinctrl-single,pins = <
  856. DRA7XX_CORE_IOPAD(0x36E8, PIN_INPUT | MUX_MODE14) >; }; /* mcasp1_axr13.gpio6_4 */
  857. P8_10_timer_pin: pinmux_P8_10_timer_pin { pinctrl-single,pins = <
  858. DRA7XX_CORE_IOPAD(0x36E8, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE10) >; }; /* mcasp1_axr13.timer10 */
  859.  
  860. /* P8_11 (ball AH4) gpio3_11 */
  861. P8_11_default_pin: pinmux_P8_11_default_pin { pinctrl-single,pins = <
  862. DRA7XX_CORE_IOPAD(0x3510, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vin1a_d7.gpio3_11 */
  863. P8_11_gpio_pin: pinmux_P8_11_gpio_pin { pinctrl-single,pins = <
  864. DRA7XX_CORE_IOPAD(0x3510, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vin1a_d7.gpio3_11 */
  865. P8_11_gpio_pu_pin: pinmux_P8_11_gpio_pu_pin { pinctrl-single,pins = <
  866. DRA7XX_CORE_IOPAD(0x3510, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vin1a_d7.gpio3_11 */
  867. P8_11_gpio_pd_pin: pinmux_P8_11_gpio_pd_pin { pinctrl-single,pins = <
  868. DRA7XX_CORE_IOPAD(0x3510, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vin1a_d7.gpio3_11 */
  869. P8_11_gpio_input_pin: pinmux_P8_11_gpio_input_pin { pinctrl-single,pins = <
  870. DRA7XX_CORE_IOPAD(0x3510, PIN_INPUT | MUX_MODE14) >; }; /* vin1a_d7.gpio3_11 */
  871. P8_11_qep_pin: pinmux_P8_11_qep_pin { pinctrl-single,pins = <
  872. DRA7XX_CORE_IOPAD(0x3510, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE10) >; }; /* vin1a_d7.eQEP2B_in */
  873. P8_11_pruout_pin: pinmux_P8_11_pruout_pin { pinctrl-single,pins = <
  874. DRA7XX_CORE_IOPAD(0x3510, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE13) >; }; /* vin1a_d7.pr1_pru0_gpo4 */
  875.  
  876. /* P8_12 (ball AG6) gpio3_10 */
  877. P8_12_default_pin: pinmux_P8_12_default_pin { pinctrl-single,pins = <
  878. DRA7XX_CORE_IOPAD(0x350C, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vin1a_d6.gpio3_10 */
  879. P8_12_gpio_pin: pinmux_P8_12_gpio_pin { pinctrl-single,pins = <
  880. DRA7XX_CORE_IOPAD(0x350C, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vin1a_d6.gpio3_10 */
  881. P8_12_gpio_pu_pin: pinmux_P8_12_gpio_pu_pin { pinctrl-single,pins = <
  882. DRA7XX_CORE_IOPAD(0x350C, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vin1a_d6.gpio3_10 */
  883. P8_12_gpio_pd_pin: pinmux_P8_12_gpio_pd_pin { pinctrl-single,pins = <
  884. DRA7XX_CORE_IOPAD(0x350C, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vin1a_d6.gpio3_10 */
  885. P8_12_gpio_input_pin: pinmux_P8_12_gpio_input_pin { pinctrl-single,pins = <
  886. DRA7XX_CORE_IOPAD(0x350C, PIN_INPUT | MUX_MODE14) >; }; /* vin1a_d6.gpio3_10 */
  887. P8_12_qep_pin: pinmux_P8_12_qep_pin { pinctrl-single,pins = <
  888. DRA7XX_CORE_IOPAD(0x350C, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE10) >; }; /* vin1a_d6.eQEP2A_in */
  889. P8_12_pruout_pin: pinmux_P8_12_pruout_pin { pinctrl-single,pins = <
  890. DRA7XX_CORE_IOPAD(0x350C, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE13) >; }; /* vin1a_d6.pr1_pru0_gpo3 */
  891.  
  892. /* P8_13 (ball D3) gpio4_11 */
  893. P8_13_default_pin: pinmux_P8_13_default_pin { pinctrl-single,pins = <
  894. DRA7XX_CORE_IOPAD(0x3590, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d10.gpio4_11 */
  895. P8_13_gpio_pin: pinmux_P8_13_gpio_pin { pinctrl-single,pins = <
  896. DRA7XX_CORE_IOPAD(0x3590, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d10.gpio4_11 */
  897. P8_13_gpio_pu_pin: pinmux_P8_13_gpio_pu_pin { pinctrl-single,pins = <
  898. DRA7XX_CORE_IOPAD(0x3590, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d10.gpio4_11 */
  899. P8_13_gpio_pd_pin: pinmux_P8_13_gpio_pd_pin { pinctrl-single,pins = <
  900. DRA7XX_CORE_IOPAD(0x3590, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d10.gpio4_11 */
  901. P8_13_gpio_input_pin: pinmux_P8_13_gpio_input_pin { pinctrl-single,pins = <
  902. DRA7XX_CORE_IOPAD(0x3590, PIN_INPUT | MUX_MODE14) >; }; /* vin2a_d10.gpio4_11 */
  903. P8_13_pwm_pin: pinmux_P8_13_pwm_pin { pinctrl-single,pins = <
  904. DRA7XX_CORE_IOPAD(0x3590, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE10) >; }; /* vin2a_d10.ehrpwm2B */
  905.  
  906. /* P8_14 (ball D5) gpio4_13*/
  907. P8_14_default_pin: pinmux_P8_14_default_pin { pinctrl-single,pins = <
  908. DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d12.gpio4_13 */
  909. P8_14_gpio_pin: pinmux_P8_14_gpio_pin { pinctrl-single,pins = <
  910. DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d12.gpio4_13 */
  911. P8_14_gpio_pu_pin: pinmux_P8_14_gpio_pu_pin { pinctrl-single,pins = <
  912. DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d12.gpio4_13 */
  913. P8_14_gpio_pd_pin: pinmux_P8_14_gpio_pd_pin { pinctrl-single,pins = <
  914. DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d12.gpio4_13 */
  915. P8_14_gpio_input_pin: pinmux_P8_14_gpio_input_pin { pinctrl-single,pins = <
  916. DRA7XX_CORE_IOPAD(0x3598, PIN_INPUT | MUX_MODE14) >; }; /* vin2a_d12.gpio4_13 */
  917. P8_14_pwm_pin: pinmux_P8_14_pwm_pin { pinctrl-single,pins = <
  918. DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE10) >; }; /* vin2a_d12.eCAP2_in_PWM2_out */
  919.  
  920. /* P8_15a (ball D1) gpio4_3*/
  921. P8_15_default_pin: pinmux_P8_15_default_pin { pinctrl-single,pins = <
  922. DRA7XX_CORE_IOPAD(0x3570, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d2.gpio4_3 */
  923. P8_15_gpio_pin: pinmux_P8_15_gpio_pin { pinctrl-single,pins = <
  924. DRA7XX_CORE_IOPAD(0x3570, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d2.gpio4_3 */
  925. P8_15_gpio_pu_pin: pinmux_P8_15_gpio_pu_pin { pinctrl-single,pins = <
  926. DRA7XX_CORE_IOPAD(0x3570, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d2.gpio4_3 */
  927. P8_15_gpio_pd_pin: pinmux_P8_15_gpio_pd_pin { pinctrl-single,pins = <
  928. DRA7XX_CORE_IOPAD(0x3570, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d2.gpio4_3 */
  929. P8_15_gpio_input_pin: pinmux_P8_15_gpio_input_pin { pinctrl-single,pins = <
  930. DRA7XX_CORE_IOPAD(0x3570, PIN_INPUT | MUX_MODE14) >; }; /* vin2a_d2.gpio4_3 */
  931. P8_15_pru_ecap_pin: pinmux_P8_15_pru_ecap_pin { pinctrl-single,pins = <
  932. DRA7XX_CORE_IOPAD(0x3570, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE11) >; }; /* vin2a_d2.pr1_ecap0_ecap_capin_apwm_o */
  933.  
  934. /* P8_15b (ball A3) gpio4_27 */
  935. P8_15_pruin_pin: pinmux_P8_15_pruin_pin { pinctrl-single,pins = <
  936. DRA7XX_CORE_IOPAD(0x35B4, PIN_INPUT | MUX_MODE12) >; }; /* vin2a_d19.pr1_pru1_gpi16*/
  937.  
  938. /* P8_16 (ball B4) gpio4_29 */
  939. P8_16_default_pin: pinmux_P8_16_default_pin { pinctrl-single,pins = <
  940. DRA7XX_CORE_IOPAD(0x35BC, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d21.gpio4_29 */
  941. P8_16_gpio_pin: pinmux_P8_16_gpio_pin { pinctrl-single,pins = <
  942. DRA7XX_CORE_IOPAD(0x35BC, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d21.gpio4_29 */
  943. P8_16_gpio_pu_pin: pinmux_P8_16_gpio_pu_pin { pinctrl-single,pins = <
  944. DRA7XX_CORE_IOPAD(0x35BC, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d21.gpio4_29 */
  945. P8_16_gpio_pd_pin: pinmux_P8_16_gpio_pd_pin { pinctrl-single,pins = <
  946. DRA7XX_CORE_IOPAD(0x35BC, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d21.gpio4_29 */
  947. P8_16_gpio_input_pin: pinmux_P8_16_gpio_input_pin { pinctrl-single,pins = <
  948. DRA7XX_CORE_IOPAD(0x35BC, PIN_INPUT | MUX_MODE14) >; }; /* vin2a_d21.gpio4_29 */
  949. P8_16_pruin_pin: pinmux_P8_16_pruin_pin { pinctrl-single,pins = <
  950. DRA7XX_CORE_IOPAD(0x35BC, PIN_INPUT | MUX_MODE12) >; }; /* vin2a_d21.pr1_pru1_gpi18 */
  951.  
  952. /* P8_17 (ball A7) gpio8_18 */
  953. P8_17_default_pin: pinmux_P8_17_default_pin { pinctrl-single,pins = <
  954. DRA7XX_CORE_IOPAD(0x3624, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_d18.gpio8_18 */
  955. P8_17_gpio_pin: pinmux_P8_17_gpio_pin { pinctrl-single,pins = <
  956. DRA7XX_CORE_IOPAD(0x3624, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vout1_d18.gpio8_18 */
  957. P8_17_gpio_pu_pin: pinmux_P8_17_gpio_pu_pin { pinctrl-single,pins = <
  958. DRA7XX_CORE_IOPAD(0x3624, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vout1_d18.gpio8_18 */
  959. P8_17_gpio_pd_pin: pinmux_P8_17_gpio_pd_pin { pinctrl-single,pins = <
  960. DRA7XX_CORE_IOPAD(0x3624, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_d18.gpio8_18 */
  961. P8_17_gpio_input_pin: pinmux_P8_17_gpio_input_pin { pinctrl-single,pins = <
  962. DRA7XX_CORE_IOPAD(0x3624, PIN_INPUT | MUX_MODE14) >; }; /* vout1_d18.gpio8_18 */
  963.  
  964. /* P8_18 (ball F5) gpio4_9 */
  965. P8_18_default_pin: pinmux_P8_18_default_pin { pinctrl-single,pins = <
  966. DRA7XX_CORE_IOPAD(0x3588, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d8.gpio4_9 */
  967. P8_18_gpio_pin: pinmux_P8_18_gpio_pin { pinctrl-single,pins = <
  968. DRA7XX_CORE_IOPAD(0x3588, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d8.gpio4_9 */
  969. P8_18_gpio_pu_pin: pinmux_P8_18_gpio_pu_pin { pinctrl-single,pins = <
  970. DRA7XX_CORE_IOPAD(0x3588, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d8.gpio4_9 */
  971. P8_18_gpio_pd_pin: pinmux_P8_18_gpio_pd_pin { pinctrl-single,pins = <
  972. DRA7XX_CORE_IOPAD(0x3588, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d8.gpio4_9 */
  973. P8_18_gpio_input_pin: pinmux_P8_18_gpio_input_pin { pinctrl-single,pins = <
  974. DRA7XX_CORE_IOPAD(0x3588, PIN_INPUT | MUX_MODE14) >; }; /* vin2a_d8.gpio4_9 */
  975. P8_18_qep_pin: pinmux_P8_18_qep_pin { pinctrl-single,pins = <
  976. DRA7XX_CORE_IOPAD(0x3588, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE10) >; }; /* vin2a_d8.eQEP2_strobe */
  977.  
  978. /* P8_19 (ball E6) gpio4_10 */
  979. P8_19_default_pin: pinmux_P8_19_default_pin { pinctrl-single,pins = <
  980. DRA7XX_CORE_IOPAD(0x358C, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d9.gpio4_10 */
  981. P8_19_gpio_pin: pinmux_P8_19_gpio_pin { pinctrl-single,pins = <
  982. DRA7XX_CORE_IOPAD(0x358C, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d9.gpio4_10 */
  983. P8_19_gpio_pu_pin: pinmux_P8_19_gpio_pu_pin { pinctrl-single,pins = <
  984. DRA7XX_CORE_IOPAD(0x358C, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d9.gpio4_10 */
  985. P8_19_gpio_pd_pin: pinmux_P8_19_gpio_pd_pin { pinctrl-single,pins = <
  986. DRA7XX_CORE_IOPAD(0x358C, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d9.gpio4_10 */
  987. P8_19_gpio_input_pin: pinmux_P8_19_gpio_input_pin { pinctrl-single,pins = <
  988. DRA7XX_CORE_IOPAD(0x358C, PIN_INPUT | MUX_MODE14) >; }; /* vin2a_d9.gpio4_10 */
  989. P8_19_pwm_pin: pinmux_P8_19_pwm_pin { pinctrl-single,pins = <
  990. DRA7XX_CORE_IOPAD(0x358C, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE10) >; }; /* vin2a_d9.ehrpwm2A */
  991.  
  992. /* P8_20 (ball AC4) gpio6_30 */
  993. P8_20_default_pin: pinmux_P8_20_default_pin { pinctrl-single,pins = <
  994. DRA7XX_CORE_IOPAD(0x3780, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* mmc3_cmd.gpio6_30 */
  995. P8_20_gpio_pin: pinmux_P8_20_gpio_pin { pinctrl-single,pins = <
  996. DRA7XX_CORE_IOPAD(0x3780, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* mmc3_cmd.gpio6_30 */
  997. P8_20_gpio_pu_pin: pinmux_P8_20_gpio_pu_pin { pinctrl-single,pins = <
  998. DRA7XX_CORE_IOPAD(0x3780, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* mmc3_cmd.gpio6_30 */
  999. P8_20_gpio_pd_pin: pinmux_P8_20_gpio_pd_pin { pinctrl-single,pins = <
  1000. DRA7XX_CORE_IOPAD(0x3780, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* mmc3_cmd.gpio6_30 */
  1001. P8_20_gpio_input_pin: pinmux_P8_20_gpio_input_pin { pinctrl-single,pins = <
  1002. DRA7XX_CORE_IOPAD(0x3780, PIN_INPUT | MUX_MODE14) >; }; /* mmc3_cmd.gpio6_30 */
  1003. P8_20_pruout_pin: pinmux_P8_20_pruout_pin { pinctrl-single,pins = <
  1004. DRA7XX_CORE_IOPAD(0x3780, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE13) >; }; /* mmc3_cmd.pr2_pru0_gpo3 */
  1005. P8_20_pruin_pin: pinmux_P8_20_pruin_pin { pinctrl-single,pins = <
  1006. DRA7XX_CORE_IOPAD(0x3780, PIN_INPUT | MUX_MODE12) >; }; /* mmc3_cmd.pr2_pru0_gpi3 */
  1007.  
  1008. /* P8_21 (ball AD4) gpio6_29 */
  1009. P8_21_default_pin: pinmux_P8_21_default_pin { pinctrl-single,pins = <
  1010. DRA7XX_CORE_IOPAD(0x377C, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* mmc3_clk.gpio6_29 */
  1011. P8_21_gpio_pin: pinmux_P8_21_gpio_pin { pinctrl-single,pins = <
  1012. DRA7XX_CORE_IOPAD(0x377C, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* mmc3_clk.gpio6_29 */
  1013. P8_21_gpio_pu_pin: pinmux_P8_21_gpio_pu_pin { pinctrl-single,pins = <
  1014. DRA7XX_CORE_IOPAD(0x377C, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* mmc3_clk.gpio6_29 */
  1015. P8_21_gpio_pd_pin: pinmux_P8_21_gpio_pd_pin { pinctrl-single,pins = <
  1016. DRA7XX_CORE_IOPAD(0x377C, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* mmc3_clk.gpio6_29 */
  1017. P8_21_gpio_input_pin: pinmux_P8_21_gpio_input_pin { pinctrl-single,pins = <
  1018. DRA7XX_CORE_IOPAD(0x377C, PIN_INPUT | MUX_MODE14) >; }; /* mmc3_clk.gpio6_29 */
  1019. P8_21_pruout_pin: pinmux_P8_21_pruout_pin { pinctrl-single,pins = <
  1020. DRA7XX_CORE_IOPAD(0x377C, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE13) >; }; /* mmc3_clk.pr2_pru0_gpo2 */
  1021. P8_21_pruin_pin: pinmux_P8_21_pruin_pin { pinctrl-single,pins = <
  1022. DRA7XX_CORE_IOPAD(0x377C, PIN_INPUT | MUX_MODE12) >; }; /* mmc3_clk.pr2_pru0_gpi2 */
  1023.  
  1024. /* P8_22 (ball AD6) gpio1_23 */
  1025. P8_22_default_pin: pinmux_P8_22_default_pin { pinctrl-single,pins = <
  1026. DRA7XX_CORE_IOPAD(0x3798, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* mmc3_dat5.gpio1_23 */
  1027. P8_22_gpio_pin: pinmux_P8_22_gpio_pin { pinctrl-single,pins = <
  1028. DRA7XX_CORE_IOPAD(0x3798, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* mmc3_dat5.gpio1_23 */
  1029. P8_22_gpio_pu_pin: pinmux_P8_22_gpio_pu_pin { pinctrl-single,pins = <
  1030. DRA7XX_CORE_IOPAD(0x3798, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* mmc3_dat5.gpio1_23 */
  1031. P8_22_gpio_pd_pin: pinmux_P8_22_gpio_pd_pin { pinctrl-single,pins = <
  1032. DRA7XX_CORE_IOPAD(0x3798, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* mmc3_dat5.gpio1_23 */
  1033. P8_22_gpio_input_pin: pinmux_P8_22_gpio_input_pin { pinctrl-single,pins = <
  1034. DRA7XX_CORE_IOPAD(0x3798, PIN_INPUT | MUX_MODE14) >; }; /* mmc3_dat5.gpio1_23 */
  1035.  
  1036. /* P8_23 (ball AC8) gpio1_22 */
  1037. P8_23_default_pin: pinmux_P8_23_default_pin { pinctrl-single,pins = <
  1038. DRA7XX_CORE_IOPAD(0x3794, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* mmc3_dat4.gpio1_22 */
  1039. P8_23_gpio_pin: pinmux_P8_23_gpio_pin { pinctrl-single,pins = <
  1040. DRA7XX_CORE_IOPAD(0x3794, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* mmc3_dat4.gpio1_22 */
  1041. P8_23_gpio_pu_pin: pinmux_P8_23_gpio_pu_pin { pinctrl-single,pins = <
  1042. DRA7XX_CORE_IOPAD(0x3794, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* mmc3_dat4.gpio1_22 */
  1043. P8_23_gpio_pd_pin: pinmux_P8_23_gpio_pd_pin { pinctrl-single,pins = <
  1044. DRA7XX_CORE_IOPAD(0x3794, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* mmc3_dat4.gpio1_22 */
  1045. P8_23_gpio_input_pin: pinmux_P8_23_gpio_input_pin { pinctrl-single,pins = <
  1046. DRA7XX_CORE_IOPAD(0x3794, PIN_INPUT | MUX_MODE14) >; }; /* mmc3_dat4.gpio1_22 */
  1047.  
  1048. /* P8_24 (ball AC6) gpio7_0 */
  1049. P8_24_default_pin: pinmux_P8_24_default_pin { pinctrl-single,pins = <
  1050. DRA7XX_CORE_IOPAD(0x3788, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* mmc3_dat1.gpio7_0 */
  1051. P8_24_gpio_pin: pinmux_P8_24_gpio_pin { pinctrl-single,pins = <
  1052. DRA7XX_CORE_IOPAD(0x3788, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* mmc3_dat1.gpio7_0 */
  1053. P8_24_gpio_pu_pin: pinmux_P8_24_gpio_pu_pin { pinctrl-single,pins = <
  1054. DRA7XX_CORE_IOPAD(0x3788, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* mmc3_dat1.gpio7_0 */
  1055. P8_24_gpio_pd_pin: pinmux_P8_24_gpio_pd_pin { pinctrl-single,pins = <
  1056. DRA7XX_CORE_IOPAD(0x3788, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* mmc3_dat1.gpio7_0 */
  1057. P8_24_gpio_input_pin: pinmux_P8_24_gpio_input_pin { pinctrl-single,pins = <
  1058. DRA7XX_CORE_IOPAD(0x3788, PIN_INPUT | MUX_MODE14) >; }; /* mmc3_dat1.gpio7_0 */
  1059.  
  1060. /* P8_25 (ball AC7) gpio6_31 */
  1061. P8_25_default_pin: pinmux_P8_25_default_pin { pinctrl-single,pins = <
  1062. DRA7XX_CORE_IOPAD(0x3784, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* mmc3_dat0.gpio6_31 */
  1063. P8_25_gpio_pin: pinmux_P8_25_gpio_pin { pinctrl-single,pins = <
  1064. DRA7XX_CORE_IOPAD(0x3784, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* mmc3_dat0.gpio6_31 */
  1065. P8_25_gpio_pu_pin: pinmux_P8_25_gpio_pu_pin { pinctrl-single,pins = <
  1066. DRA7XX_CORE_IOPAD(0x3784, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* mmc3_dat0.gpio6_31 */
  1067. P8_25_gpio_pd_pin: pinmux_P8_25_gpio_pd_pin { pinctrl-single,pins = <
  1068. DRA7XX_CORE_IOPAD(0x3784, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* mmc3_dat0.gpio6_31 */
  1069. P8_25_gpio_input_pin: pinmux_P8_25_gpio_input_pin { pinctrl-single,pins = <
  1070. DRA7XX_CORE_IOPAD(0x3784, PIN_INPUT | MUX_MODE14) >; }; /* mmc3_dat0.gpio6_31 */
  1071.  
  1072. /* P8_26 (ball B3) gpio4_28 */
  1073. P8_26_default_pin: pinmux_P8_26_default_pin { pinctrl-single,pins = <
  1074. DRA7XX_CORE_IOPAD(0x35B8, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d20.gpio4_28 */
  1075. P8_26_gpio_pin: pinmux_P8_26_gpio_pin { pinctrl-single,pins = <
  1076. DRA7XX_CORE_IOPAD(0x35B8, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d20.gpio4_28 */
  1077. P8_26_gpio_pu_pin: pinmux_P8_26_gpio_pu_pin { pinctrl-single,pins = <
  1078. DRA7XX_CORE_IOPAD(0x35B8, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d20.gpio4_28 */
  1079. P8_26_gpio_pd_pin: pinmux_P8_26_gpio_pd_pin { pinctrl-single,pins = <
  1080. DRA7XX_CORE_IOPAD(0x35B8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d20.gpio4_28 */
  1081. P8_26_gpio_input_pin: pinmux_P8_26_gpio_input_pin { pinctrl-single,pins = <
  1082. DRA7XX_CORE_IOPAD(0x35B8, PIN_INPUT | MUX_MODE14) >; }; /* vin2a_d20.gpio4_28 */
  1083.  
  1084. /* P8_27a (ball E11) gpio4_23 */
  1085. P8_27_default_pin: pinmux_P8_27_default_pin { pinctrl-single,pins = <
  1086. DRA7XX_CORE_IOPAD(0x35D8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_vsync.gpio4_23 */
  1087. P8_27_gpio_pin: pinmux_P8_27_gpio_pin { pinctrl-single,pins = <
  1088. DRA7XX_CORE_IOPAD(0x35D8, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vout1_vsync.gpio4_23 */
  1089. P8_27_gpio_pu_pin: pinmux_P8_27_gpio_pu_pin { pinctrl-single,pins = <
  1090. DRA7XX_CORE_IOPAD(0x35D8, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vout1_vsync.gpio4_23 */
  1091. P8_27_gpio_pd_pin: pinmux_P8_27_gpio_pd_pin { pinctrl-single,pins = <
  1092. DRA7XX_CORE_IOPAD(0x35D8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_vsync.gpio4_23 */
  1093. P8_27_gpio_input_pin: pinmux_P8_27_gpio_input_pin { pinctrl-single,pins = <
  1094. DRA7XX_CORE_IOPAD(0x35D8, PIN_INPUT | MUX_MODE14) >; }; /* vout1_vsync.gpio4_23 */
  1095.  
  1096. /* P8_27b (ball A8) gpio8_19 */
  1097. P8_27_pruout_pin: pinmux_P8_27_pruout_pin { pinctrl-single,pins = <
  1098. DRA7XX_CORE_IOPAD(0x3628, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE13) >; }; /* vout1_d19.pr2_pru0_gpo16 */
  1099. P8_27_pruin_pin: pinmux_P8_27_pruin_pin { pinctrl-single,pins = <
  1100. DRA7XX_CORE_IOPAD(0x3628, PIN_INPUT | MUX_MODE12) >; }; /* vout1_d19.pr2_pru0_gpi16 */
  1101.  
  1102. /* P8_28a (ball D11) gpio4_19 */
  1103. P8_28_default_pin: pinmux_P8_28_default_pin { pinctrl-single,pins = <
  1104. DRA7XX_CORE_IOPAD(0x35C8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_clk.gpio4_19 */
  1105. P8_28_gpio_pin: pinmux_P8_28_gpio_pin { pinctrl-single,pins = <
  1106. DRA7XX_CORE_IOPAD(0x35C8, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vout1_clk.gpio4_19 */
  1107. P8_28_gpio_pu_pin: pinmux_P8_28_gpio_pu_pin { pinctrl-single,pins = <
  1108. DRA7XX_CORE_IOPAD(0x35C8, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vout1_clk.gpio4_19 */
  1109. P8_28_gpio_pd_pin: pinmux_P8_28_gpio_pd_pin { pinctrl-single,pins = <
  1110. DRA7XX_CORE_IOPAD(0x35C8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_clk.gpio4_19 */
  1111. P8_28_gpio_input_pin: pinmux_P8_28_gpio_input_pin { pinctrl-single,pins = <
  1112. DRA7XX_CORE_IOPAD(0x35C8, PIN_INPUT | MUX_MODE14) >; }; /* vout1_clk.gpio4_19 */
  1113.  
  1114. /* P8_28b (ball C9) gpio8_20 */
  1115. P8_28_pruout_pin: pinmux_P8_28_pruout_pin { pinctrl-single,pins = <
  1116. DRA7XX_CORE_IOPAD(0x362C, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE13) >; }; /* vout1_d20.pr2_pru0_gpo17 */
  1117. P8_28_pruin_pin: pinmux_P8_28_pruin_pin { pinctrl-single,pins = <
  1118. DRA7XX_CORE_IOPAD(0x362C, PIN_INPUT | MUX_MODE12) >; }; /* vout1_d20.pr2_pru0_gpi17 */
  1119.  
  1120. /* P8_29a (ball C11) gpio4_22 */
  1121. P8_29_default_pin: pinmux_P8_29_default_pin { pinctrl-single,pins = <
  1122. DRA7XX_CORE_IOPAD(0x35D4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_hsync.gpio4_22 */
  1123. P8_29_gpio_pin: pinmux_P8_29_gpio_pin { pinctrl-single,pins = <
  1124. DRA7XX_CORE_IOPAD(0x35D4, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vout1_hsync.gpio4_22 */
  1125. P8_29_gpio_pu_pin: pinmux_P8_29_gpio_pu_pin { pinctrl-single,pins = <
  1126. DRA7XX_CORE_IOPAD(0x35D4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vout1_hsync.gpio4_22 */
  1127. P8_29_gpio_pd_pin: pinmux_P8_29_gpio_pd_pin { pinctrl-single,pins = <
  1128. DRA7XX_CORE_IOPAD(0x35D4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_hsync.gpio4_22 */
  1129. P8_29_gpio_input_pin: pinmux_P8_29_gpio_input_pin { pinctrl-single,pins = <
  1130. DRA7XX_CORE_IOPAD(0x35D4, PIN_INPUT | MUX_MODE14) >; }; /* vout1_hsync.gpio4_22 */
  1131.  
  1132. /* P8_29b (ball A9) gpio8_21 */
  1133. P8_29_pruout_pin: pinmux_P8_29_pruout_pin { pinctrl-single,pins = <
  1134. DRA7XX_CORE_IOPAD(0x3630, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE13) >; }; /* vout1_d21.pr2_pru0_gpo18 */
  1135. P8_29_pruin_pin: pinmux_P8_29_pruin_pin { pinctrl-single,pins = <
  1136. DRA7XX_CORE_IOPAD(0x3630, PIN_INPUT | MUX_MODE12) >; }; /* vout1_d21.pr2_pru0_gpi18 */
  1137.  
  1138. /* P8_30a (ball B10) gpio4_20 */
  1139. P8_30_default_pin: pinmux_P8_30_default_pin { pinctrl-single,pins = <
  1140. DRA7XX_CORE_IOPAD(0x35CC, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_de.gpio4_20 */
  1141. P8_30_gpio_pin: pinmux_P8_30_gpio_pin { pinctrl-single,pins = <
  1142. DRA7XX_CORE_IOPAD(0x35CC, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vout1_de.gpio4_20 */
  1143. P8_30_gpio_pu_pin: pinmux_P8_30_gpio_pu_pin { pinctrl-single,pins = <
  1144. DRA7XX_CORE_IOPAD(0x35CC, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vout1_de.gpio4_20 */
  1145. P8_30_gpio_pd_pin: pinmux_P8_30_gpio_pd_pin { pinctrl-single,pins = <
  1146. DRA7XX_CORE_IOPAD(0x35CC, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_de.gpio4_20 */
  1147. P8_30_gpio_input_pin: pinmux_P8_30_gpio_input_pin { pinctrl-single,pins = <
  1148. DRA7XX_CORE_IOPAD(0x35CC, PIN_INPUT | MUX_MODE14) >; }; /* vout1_de.gpio4_20 */
  1149.  
  1150. /* P8_30b (ball B9) gpio8_22 */
  1151. P8_30_pruout_pin: pinmux_P8_30_pruout_pin { pinctrl-single,pins = <
  1152. DRA7XX_CORE_IOPAD(0x3634, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE13) >; }; /* vout1_d22.pr2_pru0_gpo19 */
  1153. P8_30_pruin_pin: pinmux_P8_30_pruin_pin { pinctrl-single,pins = <
  1154. DRA7XX_CORE_IOPAD(0x3634, PIN_INPUT | MUX_MODE12) >; }; /* vout1_d22.pr2_pru0_gpi19 */
  1155.  
  1156.  
  1157. /* P8_31a (ball C8) gpio8_14 */
  1158. P8_31_default_pin: pinmux_P8_31_default_pin { pinctrl-single,pins = <
  1159. DRA7XX_CORE_IOPAD(0x3614, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_d14.gpio8_14 */
  1160. P8_31_gpio_pin: pinmux_P8_31_gpio_pin { pinctrl-single,pins = <
  1161. DRA7XX_CORE_IOPAD(0x3614, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vout1_d14.gpio8_14 */
  1162. P8_31_gpio_pu_pin: pinmux_P8_31_gpio_pu_pin { pinctrl-single,pins = <
  1163. DRA7XX_CORE_IOPAD(0x3614, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vout1_d14.gpio8_14 */
  1164. P8_31_gpio_pd_pin: pinmux_P8_31_gpio_pd_pin { pinctrl-single,pins = <
  1165. DRA7XX_CORE_IOPAD(0x3614, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_d14.gpio8_14 */
  1166. P8_31_gpio_input_pin: pinmux_P8_31_gpio_input_pin { pinctrl-single,pins = <
  1167. DRA7XX_CORE_IOPAD(0x3614, PIN_INPUT | MUX_MODE14) >; }; /* vout1_d14.gpio8_14 */
  1168.  
  1169. /* P8_31b (ball G16) */
  1170. P8_31_uart_pin: pinmux_P8_31_uart_pin { pinctrl-single,pins = <
  1171. DRA7XX_CORE_IOPAD(0x373C, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; }; /* mcasp4_axr0.uart4_rxd */
  1172.  
  1173. /* P8_32a (ball C7) gpio8_15 */
  1174. P8_32_default_pin: pinmux_P8_32_default_pin { pinctrl-single,pins = <
  1175. DRA7XX_CORE_IOPAD(0x3618, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_d15.gpio8_15 */
  1176. P8_32_gpio_pin: pinmux_P8_32_gpio_pin { pinctrl-single,pins = <
  1177. DRA7XX_CORE_IOPAD(0x3618, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vout1_d15.gpio8_15 */
  1178. P8_32_gpio_pu_pin: pinmux_P8_32_gpio_pu_pin { pinctrl-single,pins = <
  1179. DRA7XX_CORE_IOPAD(0x3618, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vout1_d15.gpio8_15 */
  1180. P8_32_gpio_pd_pin: pinmux_P8_32_gpio_pd_pin { pinctrl-single,pins = <
  1181. DRA7XX_CORE_IOPAD(0x3618, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_d15.gpio8_15 */
  1182. P8_32_gpio_input_pin: pinmux_P8_32_gpio_input_pin { pinctrl-single,pins = <
  1183. DRA7XX_CORE_IOPAD(0x3618, PIN_INPUT | MUX_MODE14) >; }; /* vout1_d15.gpio8_15 */
  1184.  
  1185. /* P8_32b (ball D17) */
  1186. P8_32_uart_pin: pinmux_P8_32_uart_pin { pinctrl-single,pins = <
  1187. DRA7XX_CORE_IOPAD(0x3740, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; }; /* mcasp4_axr1.uart4_txd */
  1188.  
  1189. /* P8_33a (ball C6) gpio8_13 */
  1190. P8_33_default_pin: pinmux_P8_33_default_pin { pinctrl-single,pins = <
  1191. DRA7XX_CORE_IOPAD(0x3610, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_d13.gpio8_13 */
  1192. P8_33_gpio_pin: pinmux_P8_33_gpio_pin { pinctrl-single,pins = <
  1193. DRA7XX_CORE_IOPAD(0x3610, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vout1_d13.gpio8_13 */
  1194. P8_33_gpio_pu_pin: pinmux_P8_33_gpio_pu_pin { pinctrl-single,pins = <
  1195. DRA7XX_CORE_IOPAD(0x3610, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vout1_d13.gpio8_13 */
  1196. P8_33_gpio_pd_pin: pinmux_P8_33_gpio_pd_pin { pinctrl-single,pins = <
  1197. DRA7XX_CORE_IOPAD(0x3610, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_d13.gpio8_13 */
  1198. P8_33_gpio_input_pin: pinmux_P8_33_gpio_input_pin { pinctrl-single,pins = <
  1199. DRA7XX_CORE_IOPAD(0x3610, PIN_INPUT | MUX_MODE14) >; }; /* vout1_d13.gpio8_13 */
  1200.  
  1201. /* P8_33b (ball AF9) gpio3_1 */
  1202. P8_33_qep_pin: pinmux_P8_33_qep_pin { pinctrl-single,pins = <
  1203. DRA7XX_CORE_IOPAD(0x34E8, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE10) >; }; /* vin1a_fld0.eQEP1B_in */
  1204.  
  1205.  
  1206. /* P8_34a (ball D8) gpio8_11 */
  1207. P8_34_default_pin: pinmux_P8_34_default_pin { pinctrl-single,pins = <
  1208. DRA7XX_CORE_IOPAD(0x3608, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_d11.gpio8_11 */
  1209. P8_34_gpio_pin: pinmux_P8_34_gpio_pin { pinctrl-single,pins = <
  1210. DRA7XX_CORE_IOPAD(0x3608, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vout1_d11.gpio8_11 */
  1211. P8_34_gpio_pu_pin: pinmux_P8_34_gpio_pu_pin { pinctrl-single,pins = <
  1212. DRA7XX_CORE_IOPAD(0x3608, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vout1_d11.gpio8_11 */
  1213. P8_34_gpio_pd_pin: pinmux_P8_34_gpio_pd_pin { pinctrl-single,pins = <
  1214. DRA7XX_CORE_IOPAD(0x3608, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_d11.gpio8_11 */
  1215. P8_34_gpio_input_pin: pinmux_P8_34_gpio_input_pin { pinctrl-single,pins = <
  1216. DRA7XX_CORE_IOPAD(0x3608, PIN_INPUT | MUX_MODE14) >; }; /* vout1_d11.gpio8_11 */
  1217.  
  1218. /* P8_34b (ball G6) gpio4_0 */
  1219. P8_34_pwm_pin: pinmux_P8_34_pwm_pin { pinctrl-single,pins = <
  1220. DRA7XX_CORE_IOPAD(0x3564, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE10) >; }; /* vin2a_vsync0.ehrpwm1A */
  1221.  
  1222. /* P8_35a (ball A5) gpio8_12 */
  1223. P8_35_default_pin: pinmux_P8_35_default_pin { pinctrl-single,pins = <
  1224. DRA7XX_CORE_IOPAD(0x360C, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_d12.gpio8_12 */
  1225. P8_35_gpio_pin: pinmux_P8_35_gpio_pin { pinctrl-single,pins = <
  1226. DRA7XX_CORE_IOPAD(0x360C, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vout1_d12.gpio8_12 */
  1227. P8_35_gpio_pu_pin: pinmux_P8_35_gpio_pu_pin { pinctrl-single,pins = <
  1228. DRA7XX_CORE_IOPAD(0x360C, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vout1_d12.gpio8_12 */
  1229. P8_35_gpio_pd_pin: pinmux_P8_35_gpio_pd_pin { pinctrl-single,pins = <
  1230. DRA7XX_CORE_IOPAD(0x360C, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_d12.gpio8_12 */
  1231. P8_35_gpio_input_pin: pinmux_P8_35_gpio_input_pin { pinctrl-single,pins = <
  1232. DRA7XX_CORE_IOPAD(0x360C, PIN_INPUT | MUX_MODE14) >; }; /* vout1_d12.gpio8_12 */
  1233.  
  1234. /* P8_35b (ball AD9) gpio3_0 */
  1235. P8_35_qep_pin: pinmux_P8_35_qep_pin { pinctrl-single,pins = <
  1236. DRA7XX_CORE_IOPAD(0x34E4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE10) >; }; /* vin1a_de0.eQEP1A_in */
  1237.  
  1238. /* P8_36a (ball D7) gpio8_10 */
  1239. P8_36_default_pin: pinmux_P8_36_default_pin { pinctrl-single,pins = <
  1240. DRA7XX_CORE_IOPAD(0x3604, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_d10.gpio8_10 */
  1241. P8_36_gpio_pin: pinmux_P8_36_gpio_pin { pinctrl-single,pins = <
  1242. DRA7XX_CORE_IOPAD(0x3604, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vout1_d10.gpio8_10 */
  1243. P8_36_gpio_pu_pin: pinmux_P8_36_gpio_pu_pin { pinctrl-single,pins = <
  1244. DRA7XX_CORE_IOPAD(0x3604, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vout1_d10.gpio8_10 */
  1245. P8_36_gpio_pd_pin: pinmux_P8_36_gpio_pd_pin { pinctrl-single,pins = <
  1246. DRA7XX_CORE_IOPAD(0x3604, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_d10.gpio8_10 */
  1247. P8_36_gpio_input_pin: pinmux_P8_36_gpio_input_pin { pinctrl-single,pins = <
  1248. DRA7XX_CORE_IOPAD(0x3604, PIN_INPUT | MUX_MODE14) >; }; /* vout1_d10.gpio8_10 */
  1249.  
  1250. /* P8_36b (ball F2) gpio4_1 */
  1251. P8_36_pwm_pin: pinmux_P8_36_pwm_pin { pinctrl-single,pins = <
  1252. DRA7XX_CORE_IOPAD(0x3568, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE10) >; }; /* vin2a_d0.ehrpwm1B */
  1253.  
  1254. /* P8_37a (ball E8) gpio8_8 */
  1255. P8_37_default_pin: pinmux_P8_37_default_pin { pinctrl-single,pins = <
  1256. DRA7XX_CORE_IOPAD(0x35FC, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_d8.gpio8_8 */
  1257. P8_37_gpio_pin: pinmux_P8_37_gpio_pin { pinctrl-single,pins = <
  1258. DRA7XX_CORE_IOPAD(0x35FC, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vout1_d8.gpio8_8 */
  1259. P8_37_gpio_pu_pin: pinmux_P8_37_gpio_pu_pin { pinctrl-single,pins = <
  1260. DRA7XX_CORE_IOPAD(0x35FC, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vout1_d8.gpio8_8 */
  1261. P8_37_gpio_pd_pin: pinmux_P8_37_gpio_pd_pin { pinctrl-single,pins = <
  1262. DRA7XX_CORE_IOPAD(0x35FC, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_d8.gpio8_8 */
  1263. P8_37_gpio_input_pin: pinmux_P8_37_gpio_input_pin { pinctrl-single,pins = <
  1264. DRA7XX_CORE_IOPAD(0x35FC, PIN_INPUT | MUX_MODE14) >; }; /* vout1_d8.gpio8_8 */
  1265.  
  1266. /* P8_37b (ball A21) */
  1267. P8_37_uart_pin: pinmux_P8_37_uart_pin { pinctrl-single,pins = <
  1268. DRA7XX_CORE_IOPAD(0x3738, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; }; /* mcasp4_fsx.uart8_txd */
  1269.  
  1270. /* P8_38a (ball D9) gpio8_9 */
  1271. P8_38_default_pin: pinmux_P8_38_default_pin { pinctrl-single,pins = <
  1272. DRA7XX_CORE_IOPAD(0x3600, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_d9.gpio8_9 */
  1273. P8_38_gpio_pin: pinmux_P8_38_gpio_pin { pinctrl-single,pins = <
  1274. DRA7XX_CORE_IOPAD(0x3600, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vout1_d9.gpio8_9 */
  1275. P8_38_gpio_pu_pin: pinmux_P8_38_gpio_pu_pin { pinctrl-single,pins = <
  1276. DRA7XX_CORE_IOPAD(0x3600, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vout1_d9.gpio8_9 */
  1277. P8_38_gpio_pd_pin: pinmux_P8_38_gpio_pd_pin { pinctrl-single,pins = <
  1278. DRA7XX_CORE_IOPAD(0x3600, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_d9.gpio8_9 */
  1279. P8_38_gpio_input_pin: pinmux_P8_38_gpio_input_pin { pinctrl-single,pins = <
  1280. DRA7XX_CORE_IOPAD(0x3600, PIN_INPUT | MUX_MODE14) >; }; /* vout1_d9.gpio8_9 */
  1281.  
  1282. /* P8_38b (ball C18) */
  1283. P8_38_uart_pin: pinmux_P8_38_uart_pin { pinctrl-single,pins = <
  1284. DRA7XX_CORE_IOPAD(0x3734, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; }; /* mcasp4_aclkx.uart8_rxd */
  1285.  
  1286. /* P8_39 (ball F8) gpio8_6 */
  1287. P8_39_default_pin: pinmux_P8_39_default_pin { pinctrl-single,pins = <
  1288. DRA7XX_CORE_IOPAD(0x35F4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_d6.gpio8_6 */
  1289. P8_39_gpio_pin: pinmux_P8_39_gpio_pin { pinctrl-single,pins = <
  1290. DRA7XX_CORE_IOPAD(0x35F4, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vout1_d6.gpio8_6 */
  1291. P8_39_gpio_pu_pin: pinmux_P8_39_gpio_pu_pin { pinctrl-single,pins = <
  1292. DRA7XX_CORE_IOPAD(0x35F4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vout1_d6.gpio8_6 */
  1293. P8_39_gpio_pd_pin: pinmux_P8_39_gpio_pd_pin { pinctrl-single,pins = <
  1294. DRA7XX_CORE_IOPAD(0x35F4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_d6.gpio8_6 */
  1295. P8_39_gpio_input_pin: pinmux_P8_39_gpio_input_pin { pinctrl-single,pins = <
  1296. DRA7XX_CORE_IOPAD(0x35F4, PIN_INPUT | MUX_MODE14) >; }; /* vout1_d6.gpio8_6 */
  1297. P8_39_pruout_pin: pinmux_P8_39_pruout_pin { pinctrl-single,pins = <
  1298. DRA7XX_CORE_IOPAD(0x35F4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE13) >; }; /* vout1_d6.pr2_pru0_gpo3 */
  1299. P8_39_pruin_pin: pinmux_P8_39_pruin_pin { pinctrl-single,pins = <
  1300. DRA7XX_CORE_IOPAD(0x35F4, PIN_INPUT | MUX_MODE12) >; }; /* vout1_d6.pr2_pru0_gpi3 */
  1301.  
  1302. /* P8_40 (ball E7) gpio8_7 */
  1303. P8_40_default_pin: pinmux_P8_40_default_pin { pinctrl-single,pins = <
  1304. DRA7XX_CORE_IOPAD(0x35F8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_d7.gpio8_7 */
  1305. P8_40_gpio_pin: pinmux_P8_40_gpio_pin { pinctrl-single,pins = <
  1306. DRA7XX_CORE_IOPAD(0x35F8, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vout1_d7.gpio8_7 */
  1307. P8_40_gpio_pu_pin: pinmux_P8_40_gpio_pu_pin { pinctrl-single,pins = <
  1308. DRA7XX_CORE_IOPAD(0x35F8, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vout1_d7.gpio8_7 */
  1309. P8_40_gpio_pd_pin: pinmux_P8_40_gpio_pd_pin { pinctrl-single,pins = <
  1310. DRA7XX_CORE_IOPAD(0x35F8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_d7.gpio8_7 */
  1311. P8_40_gpio_input_pin: pinmux_P8_40_gpio_input_pin { pinctrl-single,pins = <
  1312. DRA7XX_CORE_IOPAD(0x35F8, PIN_INPUT | MUX_MODE14) >; }; /* vout1_d7.gpio8_7 */
  1313. P8_40_pruout_pin: pinmux_P8_40_pruout_pin { pinctrl-single,pins = <
  1314. DRA7XX_CORE_IOPAD(0x35F8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE13) >; }; /* vout1_d7.pr2_pru0_gpo4 */
  1315. P8_40_pruin_pin: pinmux_P8_40_pruin_pin { pinctrl-single,pins = <
  1316. DRA7XX_CORE_IOPAD(0x35F8, PIN_INPUT | MUX_MODE12) >; }; /* vout1_d7.pr2_pru0_gpi4 */
  1317.  
  1318. /* P8_41 (ball E9) gpio8_4 */
  1319. P8_41_default_pin: pinmux_P8_41_default_pin { pinctrl-single,pins = <
  1320. DRA7XX_CORE_IOPAD(0x35EC, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_d4.gpio8_4 */
  1321. P8_41_gpio_pin: pinmux_P8_41_gpio_pin { pinctrl-single,pins = <
  1322. DRA7XX_CORE_IOPAD(0x35EC, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vout1_d4.gpio8_4 */
  1323. P8_41_gpio_pu_pin: pinmux_P8_41_gpio_pu_pin { pinctrl-single,pins = <
  1324. DRA7XX_CORE_IOPAD(0x35EC, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vout1_d4.gpio8_4 */
  1325. P8_41_gpio_pd_pin: pinmux_P8_41_gpio_pd_pin { pinctrl-single,pins = <
  1326. DRA7XX_CORE_IOPAD(0x35EC, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_d4.gpio8_4 */
  1327. P8_41_gpio_input_pin: pinmux_P8_41_gpio_input_pin { pinctrl-single,pins = <
  1328. DRA7XX_CORE_IOPAD(0x35EC, PIN_INPUT | MUX_MODE14) >; }; /* vout1_d4.gpio8_4 */
  1329. P8_41_pruout_pin: pinmux_P8_41_pruout_pin { pinctrl-single,pins = <
  1330. DRA7XX_CORE_IOPAD(0x35EC, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE13) >; }; /* vout1_d4.pr2_pru0_gpo1 */
  1331. P8_41_pruin_pin: pinmux_P8_41_pruin_pin { pinctrl-single,pins = <
  1332. DRA7XX_CORE_IOPAD(0x35EC, PIN_INPUT | MUX_MODE12) >; }; /* vout1_d4.pr2_pru0_gpi1 */
  1333.  
  1334. /* P8_42 (ball F9) gpio8_5 */
  1335. P8_42_default_pin: pinmux_P8_42_default_pin { pinctrl-single,pins = <
  1336. DRA7XX_CORE_IOPAD(0x35F0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_d5.gpio8_5 */
  1337. P8_42_gpio_pin: pinmux_P8_42_gpio_pin { pinctrl-single,pins = <
  1338. DRA7XX_CORE_IOPAD(0x35F0, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vout1_d5.gpio8_5 */
  1339. P8_42_gpio_pu_pin: pinmux_P8_42_gpio_pu_pin { pinctrl-single,pins = <
  1340. DRA7XX_CORE_IOPAD(0x35F0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vout1_d5.gpio8_5 */
  1341. P8_42_gpio_pd_pin: pinmux_P8_42_gpio_pd_pin { pinctrl-single,pins = <
  1342. DRA7XX_CORE_IOPAD(0x35F0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_d5.gpio8_5 */
  1343. P8_42_gpio_input_pin: pinmux_P8_42_gpio_input_pin { pinctrl-single,pins = <
  1344. DRA7XX_CORE_IOPAD(0x35F0, PIN_INPUT | MUX_MODE14) >; }; /* vout1_d5.gpio8_5 */
  1345. P8_42_pruout_pin: pinmux_P8_42_pruout_pin { pinctrl-single,pins = <
  1346. DRA7XX_CORE_IOPAD(0x35F0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE13) >; }; /* vout1_d5.pr2_pru0_gpo2 */
  1347. P8_42_pruin_pin: pinmux_P8_42_pruin_pin { pinctrl-single,pins = <
  1348. DRA7XX_CORE_IOPAD(0x35F0, PIN_INPUT | MUX_MODE12) >; }; /* vout1_d5.pr2_pru0_gpi2 */
  1349.  
  1350. /* P8_43 (ball F10) gpio8_2 */
  1351. P8_43_default_pin: pinmux_P8_43_default_pin { pinctrl-single,pins = <
  1352. DRA7XX_CORE_IOPAD(0x35E4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_d2.gpio8_2 */
  1353. P8_43_gpio_pin: pinmux_P8_43_gpio_pin { pinctrl-single,pins = <
  1354. DRA7XX_CORE_IOPAD(0x35E4, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vout1_d2.gpio8_2 */
  1355. P8_43_gpio_pu_pin: pinmux_P8_43_gpio_pu_pin { pinctrl-single,pins = <
  1356. DRA7XX_CORE_IOPAD(0x35E4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vout1_d2.gpio8_2 */
  1357. P8_43_gpio_pd_pin: pinmux_P8_43_gpio_pd_pin { pinctrl-single,pins = <
  1358. DRA7XX_CORE_IOPAD(0x35E4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_d2.gpio8_2 */
  1359. P8_43_gpio_input_pin: pinmux_P8_43_gpio_input_pin { pinctrl-single,pins = <
  1360. DRA7XX_CORE_IOPAD(0x35E4, PIN_INPUT | MUX_MODE14) >; }; /* vout1_d2.gpio8_2 */
  1361. P8_43_pruout_pin: pinmux_P8_43_pruout_pin { pinctrl-single,pins = <
  1362. DRA7XX_CORE_IOPAD(0x35E4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE13) >; }; /* vout1_d2.pr2_pru1_gpo20 */
  1363. P8_43_pruin_pin: pinmux_P8_43_pruin_pin { pinctrl-single,pins = <
  1364. DRA7XX_CORE_IOPAD(0x35E4, PIN_INPUT | MUX_MODE12) >; }; /* vout1_d2.pr2_pru1_gpi20 */
  1365.  
  1366. /* P8_44 (ball G11) gpio8_3 */
  1367. P8_44_default_pin: pinmux_P8_44_default_pin { pinctrl-single,pins = <
  1368. DRA7XX_CORE_IOPAD(0x35E8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_d3.gpio8_3 */
  1369. P8_44_gpio_pin: pinmux_P8_44_gpio_pin { pinctrl-single,pins = <
  1370. DRA7XX_CORE_IOPAD(0x35E8, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vout1_d3.gpio8_3 */
  1371. P8_44_gpio_pu_pin: pinmux_P8_44_gpio_pu_pin { pinctrl-single,pins = <
  1372. DRA7XX_CORE_IOPAD(0x35E8, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vout1_d3.gpio8_3 */
  1373. P8_44_gpio_pd_pin: pinmux_P8_44_gpio_pd_pin { pinctrl-single,pins = <
  1374. DRA7XX_CORE_IOPAD(0x35E8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_d3.gpio8_3 */
  1375. P8_44_gpio_input_pin: pinmux_P8_44_gpio_input_pin { pinctrl-single,pins = <
  1376. DRA7XX_CORE_IOPAD(0x35E8, PIN_INPUT | MUX_MODE14) >; }; /* vout1_d3.gpio8_3 */
  1377. P8_44_pruout_pin: pinmux_P8_44_pruout_pin { pinctrl-single,pins = <
  1378. DRA7XX_CORE_IOPAD(0x35E8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE13) >; }; /* vout1_d3.pr2_pru0_gpo0 */
  1379. P8_44_pruin_pin: pinmux_P8_44_pruin_pin { pinctrl-single,pins = <
  1380. DRA7XX_CORE_IOPAD(0x35E8, PIN_INPUT | MUX_MODE12) >; }; /* vout1_d3.pr2_pru0_gpi0 */
  1381.  
  1382. /* P8_45a (ball F11) gpio8_0 */
  1383. P8_45_default_pin: pinmux_P8_45_default_pin { pinctrl-single,pins = <
  1384. DRA7XX_CORE_IOPAD(0x35DC, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_d0.gpio8_0 */
  1385. P8_45_gpio_pin: pinmux_P8_45_gpio_pin { pinctrl-single,pins = <
  1386. DRA7XX_CORE_IOPAD(0x35DC, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vout1_d0.gpio8_0 */
  1387. P8_45_gpio_pu_pin: pinmux_P8_45_gpio_pu_pin { pinctrl-single,pins = <
  1388. DRA7XX_CORE_IOPAD(0x35DC, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vout1_d0.gpio8_0 */
  1389. P8_45_gpio_pd_pin: pinmux_P8_45_gpio_pd_pin { pinctrl-single,pins = <
  1390. DRA7XX_CORE_IOPAD(0x35DC, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_d0.gpio8_0 */
  1391. P8_45_gpio_input_pin: pinmux_P8_45_gpio_input_pin { pinctrl-single,pins = <
  1392. DRA7XX_CORE_IOPAD(0x35DC, PIN_INPUT | MUX_MODE14) >; }; /* vout1_d0.gpio8_0 */
  1393.  
  1394. /* P8_45b (ball B7) gpio8_16 */
  1395. P8_45_pruout_pin: pinmux_P8_45_pruout_pin { pinctrl-single,pins = <
  1396. DRA7XX_CORE_IOPAD(0x361C, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE13) >; }; /* vout1_d16.pr2_pru0_gpo13 */
  1397. P8_45_pruin_pin: pinmux_P8_45_pruin_pin { pinctrl-single,pins = <
  1398. DRA7XX_CORE_IOPAD(0x361C, PIN_INPUT | MUX_MODE12) >; }; /* vout1_d16.pr2_pru0_gpi13 */
  1399.  
  1400. /* P8_46a (ball G10) gpio8_1 */
  1401. P8_46_default_pin: pinmux_P8_46_default_pin { pinctrl-single,pins = <
  1402. DRA7XX_CORE_IOPAD(0x35E0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_d1.gpio8_1 */
  1403. P8_46_gpio_pin: pinmux_P8_46_gpio_pin { pinctrl-single,pins = <
  1404. DRA7XX_CORE_IOPAD(0x35E0, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vout1_d1.gpio8_1 */
  1405. P8_46_gpio_pu_pin: pinmux_P8_46_gpio_pu_pin { pinctrl-single,pins = <
  1406. DRA7XX_CORE_IOPAD(0x35E0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vout1_d1.gpio8_1 */
  1407. P8_46_gpio_pd_pin: pinmux_P8_46_gpio_pd_pin { pinctrl-single,pins = <
  1408. DRA7XX_CORE_IOPAD(0x35E0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_d1.gpio8_1 */
  1409. P8_46_gpio_input_pin: pinmux_P8_46_gpio_input_pin { pinctrl-single,pins = <
  1410. DRA7XX_CORE_IOPAD(0x35E0, PIN_INPUT | MUX_MODE14) >; }; /* vout1_d1.gpio8_1 */
  1411.  
  1412. /* P8_46b (ball A10) gpio8_23 */
  1413. P8_46_pruout_pin: pinmux_P8_46_pruout_pin { pinctrl-single,pins = <
  1414. DRA7XX_CORE_IOPAD(0x3638, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE13) >; }; /* vout1_d23.pr2_pru0_gpo20 */
  1415. P8_46_pruin_pin: pinmux_P8_46_pruin_pin { pinctrl-single,pins = <
  1416. DRA7XX_CORE_IOPAD(0x3638, PIN_INPUT | MUX_MODE12) >; }; /* vout1_d23.pr2_pru0_gpi20 */
  1417.  
  1418. /************************/
  1419. /* P9 Header */
  1420. /************************/
  1421.  
  1422. /* P9_01 GND */
  1423.  
  1424. /* P9_02 GND */
  1425.  
  1426. /* P9_03 3V3 */
  1427.  
  1428. /* P9_04 3V3 */
  1429.  
  1430. /* P9_05 VDD_5V */
  1431.  
  1432. /* P9_06 VDD_5V */
  1433.  
  1434. /* P9_07 SYS_5V */
  1435.  
  1436. /* P9_08 SYS_5V */
  1437.  
  1438. /* P9_09 PWR_BUT */
  1439.  
  1440. /* P9_10 RSTn */
  1441.  
  1442. /* P9_11a (ball B19) */
  1443. P9_11_uart_pin: pinmux_P9_11_uart_pin { pinctrl-single,pins = <
  1444. DRA7XX_CORE_IOPAD(0x372C, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; }; /* mcasp3_axr0.uart5_rxd */
  1445.  
  1446. /* P9_11b (ball B8) gpio8_17 */
  1447. P9_11_default_pin: pinmux_P9_11_default_pin { pinctrl-single,pins = <
  1448. DRA7XX_CORE_IOPAD(0x3620, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vout1_d17.gpio8_17 */
  1449. P9_11_gpio_pin: pinmux_P9_11_gpio_pin { pinctrl-single,pins = <
  1450. DRA7XX_CORE_IOPAD(0x3620, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vout1_d17.gpio8_17 */
  1451. P9_11_gpio_pu_pin: pinmux_P9_11_gpio_pu_pin { pinctrl-single,pins = <
  1452. DRA7XX_CORE_IOPAD(0x3620, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vout1_d17.gpio8_17 */
  1453. P9_11_gpio_pd_pin: pinmux_P9_11_gpio_pd_pin { pinctrl-single,pins = <
  1454. DRA7XX_CORE_IOPAD(0x3620, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vout1_d17.gpio8_17 */
  1455. P9_11_gpio_input_pin: pinmux_P9_11_gpio_input_pin { pinctrl-single,pins = <
  1456. DRA7XX_CORE_IOPAD(0x3620, PIN_INPUT | MUX_MODE14) >; }; /* vout1_d17.gpio8_17 */
  1457.  
  1458. /* P9_12 (ball B14) gpio5_0 */
  1459. P9_12_default_pin: pinmux_P9_12_default_pin { pinctrl-single,pins = <
  1460. DRA7XX_CORE_IOPAD(0x36AC, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_aclkr.gpio5_0 */
  1461. P9_12_gpio_pin: pinmux_P9_12_gpio_pin { pinctrl-single,pins = <
  1462. DRA7XX_CORE_IOPAD(0x36AC, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_aclkr.gpio5_0 */
  1463. P9_12_gpio_pu_pin: pinmux_P9_12_gpio_pu_pin { pinctrl-single,pins = <
  1464. DRA7XX_CORE_IOPAD(0x36AC, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_aclkr.gpio5_0 */
  1465. P9_12_gpio_pd_pin: pinmux_P9_12_gpio_pd_pin { pinctrl-single,pins = <
  1466. DRA7XX_CORE_IOPAD(0x36AC, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_aclkr.gpio5_0 */
  1467. P9_12_gpio_input_pin: pinmux_P9_12_gpio_input_pin { pinctrl-single,pins = <
  1468. DRA7XX_CORE_IOPAD(0x36AC, PIN_INPUT | MUX_MODE14) >; }; /* mcasp1_aclkr.gpio5_0 */
  1469.  
  1470. /* P9_13a (ball C17) */
  1471. P9_13_uart_pin: pinmux_P9_13_uart_pin { pinctrl-single,pins = <
  1472. DRA7XX_CORE_IOPAD(0x3730, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; }; /* mcasp3_axr1.uart5_txd */
  1473.  
  1474. /* P9_13b (ball AB10) gpio6_12 */
  1475. P9_13_default_pin: pinmux_P9_13_default_pin { pinctrl-single,pins = <
  1476. DRA7XX_CORE_IOPAD(0x3680, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* usb1_drvvbus.gpio6_12 */
  1477. P9_13_gpio_pin: pinmux_P9_13_gpio_pin { pinctrl-single,pins = <
  1478. DRA7XX_CORE_IOPAD(0x3680, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* usb1_drvvbus.gpio6_12 */
  1479. P9_13_gpio_pu_pin: pinmux_P9_13_gpio_pu_pin { pinctrl-single,pins = <
  1480. DRA7XX_CORE_IOPAD(0x3680, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* usb1_drvvbus.gpio6_12 */
  1481. P9_13_gpio_pd_pin: pinmux_P9_13_gpio_pd_pin { pinctrl-single,pins = <
  1482. DRA7XX_CORE_IOPAD(0x3680, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* usb1_drvvbus.gpio6_12 */
  1483. P9_13_gpio_input_pin: pinmux_P9_13_gpio_input_pin { pinctrl-single,pins = <
  1484. DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT | MUX_MODE14) >; }; /* usb1_drvvbus.gpio6_12 */
  1485.  
  1486.  
  1487. /* P9_14 (ball D6) gpio4_25 */
  1488. P9_14_default_pin: pinmux_P9_14_default_pin { pinctrl-single,pins = <
  1489. DRA7XX_CORE_IOPAD(0x35AC, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d17.gpio4_25 */
  1490. P9_14_gpio_pin: pinmux_P9_14_gpio_pin { pinctrl-single,pins = <
  1491. DRA7XX_CORE_IOPAD(0x35AC, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d17.gpio4_25 */
  1492. P9_14_gpio_pu_pin: pinmux_P9_14_gpio_pu_pin { pinctrl-single,pins = <
  1493. DRA7XX_CORE_IOPAD(0x35AC, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d17.gpio4_25 */
  1494. P9_14_gpio_pd_pin: pinmux_P9_14_gpio_pd_pin { pinctrl-single,pins = <
  1495. DRA7XX_CORE_IOPAD(0x35AC, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d17.gpio4_25 */
  1496. P9_14_gpio_input_pin: pinmux_P9_14_gpio_input_pin { pinctrl-single,pins = <
  1497. DRA7XX_CORE_IOPAD(0x35AC, PIN_INPUT | MUX_MODE14) >; }; /* vin2a_d17.gpio4_25 */
  1498. P9_14_pwm_pin: pinmux_P9_14_pwm_pin { pinctrl-single,pins = <
  1499. DRA7XX_CORE_IOPAD(0x35AC, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE10) >; }; /* vin2a_d17.ehrpwm3A */
  1500.  
  1501. /* P9_15 (ball AG4) gpio3_12 */
  1502. P9_15_default_pin: pinmux_P9_15_default_pin { pinctrl-single,pins = <
  1503. DRA7XX_CORE_IOPAD(0x3514, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vin1a_d8.gpio3_12 */
  1504. P9_15_gpio_pin: pinmux_P9_15_gpio_pin { pinctrl-single,pins = <
  1505. DRA7XX_CORE_IOPAD(0x3514, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vin1a_d8.gpio3_12 */
  1506. P9_15_gpio_pu_pin: pinmux_P9_15_gpio_pu_pin { pinctrl-single,pins = <
  1507. DRA7XX_CORE_IOPAD(0x3514, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vin1a_d8.gpio3_12 */
  1508. P9_15_gpio_pd_pin: pinmux_P9_15_gpio_pd_pin { pinctrl-single,pins = <
  1509. DRA7XX_CORE_IOPAD(0x3514, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vin1a_d8.gpio3_12 */
  1510. P9_15_gpio_input_pin: pinmux_P9_15_gpio_input_pin { pinctrl-single,pins = <
  1511. DRA7XX_CORE_IOPAD(0x3514, PIN_INPUT | MUX_MODE14) >; }; /* vin1a_d8.gpio3_12 */
  1512.  
  1513. /* P9_16 (ball C5) gpio4_26 */
  1514. P9_16_default_pin: pinmux_P9_16_default_pin { pinctrl-single,pins = <
  1515. DRA7XX_CORE_IOPAD(0x35B0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE10) >; }; /* vin2a_d18.gpio4_26 */
  1516. P9_16_gpio_pin: pinmux_P9_16_gpio_pin { pinctrl-single,pins = <
  1517. DRA7XX_CORE_IOPAD(0x35B0, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d18.gpio4_26 */
  1518. P9_16_gpio_pu_pin: pinmux_P9_16_gpio_pu_pin { pinctrl-single,pins = <
  1519. DRA7XX_CORE_IOPAD(0x35B0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d18.gpio4_26 */
  1520. P9_16_gpio_pd_pin: pinmux_P9_16_gpio_pd_pin { pinctrl-single,pins = <
  1521. DRA7XX_CORE_IOPAD(0x35B0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d18.gpio4_26 */
  1522. P9_16_gpio_input_pin: pinmux_P9_16_gpio_input_pin { pinctrl-single,pins = <
  1523. DRA7XX_CORE_IOPAD(0x35B0, PIN_INPUT | MUX_MODE14) >; }; /* vin2a_d18.gpio4_26 */
  1524. P9_16_pwm_pin: pinmux_P9_16_pwm_pin { pinctrl-single,pins = <
  1525. DRA7XX_CORE_IOPAD(0x35B0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE10) >; }; /* vin2a_d18.ehrpwm3B */
  1526.  
  1527. /* P9_17a (ball B24) gpio7_17 */
  1528. P9_17_default_pin: pinmux_P9_17_default_pin { pinctrl-single,pins = <
  1529. DRA7XX_CORE_IOPAD(0x37CC, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* spi2_cs0.gpio7_17 */
  1530. P9_17_gpio_pin: pinmux_P9_17_gpio_pin { pinctrl-single,pins = <
  1531. DRA7XX_CORE_IOPAD(0x37CC, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* spi2_cs0.gpio7_17 */
  1532. P9_17_gpio_pu_pin: pinmux_P9_17_gpio_pu_pin { pinctrl-single,pins = <
  1533. DRA7XX_CORE_IOPAD(0x37CC, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* spi2_cs0.gpio7_17 */
  1534. P9_17_gpio_pd_pin: pinmux_P9_17_gpio_pd_pin { pinctrl-single,pins = <
  1535. DRA7XX_CORE_IOPAD(0x37CC, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* spi2_cs0.gpio7_17 */
  1536. P9_17_gpio_input_pin: pinmux_P9_17_gpio_input_pin { pinctrl-single,pins = <
  1537. DRA7XX_CORE_IOPAD(0x37CC, PIN_INPUT | MUX_MODE14) >; }; /* spi2_cs0.gpio7_17 */
  1538. P9_17_spi_cs_pin: pinmux_P9_17_spi_cs_pin { pinctrl-single,pins = <
  1539. DRA7XX_CORE_IOPAD(0x37CC, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE0) >; }; /* spi2_cs0.spi2_cs0 */
  1540.  
  1541. /* P9_17b (ball F12) gpio5_3 */
  1542. P9_17_i2c_pin: pinmux_P9_17_i2c_pin { pinctrl-single,pins = <
  1543. DRA7XX_CORE_IOPAD(0x36B8, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE10) >; }; /* mcasp1_axr1.i2c5_scl */
  1544. P9_17_uart_pin: pinmux_P9_17_pru_uart_pin { pinctrl-single,pins = <
  1545. DRA7XX_CORE_IOPAD(0x36B8, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; }; /* mcasp1_axr1.uart6_txd */
  1546.  
  1547. /* P9_18a (ball G17) gpio7_16 */
  1548. P9_18_default_pin: pinmux_P9_18_default_pin { pinctrl-single,pins = <
  1549. DRA7XX_CORE_IOPAD(0x37C8, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* spi2_d0.gpio7_16 */
  1550. P9_18_gpio_pin: pinmux_P9_18_gpio_pin { pinctrl-single,pins = <
  1551. DRA7XX_CORE_IOPAD(0x37C8, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* spi2_d0.gpio7_16 */
  1552. P9_18_gpio_pu_pin: pinmux_P9_18_gpio_pu_pin { pinctrl-single,pins = <
  1553. DRA7XX_CORE_IOPAD(0x37C8, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* spi2_d0.gpio7_16 */
  1554. P9_18_gpio_pd_pin: pinmux_P9_18_gpio_pd_pin { pinctrl-single,pins = <
  1555. DRA7XX_CORE_IOPAD(0x37C8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* spi2_d0.gpio7_16 */
  1556. P9_18_gpio_input_pin: pinmux_P9_18_gpio_input_pin { pinctrl-single,pins = <
  1557. DRA7XX_CORE_IOPAD(0x37C8, PIN_INPUT | MUX_MODE14) >; }; /* spi2_d0.gpio7_16 */
  1558. P9_18_spi_pin: pinmux_P9_18_spi_pin { pinctrl-single,pins = <
  1559. DRA7XX_CORE_IOPAD(0x37C8, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE0) >; }; /* spi2_d0.spi2_d0 */
  1560.  
  1561. /* P9_18b (ball G12) gpio5_2 */
  1562. P9_18_i2c_pin: pinmux_P9_18_i2c_pin { pinctrl-single,pins = <
  1563. DRA7XX_CORE_IOPAD(0x36B4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE10) >; }; /* mcasp1_axr0.i2c5_sda */
  1564. P9_18_uart_pin: pinmux_P9_18_pru_uart_pin { pinctrl-single,pins = <
  1565. DRA7XX_CORE_IOPAD(0x36B4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; }; /* mcasp1_axr0.uart6_rxd */
  1566.  
  1567. /* P9_19a (ball R6) gpio7_3 */
  1568. P9_19_default_pin: pinmux_P9_19_default_pin { pinctrl-single,pins = <
  1569. DRA7XX_CORE_IOPAD(0x3440, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; }; /* gpmc_a0.gpio7_3 */
  1570. P9_19_gpio_pin: pinmux_P9_19_gpio_pin { pinctrl-single,pins = <
  1571. DRA7XX_CORE_IOPAD(0x3440, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* gpmc_a0.gpio7_3 */
  1572. P9_19_gpio_pu_pin: pinmux_P9_19_gpio_pu_pin { pinctrl-single,pins = <
  1573. DRA7XX_CORE_IOPAD(0x3440, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* gpmc_a0.gpio7_3 */
  1574. P9_19_gpio_pd_pin: pinmux_P9_19_gpio_pd_pin { pinctrl-single,pins = <
  1575. DRA7XX_CORE_IOPAD(0x3440, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* gpmc_a0.gpio7_3 */
  1576. P9_19_gpio_input_pin: pinmux_P9_19_gpio_input_pin { pinctrl-single,pins = <
  1577. DRA7XX_CORE_IOPAD(0x3440, PIN_INPUT | MUX_MODE14) >; }; /* gpmc_a0.gpio7_3 */
  1578. P9_19_i2c_pin: pinmux_P9_19_i2c_pin { pinctrl-single,pins = <
  1579. DRA7XX_CORE_IOPAD(0x3440, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; }; /* gpmc_a0.i2c4_scl */
  1580.  
  1581. /* P9_19b (ball F4) gpio4_6 */
  1582. P9_19_qep_pin: pinmux_P9_19_qep_pin { pinctrl-single,pins = <
  1583. DRA7XX_CORE_IOPAD(0x357C, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE10) >; }; /* vin2a_d5.eQEP2A_in */
  1584.  
  1585. /* P9_20a (ball T9) gpio7_4 */
  1586. P9_20_default_pin: pinmux_P9_20_default_pin { pinctrl-single,pins = <
  1587. DRA7XX_CORE_IOPAD(0x3444, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; }; /* gpmc_a1.gpio7_4 */
  1588. P9_20_gpio_pin: pinmux_P9_20_gpio_pin { pinctrl-single,pins = <
  1589. DRA7XX_CORE_IOPAD(0x3444, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* gpmc_a1.gpio7_4 */
  1590. P9_20_gpio_pu_pin: pinmux_P9_20_gpio_pu_pin { pinctrl-single,pins = <
  1591. DRA7XX_CORE_IOPAD(0x3444, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* gpmc_a1.gpio7_4 */
  1592. P9_20_gpio_pd_pin: pinmux_P9_20_gpio_pd_pin { pinctrl-single,pins = <
  1593. DRA7XX_CORE_IOPAD(0x3444, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* gpmc_a1.gpio7_4 */
  1594. P9_20_gpio_input_pin: pinmux_P9_20_gpio_input_pin { pinctrl-single,pins = <
  1595. DRA7XX_CORE_IOPAD(0x3444, PIN_INPUT | MUX_MODE14) >; }; /* gpmc_a1.gpio7_4 */
  1596. P9_20_i2c_pin: pinmux_P9_20_i2c_pin { pinctrl-single,pins = <
  1597. DRA7XX_CORE_IOPAD(0x3444, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; }; /* gpmc_a1.i2c4_sda */
  1598.  
  1599. /* P9_20b (ball D2) gpio4_5*/
  1600. P9_20_pruout_pin: pinmux_P9_20_pruout_pin { pinctrl-single,pins = <
  1601. DRA7XX_CORE_IOPAD(0x3578, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE13) >; }; /* vin2a_d4.pr1_pru1_gpo1 */
  1602. P9_20_pruin_pin: pinmux_P9_20_pruin_pin { pinctrl-single,pins = <
  1603. DRA7XX_CORE_IOPAD(0x3578, PIN_INPUT | MUX_MODE12) >; }; /* vin2a_d4.pr1_pru1_gpi1 */
  1604.  
  1605. /* P9_21a (ball AF8) gpio3_3 */
  1606. P9_21_default_pin: pinmux_P9_21_default_pin { pinctrl-single,pins = <
  1607. DRA7XX_CORE_IOPAD(0x34F0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vin1a_vsync0.gpio3_3 */
  1608. P9_21_gpio_pin: pinmux_P9_21_gpio_pin { pinctrl-single,pins = <
  1609. DRA7XX_CORE_IOPAD(0x34F0, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vin1a_vsync0.gpio3_3 */
  1610. P9_21_gpio_pu_pin: pinmux_P9_21_gpio_pu_pin { pinctrl-single,pins = <
  1611. DRA7XX_CORE_IOPAD(0x34F0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vin1a_vsync0.gpio3_3 */
  1612. P9_21_gpio_pd_pin: pinmux_P9_21_gpio_pd_pin { pinctrl-single,pins = <
  1613. DRA7XX_CORE_IOPAD(0x34F0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vin1a_vsync0.gpio3_3 */
  1614. P9_21_gpio_input_pin: pinmux_P9_21_gpio_input_pin { pinctrl-single,pins = <
  1615. DRA7XX_CORE_IOPAD(0x34F0, PIN_INPUT | MUX_MODE14) >; }; /* vin1a_vsync0.gpio3_3 */
  1616. P9_21_qep_pin: pinmux_P9_21_qep_pin { pinctrl-single,pins = <
  1617. DRA7XX_CORE_IOPAD(0x34F0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE10) >; }; /* vin1a_vsync0.eQEP1_strobe */
  1618.  
  1619. /* P9_21b (ball B22) gpio7_15 */
  1620. P9_21_spi_pin: pinmux_P9_21_spi_pin { pinctrl-single,pins = <
  1621. DRA7XX_CORE_IOPAD(0x37C4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE0) >; }; /* spi2_d1.spi2_d1 */
  1622. P9_21_uart_pin: pinmux_P9_21_uart_pin { pinctrl-single,pins = <
  1623. DRA7XX_CORE_IOPAD(0x37C4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE1) >; }; /* spi2_d1.uart3_txd */
  1624.  
  1625. /* P9_22a (ball B26) gpio6_19 */
  1626. P9_22_default_pin: pinmux_P9_22_default_pin { pinctrl-single,pins = <
  1627. DRA7XX_CORE_IOPAD(0x369C, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* xref_clk2.gpio6_19 */
  1628. P9_22_gpio_pin: pinmux_P9_22_gpio_pin { pinctrl-single,pins = <
  1629. DRA7XX_CORE_IOPAD(0x369C, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* xref_clk2.gpio6_19 */
  1630. P9_22_gpio_pu_pin: pinmux_P9_22_gpio_pu_pin { pinctrl-single,pins = <
  1631. DRA7XX_CORE_IOPAD(0x369C, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* xref_clk2.gpio6_19 */
  1632. P9_22_gpio_pd_pin: pinmux_P9_22_gpio_pd_pin { pinctrl-single,pins = <
  1633. DRA7XX_CORE_IOPAD(0x369C, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* xref_clk2.gpio6_19 */
  1634. P9_22_gpio_input_pin: pinmux_P9_22_gpio_input_pin { pinctrl-single,pins = <
  1635. DRA7XX_CORE_IOPAD(0x369C, PIN_INPUT | MUX_MODE14) >; }; /* xref_clk2.gpio6_19 */
  1636.  
  1637. /* P9_22b (ball A26) gpio7_14 */
  1638. P9_22_spi_sclk_pin: pinmux_P9_22_spi_sclk_pin { pinctrl-single,pins = <
  1639. DRA7XX_CORE_IOPAD(0x37C0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE0) >; }; /* spi2_sclk.spi2_sclk */
  1640. P9_22_uart_pin: pinmux_P9_22_uart_pin { pinctrl-single,pins = <
  1641. DRA7XX_CORE_IOPAD(0x37C0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE1) >; }; /* spi2_sclk.uart3_rxd */
  1642.  
  1643. /* P9_23 (ball A22) gpio7_11 */
  1644. P9_23_default_pin: pinmux_P9_23_default_pin { pinctrl-single,pins = <
  1645. DRA7XX_CORE_IOPAD(0x37B4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* spi1_cs1.gpio7_11 */
  1646. P9_23_gpio_pin: pinmux_P9_23_gpio_pin { pinctrl-single,pins = <
  1647. DRA7XX_CORE_IOPAD(0x37B4, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* spi1_cs1.gpio7_11 */
  1648. P9_23_gpio_pu_pin: pinmux_P9_23_gpio_pu_pin { pinctrl-single,pins = <
  1649. DRA7XX_CORE_IOPAD(0x37B4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* spi1_cs1.gpio7_11 */
  1650. P9_23_gpio_pd_pin: pinmux_P9_23_gpio_pd_pin { pinctrl-single,pins = <
  1651. DRA7XX_CORE_IOPAD(0x37B4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* spi1_cs1.gpio7_11 */
  1652. P9_23_gpio_input_pin: pinmux_P9_23_gpio_input_pin { pinctrl-single,pins = <
  1653. DRA7XX_CORE_IOPAD(0x37B4, PIN_INPUT | MUX_MODE14) >; }; /* spi1_cs1.gpio7_11 */
  1654.  
  1655. /* P9_24 (ball F20) gpio6_15*/
  1656. P9_24_default_pin: pinmux_P9_24_default_pin { pinctrl-single,pins = <
  1657. DRA7XX_CORE_IOPAD(0x368C, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* gpio6_15.gpio6_15 */
  1658. P9_24_gpio_pin: pinmux_P9_24_gpio_pin { pinctrl-single,pins = <
  1659. DRA7XX_CORE_IOPAD(0x368C, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* gpio6_15.gpio6_15 */
  1660. P9_24_gpio_pu_pin: pinmux_P9_24_gpio_pu_pin { pinctrl-single,pins = <
  1661. DRA7XX_CORE_IOPAD(0x368C, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* gpio6_15.gpio6_15 */
  1662. P9_24_gpio_pd_pin: pinmux_P9_24_gpio_pd_pin { pinctrl-single,pins = <
  1663. DRA7XX_CORE_IOPAD(0x368C, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* gpio6_15.gpio6_15 */
  1664. P9_24_gpio_input_pin: pinmux_P9_24_gpio_input_pin { pinctrl-single,pins = <
  1665. DRA7XX_CORE_IOPAD(0x368C, PIN_INPUT | MUX_MODE14) >; }; /* gpio6_15.gpio6_15 */
  1666. P9_24_uart_pin: pinmux_P9_24_uart_pin { pinctrl-single,pins = <
  1667. DRA7XX_CORE_IOPAD(0x368C, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; }; /* gpio6_15.uart10_txd */
  1668. P9_24_can_pin: pinmux_P9_24_can_pin { pinctrl-single,pins = <
  1669. DRA7XX_CORE_IOPAD(0x368C, PIN_INPUT_PULLUP | MUX_MODE2) >; }; /* gpio6_15.dcan2_rx */
  1670. P9_24_i2c_pin: pinmux_P9_24_i2c_pin { pinctrl-single,pins = <
  1671. DRA7XX_CORE_IOPAD(0x368C, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE9) >; }; /* gpio6_15.i2c3_scl */
  1672.  
  1673. /* P9_25 (ball D18) gpio6_17 */
  1674. P9_25_default_pin: pinmux_P9_25_default_pin { pinctrl-single,pins = <
  1675. DRA7XX_CORE_IOPAD(0x3694, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* xref_clk0.gpio6_17 */
  1676. P9_25_gpio_pin: pinmux_P9_25_gpio_pin { pinctrl-single,pins = <
  1677. DRA7XX_CORE_IOPAD(0x3694, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* xref_clk0.gpio6_17 */
  1678. P9_25_gpio_pu_pin: pinmux_P9_25_gpio_pu_pin { pinctrl-single,pins = <
  1679. DRA7XX_CORE_IOPAD(0x3694, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* xref_clk0.gpio6_17 */
  1680. P9_25_gpio_pd_pin: pinmux_P9_25_gpio_pd_pin { pinctrl-single,pins = <
  1681. DRA7XX_CORE_IOPAD(0x3694, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* xref_clk0.gpio6_17 */
  1682. P9_25_gpio_input_pin: pinmux_P9_25_gpio_input_pin { pinctrl-single,pins = <
  1683. DRA7XX_CORE_IOPAD(0x3694, PIN_INPUT | MUX_MODE14) >; }; /* xref_clk0.gpio6_17 */
  1684. P9_25_pruout_pin: pinmux_P9_25_pruout_pin { pinctrl-single,pins = <
  1685. DRA7XX_CORE_IOPAD(0x3694, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE13) >; }; /* xref_clk0.pr2_pru1_gpo5 */
  1686. P9_25_pruin_pin: pinmux_P9_25_pruin_pin { pinctrl-single,pins = <
  1687. DRA7XX_CORE_IOPAD(0x3694, PIN_INPUT | MUX_MODE12) >; }; /* xref_clk0.pr2_pru1_gpi5 */
  1688.  
  1689. /* P9_26a (ball E21) gpio6_14 */
  1690. P9_26_default_pin: pinmux_P9_26_default_pin { pinctrl-single,pins = <
  1691. DRA7XX_CORE_IOPAD(0x3688, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* gpio6_14.gpio6_14 */
  1692. P9_26_gpio_pin: pinmux_P9_26_gpio_pin { pinctrl-single,pins = <
  1693. DRA7XX_CORE_IOPAD(0x3688, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* gpio6_14.gpio6_14 */
  1694. P9_26_gpio_pu_pin: pinmux_P9_26_gpio_pu_pin { pinctrl-single,pins = <
  1695. DRA7XX_CORE_IOPAD(0x3688, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* gpio6_14.gpio6_14 */
  1696. P9_26_gpio_pd_pin: pinmux_P9_26_gpio_pd_pin { pinctrl-single,pins = <
  1697. DRA7XX_CORE_IOPAD(0x3688, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* gpio6_14.gpio6_14 */
  1698. P9_26_gpio_input_pin: pinmux_P9_26_gpio_input_pin { pinctrl-single,pins = <
  1699. DRA7XX_CORE_IOPAD(0x3688, PIN_INPUT | MUX_MODE14) >; }; /* gpio6_14.gpio6_14 */
  1700. P9_26_uart_pin: pinmux_P9_26_uart_pin { pinctrl-single,pins = <
  1701. DRA7XX_CORE_IOPAD(0x3688, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; }; /* gpio6_14.uart10_rxd */
  1702. P9_26_can_pin: pinmux_P9_26_can_pin { pinctrl-single,pins = <
  1703. DRA7XX_CORE_IOPAD(0x3688, PIN_OUTPUT_PULLUP | MUX_MODE2) >; }; /* gpio6_14.dcan2_tx */
  1704. P9_26_i2c_pin: pinmux_P9_26_i2c_pin { pinctrl-single,pins = <
  1705. DRA7XX_CORE_IOPAD(0x3688, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE9) >; }; /* gpio6_14.i2c3_sda */
  1706.  
  1707. /* P9_26b (ball AE2) gpio3_24 */
  1708. P9_26_pruout_pin: pinmux_P9_26_pruout_pin { pinctrl-single,pins = <
  1709. DRA7XX_CORE_IOPAD(0x3544, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE13) >; }; /* vin1a_d20.pr1_pru0_gpo17*/
  1710. P9_26_pruin_pin: pinmux_P9_26_pruin_pin { pinctrl-single,pins = <
  1711. DRA7XX_CORE_IOPAD(0x3544, PIN_INPUT | MUX_MODE12) >; }; /* vin1a_d20.pr1_pru0_gpi17*/
  1712.  
  1713. /* P9_27a (ball C3) gpio4_15 */
  1714. P9_27_default_pin: pinmux_P9_27_default_pin { pinctrl-single,pins = <
  1715. DRA7XX_CORE_IOPAD(0x35A0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d14.gpio4_15 */
  1716. P9_27_gpio_pin: pinmux_P9_27_gpio_pin { pinctrl-single,pins = <
  1717. DRA7XX_CORE_IOPAD(0x35A0, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d14.gpio4_15 */
  1718. P9_27_gpio_pu_pin: pinmux_P9_27_gpio_pu_pin { pinctrl-single,pins = <
  1719. DRA7XX_CORE_IOPAD(0x35A0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d14.gpio4_15 */
  1720. P9_27_gpio_pd_pin: pinmux_P9_27_gpio_pd_pin { pinctrl-single,pins = <
  1721. DRA7XX_CORE_IOPAD(0x35A0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* vin2a_d14.gpio4_15 */
  1722. P9_27_gpio_input_pin: pinmux_P9_27_gpio_input_pin { pinctrl-single,pins = <
  1723. DRA7XX_CORE_IOPAD(0x35A0, PIN_INPUT | MUX_MODE14) >; }; /* vin2a_d14.gpio4_15 */
  1724. P9_27_qep_pin: pinmux_P9_27_qep_pin { pinctrl-single,pins = <
  1725. DRA7XX_CORE_IOPAD(0x35A0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE10) >; }; /* vin2a_d14.eQEP3B_in */
  1726. P9_27_pruout_pin: pinmux_P9_27_pruout_pin { pinctrl-single,pins = <
  1727. DRA7XX_CORE_IOPAD(0x35A0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE13) >; }; /* vin2a_d14.pr1_pru1_gpo11 */
  1728. P9_27_pruin_pin: pinmux_P9_27_pruin_pin { pinctrl-single,pins = <
  1729. DRA7XX_CORE_IOPAD(0x35A0, PIN_INPUT | MUX_MODE12) >; }; /* vin2a_d14.pr1_pru1_gpi11 */
  1730.  
  1731. /* P9_27b (ball J14) gpio5_1 */
  1732.  
  1733.  
  1734. /* P9_28 (ball A12) gpio4_17 */
  1735. P9_28_default_pin: pinmux_P9_28_default_pin { pinctrl-single,pins = <
  1736. DRA7XX_CORE_IOPAD(0x36E0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_axr11.gpio4_17 */
  1737. P9_28_gpio_pin: pinmux_P9_28_gpio_pin { pinctrl-single,pins = <
  1738. DRA7XX_CORE_IOPAD(0x36E0, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_axr11.gpio4_17 */
  1739. P9_28_gpio_pu_pin: pinmux_P9_28_gpio_pu_pin { pinctrl-single,pins = <
  1740. DRA7XX_CORE_IOPAD(0x36E0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_axr11.gpio4_17 */
  1741. P9_28_gpio_pd_pin: pinmux_P9_28_gpio_pd_pin { pinctrl-single,pins = <
  1742. DRA7XX_CORE_IOPAD(0x36E0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_axr11.gpio4_17 */
  1743. P9_28_gpio_input_pin: pinmux_P9_28_gpio_input_pin { pinctrl-single,pins = <
  1744. DRA7XX_CORE_IOPAD(0x36E0, PIN_INPUT | MUX_MODE14) >; }; /* mcasp1_axr11.gpio4_17 */
  1745. P9_28_spi_cs_pin: pinmux_P9_28_spi_cs_pin { pinctrl-single,pins = <
  1746. DRA7XX_CORE_IOPAD(0x36E0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; }; /* mcasp1_axr11.spi3_cs0 */
  1747. P9_28_pruout_pin: pinmux_P9_28_pruout_pin { pinctrl-single,pins = <
  1748. DRA7XX_CORE_IOPAD(0x36E0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE13) >; }; /* mcasp1_axr11.pr2_pru1_gpo13 */
  1749. P9_28_pruin_pin: pinmux_P9_28_pruin_pin { pinctrl-single,pins = <
  1750. DRA7XX_CORE_IOPAD(0x36E0, PIN_INPUT | MUX_MODE12) >; }; /* mcasp1_axr11.pr2_pru1_gpi13 */
  1751.  
  1752. /* P9_29a (ball A11) gpio5_11*/
  1753. P9_29_default_pin: pinmux_P9_29_default_pin { pinctrl-single,pins = <
  1754. DRA7XX_CORE_IOPAD(0x36D8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_axr9.gpio5_11 */
  1755. P9_29_gpio_pin: pinmux_P9_29_gpio_pin { pinctrl-single,pins = <
  1756. DRA7XX_CORE_IOPAD(0x36D8, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_axr9.gpio5_11 */
  1757. P9_29_gpio_pu_pin: pinmux_P9_29_gpio_pu_pin { pinctrl-single,pins = <
  1758. DRA7XX_CORE_IOPAD(0x36D8, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_axr9.gpio5_11 */
  1759. P9_29_gpio_pd_pin: pinmux_P9_29_gpio_pd_pin { pinctrl-single,pins = <
  1760. DRA7XX_CORE_IOPAD(0x36D8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_axr9.gpio5_11 */
  1761. P9_29_gpio_input_pin: pinmux_P9_29_gpio_input_pin { pinctrl-single,pins = <
  1762. DRA7XX_CORE_IOPAD(0x36D8, PIN_INPUT | MUX_MODE14) >; }; /* mcasp1_axr9.gpio5_11 */
  1763. P9_29_spi_pin: pinmux_P9_29_spi_pin { pinctrl-single,pins = <
  1764. DRA7XX_CORE_IOPAD(0x36D8, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; }; /* mcasp1_axr9.spi3_d1 */
  1765. P9_29_pruout_pin: pinmux_P9_29_pruout_pin { pinctrl-single,pins = <
  1766. DRA7XX_CORE_IOPAD(0x36D8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE13) >; }; /* mcasp1_axr9.pr2_pru1_gpo11 */
  1767. P9_29_pruin_pin: pinmux_P9_29_pruin_pin { pinctrl-single,pins = <
  1768. DRA7XX_CORE_IOPAD(0x36D8, PIN_INPUT | MUX_MODE12) >; }; /* mcasp1_axr9.pr2_pru1_gpi11 */
  1769.  
  1770. /* P9_29b (ball D14) gpio7_30 */
  1771.  
  1772.  
  1773. /* P9_30 (ball B13) gpio5_12*/
  1774. P9_30_default_pin: pinmux_P9_30_default_pin { pinctrl-single,pins = <
  1775. DRA7XX_CORE_IOPAD(0x36DC, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_axr10.gpio5_12 */
  1776. P9_30_gpio_pin: pinmux_P9_30_gpio_pin { pinctrl-single,pins = <
  1777. DRA7XX_CORE_IOPAD(0x36DC, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_axr10.gpio5_12 */
  1778. P9_30_gpio_pu_pin: pinmux_P9_30_gpio_pu_pin { pinctrl-single,pins = <
  1779. DRA7XX_CORE_IOPAD(0x36DC, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_axr10.gpio5_12 */
  1780. P9_30_gpio_pd_pin: pinmux_P9_30_gpio_pd_pin { pinctrl-single,pins = <
  1781. DRA7XX_CORE_IOPAD(0x36DC, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_axr10.gpio5_12 */
  1782. P9_30_gpio_input_pin: pinmux_P9_30_gpio_input_pin { pinctrl-single,pins = <
  1783. DRA7XX_CORE_IOPAD(0x36DC, PIN_INPUT | MUX_MODE14) >; }; /* mcasp1_axr10.gpio5_12 */
  1784. P9_30_spi_pin: pinmux_P9_30_spi_pin { pinctrl-single,pins = <
  1785. DRA7XX_CORE_IOPAD(0x36DC, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; }; /* mcasp1_axr10.spi3_d0 */
  1786. P9_30_pruout_pin: pinmux_P9_30_pruout_pin { pinctrl-single,pins = <
  1787. DRA7XX_CORE_IOPAD(0x36DC, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE13) >; }; /* mcasp1_axr10.pr2_pru1_gpo12 */
  1788. P9_30_pruin_pin: pinmux_P9_30_pruin_pin { pinctrl-single,pins = <
  1789. DRA7XX_CORE_IOPAD(0x36DC, PIN_INPUT | MUX_MODE12) >; }; /* mcasp1_axr10.pr2_pru1_gpi12 */
  1790.  
  1791. /* P9_31a (ball B12) gpio5_10 */
  1792. P9_31_default_pin: pinmux_P9_31_default_pin { pinctrl-single,pins = <
  1793. DRA7XX_CORE_IOPAD(0x36D4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_axr8.gpio5_10 */
  1794. P9_31_gpio_pin: pinmux_P9_31_gpio_pin { pinctrl-single,pins = <
  1795. DRA7XX_CORE_IOPAD(0x36D4, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_axr8.gpio5_10 */
  1796. P9_31_gpio_pu_pin: pinmux_P9_31_gpio_pu_pin { pinctrl-single,pins = <
  1797. DRA7XX_CORE_IOPAD(0x36D4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_axr8.gpio5_10 */
  1798. P9_31_gpio_pd_pin: pinmux_P9_31_gpio_pd_pin { pinctrl-single,pins = <
  1799. DRA7XX_CORE_IOPAD(0x36D4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_axr8.gpio5_10 */
  1800. P9_31_gpio_input_pin: pinmux_P9_31_gpio_input_pin { pinctrl-single,pins = <
  1801. DRA7XX_CORE_IOPAD(0x36D4, PIN_INPUT | MUX_MODE14) >; }; /* mcasp1_axr8.gpio5_10 */
  1802. P9_31_spi_sclk_pin: pinmux_P9_31_spi_sclk_pin { pinctrl-single,pins = <
  1803. DRA7XX_CORE_IOPAD(0x36D4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; }; /* mcasp1_axr8.spi3_sclk */
  1804. P9_31_pruout_pin: pinmux_P9_31_pruout_pin { pinctrl-single,pins = <
  1805. DRA7XX_CORE_IOPAD(0x36D4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE13) >; }; /* mcasp1_axr8.pr2_pru1_gpo10 */
  1806. P9_31_pruin_pin: pinmux_P9_31_pruin_pin { pinctrl-single,pins = <
  1807. DRA7XX_CORE_IOPAD(0x36D4, PIN_INPUT | MUX_MODE12) >; }; /* mcasp1_axr8.pr2_pru1_gpi10 */
  1808.  
  1809. /* P9_31b (ball C14) gpio7_31*/
  1810.  
  1811. /* P9_32 VADC */
  1812.  
  1813. /* P9_33 AIN4*/
  1814.  
  1815. /* P9_34 AGND */
  1816.  
  1817. /* P9_35 AIN6 */
  1818.  
  1819. /* P9_36 AIN5 */
  1820.  
  1821. /* P9_37 AIN2 */
  1822.  
  1823. /* P9_38 AIN3*/
  1824.  
  1825. /* P9_39 AIN0*/
  1826.  
  1827. /* P9_40 AIN1*/
  1828.  
  1829. /* P9_41a (ball C23) gpio6_20 */
  1830. P9_41_default_pin: pinmux_P9_41_default_pin { pinctrl-single,pins = <
  1831. DRA7XX_CORE_IOPAD(0x36A0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* xref_clk3.gpio6_20 */
  1832. P9_41_gpio_pin: pinmux_P9_41_gpio_pin { pinctrl-single,pins = <
  1833. DRA7XX_CORE_IOPAD(0x36A0, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* xref_clk3.gpio6_20 */
  1834. P9_41_gpio_pu_pin: pinmux_P9_41_gpio_pu_pin { pinctrl-single,pins = <
  1835. DRA7XX_CORE_IOPAD(0x36A0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* xref_clk3.gpio6_20 */
  1836. P9_41_gpio_pd_pin: pinmux_P9_41_gpio_pd_pin { pinctrl-single,pins = <
  1837. DRA7XX_CORE_IOPAD(0x36A0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* xref_clk3.gpio6_20 */
  1838. P9_41_gpio_input_pin: pinmux_P9_41_gpio_input_pin { pinctrl-single,pins = <
  1839. DRA7XX_CORE_IOPAD(0x36A0, PIN_INPUT | MUX_MODE14) >; }; /* xref_clk3.gpio6_20 */
  1840.  
  1841. /* P9_41b (ball C1) gpio4_7 */
  1842. P9_41_pruout_pin: pinmux_P9_41_pruout_pin { pinctrl-single,pins = <
  1843. DRA7XX_CORE_IOPAD(0x3580, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE13) >; }; /* vin2a_d6.pr1_pru1_gpo3 */
  1844. P9_41_pruin_pin: pinmux_P9_41_pruin_pin { pinctrl-single,pins = <
  1845. DRA7XX_CORE_IOPAD(0x3580, PIN_INPUT | MUX_MODE12) >; }; /* vin2a_d6.pr1_pru1_gpi3 */
  1846.  
  1847. /* P9_42a (ball E14) gpio4_18 */
  1848. P9_42_default_pin: pinmux_P9_42_default_pin { pinctrl-single,pins = <
  1849. DRA7XX_CORE_IOPAD(0x36E4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_axr12.gpio4_18 */
  1850. P9_42_gpio_pin: pinmux_P9_42_gpio_pin { pinctrl-single,pins = <
  1851. DRA7XX_CORE_IOPAD(0x36E4, PIN_OUTPUT | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_axr12.gpio4_18 */
  1852. P9_42_gpio_pu_pin: pinmux_P9_42_gpio_pu_pin { pinctrl-single,pins = <
  1853. DRA7XX_CORE_IOPAD(0x36E4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_axr12.gpio4_18 */
  1854. P9_42_gpio_pd_pin: pinmux_P9_42_gpio_pd_pin { pinctrl-single,pins = <
  1855. DRA7XX_CORE_IOPAD(0x36E4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE14) >; }; /* mcasp1_axr12.gpio4_18 */
  1856. P9_42_gpio_input_pin: pinmux_P9_42_gpio_input_pin { pinctrl-single,pins = <
  1857. DRA7XX_CORE_IOPAD(0x36E4, PIN_INPUT | MUX_MODE14) >; }; /* mcasp1_axr12.gpio4_18 */
  1858. P9_42_spi_cs_pin: pinmux_P9_42_spi_cs_pin { pinctrl-single,pins = <
  1859. DRA7XX_CORE_IOPAD(0x36E4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; }; /* mcasp1_axr12.spi3_cs1 */
  1860.  
  1861. /* P9_42b (ball C2) gpio4_14*/
  1862. P9_42_pruout_pin: pinmux_P9_42_pruout_pin { pinctrl-single,pins = <
  1863. DRA7XX_CORE_IOPAD(0x359C, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE13) >; }; /* vin2a_d13.pr1_pru1_gpo10 */
  1864. P9_42_pruin_pin: pinmux_P9_42_pruin_pin { pinctrl-single,pins = <
  1865. DRA7XX_CORE_IOPAD(0x359C, PIN_INPUT | MUX_MODE12) >; }; /* vin2a_d13.pr1_pru1_gpi10 */
  1866.  
  1867. /* P9_43 GND */
  1868.  
  1869. /* P9_44 GND */
  1870.  
  1871. /* P9_45 GND */
  1872.  
  1873. /* P9_46 GND */
  1874.  
  1875. extcon_usb1_pins_default: extcon_usb1_pins_default {
  1876. pinctrl-single,pins = <
  1877. DRA7XX_CORE_IOPAD(0x3518, PIN_INPUT | MUX_MODE14) /* AG2: vin1a_d9.gpio3_13 - USR0 */
  1878. >;
  1879. };
  1880.  
  1881. led_pins_default: led_pins_default {
  1882. pinctrl-single,pins = <
  1883. DRA7XX_CORE_IOPAD(0x3528, PIN_OUTPUT | MUX_MODE14) /* AF6: vin1a_d13.gpio3_17 - USR0 */
  1884. DRA7XX_CORE_IOPAD(0x36c0, PIN_OUTPUT | MUX_MODE14) /* J11: mcasp1_axr3.gpio5_5 - USR1 */
  1885. DRA7XX_CORE_IOPAD(0x3520, PIN_OUTPUT | MUX_MODE14) /* AG5: vin1a_d12.gpio3_15 - USR2 */
  1886. DRA7XX_CORE_IOPAD(0x351c, PIN_OUTPUT | MUX_MODE14) /* AG3: vin1a_d10.gpio3_14 - USR3 */
  1887. DRA7XX_CORE_IOPAD(0x3500, PIN_OUTPUT | MUX_MODE14) /* AH6: vin1a_d3.gpio3_7 - USR4 */
  1888. >;
  1889. };
  1890.  
  1891. microsd_extra_pins_default: microsd_extra_pins_default {
  1892. pinctrl-single,pins = <
  1893. DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT_PULLUP | MUX_MODE14) /* W7: mmc1_sdcd.gpio6_27 - MMC1_SDCD */
  1894. >;
  1895. };
  1896.  
  1897. ethphy_extra_pins_default: ethphy_extra_pins_default {
  1898. pinctrl-single,pins = <
  1899. DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT_PULLUP | MUX_MODE14) /* N1: gpmc_advn_ale.gpio2_23 - RGMII_RST */
  1900. DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT | MUX_MODE14) /* Y1: uart3_txd.gpio5_19 - MII0_INT */
  1901. >;
  1902. };
  1903.  
  1904. emmc_pwrseq_pins_default: emmc_pwrseq_pins_default {
  1905. pinctrl-single,pins = <
  1906. DRA7XX_CORE_IOPAD(0x36c8, PIN_OUTPUT_PULLUP | MUX_MODE14) /* F13: mcasp1_axr5.gpio5_7 - eMMC_RSTn */
  1907. >;
  1908. };
  1909.  
  1910. brcmf_pwrseq_pins_default: brcmf_pwrseq_pins_default {
  1911. pinctrl-single,pins = <
  1912. DRA7XX_CORE_IOPAD(0x352c, PIN_OUTPUT_PULLUP | MUX_MODE14) /* AF3: vin1a_d14.gpio3_18 - WL_REG_ON */
  1913. DRA7XX_CORE_IOPAD(0x353c, PIN_OUTPUT_PULLUP | MUX_MODE14) /* AE5: vin1a_d18.gpio3_22 - BT_REG_ON */
  1914. >;
  1915. };
  1916.  
  1917. wifibt_extra_pins_default: wifibt_extra_pins_default {
  1918. pinctrl-single,pins = <
  1919. DRA7XX_CORE_IOPAD(0x3540, PIN_INPUT | MUX_MODE14) /* AE1: vin1a_d19.gpio3_23 - WL_HOST_WAKE */
  1920. DRA7XX_CORE_IOPAD(0x3450, PIN_INPUT | MUX_MODE8) /* P6: vin1a_d20.uart6_rxd - UART6_RXD */
  1921. DRA7XX_CORE_IOPAD(0x3454, PIN_INPUT | MUX_MODE8) /* R9: vin1a_d21.uart6_txd - UART6_TXD */
  1922. DRA7XX_CORE_IOPAD(0x3458, PIN_INPUT | MUX_MODE8) /* R5: vin1a_d22.uart6_ctsn - UART6_CTSN */
  1923. DRA7XX_CORE_IOPAD(0x345c, PIN_INPUT | MUX_MODE8) /* P5: vin1a_d23.uart6_rtsn - UART6_RTSN */
  1924. DRA7XX_CORE_IOPAD(0x3534, PIN_INPUT_PULLDOWN | MUX_MODE14) /* AF1: vin1a_d16.gpio3_20 - BT_HOST_WAKE */
  1925. DRA7XX_CORE_IOPAD(0x3538, PIN_OUTPUT_PULLDOWN | MUX_MODE14) /* AE3: vin1a_d6.gpio3_21 - BT_WAKE */
  1926. >;
  1927. };
  1928.  
  1929. adc_pins_default: adc_pins_default {
  1930. pinctrl-single,pins = <
  1931. DRA7XX_CORE_IOPAD(0x3550, PIN_OUTPUT | MUX_MODE14) /* AD3: vin1a_d23.gpio3_27 - VDD_ADC_SEL */
  1932. DRA7XX_CORE_IOPAD(0x34DC, PIN_INPUT_PULLUP | MUX_MODE14) /* AG8: vin1a_clk0.gpio2_30 - INT_ADC */
  1933. >;
  1934. };
  1935.  
  1936. pmic_pins_default: pmic_pins_default {
  1937. pinctrl-single,pins = <
  1938. DRA7XX_CORE_IOPAD(0x3690, PIN_INPUT_PULLUP | MUX_MODE14) /* F21: gpio6_16.gpio6_16 - PMIC_INT */
  1939. >;
  1940. };
  1941.  
  1942. hdmi_pins_default: hdmi_pins_default {
  1943. pinctrl-single,pins = <
  1944. DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* C25: i2c2_sda.hdmi1_ddc_scl - HDMI_DDC_SCL */
  1945. DRA7XX_CORE_IOPAD(0x380C, PIN_INPUT | MUX_MODE1) /* F17: i2c2_scl.hdmi1_ddc_sda - HDMI_DDC_SDA */
  1946. DRA7XX_CORE_IOPAD(0x37BC, PIN_INPUT | MUX_MODE6) /* B20: spi1_cs3.hdmi1_cec - HDMI_DDC_CEC */
  1947. #if 0
  1948. DRA7XX_CORE_IOPAD(0x37B8, PIN_INPUT | MUX_MODE6) /* B21: spi1_cs2.hdmi1_hpd - HDMI_DDC_HPD */
  1949. #else
  1950. DRA7XX_CORE_IOPAD(0x37B8, PIN_INPUT | MUX_MODE14) /* B21: spi1_cs2.gpio7_12 - HDMI_DDC_HPD */
  1951. #endif
  1952. >;
  1953. };
  1954.  
  1955. unused_pins_default: unused_pins_default {
  1956. pinctrl-single,pins = <
  1957. DRA7XX_CORE_IOPAD(0x3400, MUX_MODE15) /* M6: sysboot0 */
  1958. DRA7XX_CORE_IOPAD(0x3404, MUX_MODE15) /* M2: sysboot1 */
  1959. DRA7XX_CORE_IOPAD(0x3408, MUX_MODE15) /* L5: sysboot2 */
  1960. DRA7XX_CORE_IOPAD(0x340C, MUX_MODE15) /* M1: sysboot3 */
  1961. DRA7XX_CORE_IOPAD(0x3410, MUX_MODE15) /* L6: sysboot4 */
  1962. DRA7XX_CORE_IOPAD(0x3414, MUX_MODE15) /* L4: sysboot5 */
  1963. DRA7XX_CORE_IOPAD(0x3418, MUX_MODE15) /* L3: sysboot6 */
  1964. DRA7XX_CORE_IOPAD(0x341C, MUX_MODE15) /* L2: sysboot7 */
  1965. DRA7XX_CORE_IOPAD(0x3420, MUX_MODE15) /* L1: sysboot8 */
  1966. DRA7XX_CORE_IOPAD(0x3424, MUX_MODE15) /* K2: sysboot9 */
  1967. DRA7XX_CORE_IOPAD(0x3428, MUX_MODE15) /* J1: sysboot10 */
  1968. DRA7XX_CORE_IOPAD(0x342C, MUX_MODE15) /* J2: sysboot11 */
  1969. DRA7XX_CORE_IOPAD(0x3430, MUX_MODE15) /* H1: sysboot12 */
  1970. DRA7XX_CORE_IOPAD(0x3434, MUX_MODE15) /* J3: sysboot13 */
  1971. DRA7XX_CORE_IOPAD(0x3438, MUX_MODE15) /* H2: sysboot14 */
  1972. DRA7XX_CORE_IOPAD(0x343C, MUX_MODE15) /* H3: sysboot15 */
  1973.  
  1974. DRA7XX_CORE_IOPAD(0x3448, MUX_MODE15) /* T6: N/C */
  1975. DRA7XX_CORE_IOPAD(0x344C, MUX_MODE15) /* T7: N/C */
  1976.  
  1977. DRA7XX_CORE_IOPAD(0x3460, MUX_MODE15) /* N7: N/C */
  1978. DRA7XX_CORE_IOPAD(0x3464, MUX_MODE15) /* R4: N/C */
  1979. DRA7XX_CORE_IOPAD(0x3468, MUX_MODE15) /* N9: N/C */
  1980. DRA7XX_CORE_IOPAD(0x346C, MUX_MODE15) /* P9: N/C */
  1981. DRA7XX_CORE_IOPAD(0x3470, MUX_MODE15) /* P4: N/C */
  1982. DRA7XX_CORE_IOPAD(0x3474, MUX_MODE15) /* R3: N/C */
  1983. DRA7XX_CORE_IOPAD(0x3478, MUX_MODE15) /* T2: N/C */
  1984. DRA7XX_CORE_IOPAD(0x347C, MUX_MODE15) /* U2: N/C */
  1985. DRA7XX_CORE_IOPAD(0x3480, MUX_MODE15) /* U1: N/C */
  1986. DRA7XX_CORE_IOPAD(0x3484, MUX_MODE15) /* P3: N/C */
  1987. DRA7XX_CORE_IOPAD(0x3488, MUX_MODE15) /* R2: N/C */
  1988.  
  1989. DRA7XX_CORE_IOPAD(0x34B4, MUX_MODE15) /* T1: N/C */
  1990. DRA7XX_CORE_IOPAD(0x34B8, MUX_MODE15) /* P2: N/C */
  1991. DRA7XX_CORE_IOPAD(0x34BC, MUX_MODE15) /* P1: N/C */
  1992. DRA7XX_CORE_IOPAD(0x34C0, MUX_MODE15) /* P7: N/C */
  1993. DRA7XX_CORE_IOPAD(0x34C4, MUX_MODE15) /* N1: N/C */
  1994. DRA7XX_CORE_IOPAD(0x34C8, MUX_MODE15) /* M5: N/C */
  1995. DRA7XX_CORE_IOPAD(0x34CC, MUX_MODE15) /* M3: N/C */
  1996. DRA7XX_CORE_IOPAD(0x34D0, MUX_MODE15) /* N6: N/C */
  1997. DRA7XX_CORE_IOPAD(0x34D4, MUX_MODE15) /* M4: N/C */
  1998. DRA7XX_CORE_IOPAD(0x34D8, MUX_MODE15) /* N2: N/C */
  1999.  
  2000. DRA7XX_CORE_IOPAD(0x34E0, MUX_MODE15) /* AH7: N/C */
  2001.  
  2002. DRA7XX_CORE_IOPAD(0x34EC, MUX_MODE15) /* AE9: N/C */
  2003.  
  2004. DRA7XX_CORE_IOPAD(0x34F4, MUX_MODE15) /* AE8: N/C */
  2005. DRA7XX_CORE_IOPAD(0x34F8, MUX_MODE15) /* AD8: N/C */
  2006. DRA7XX_CORE_IOPAD(0x34FC, MUX_MODE15) /* AG7: N/C */
  2007.  
  2008. DRA7XX_CORE_IOPAD(0x3504, MUX_MODE15) /* AH3: N/C */
  2009. DRA7XX_CORE_IOPAD(0x3508, MUX_MODE15) /* AH5: N/C */
  2010.  
  2011. DRA7XX_CORE_IOPAD(0x3524, MUX_MODE15) /* AF2: N/C */
  2012.  
  2013. DRA7XX_CORE_IOPAD(0x3530, MUX_MODE15) /* AF4: N/C */
  2014.  
  2015. DRA7XX_CORE_IOPAD(0x354C, MUX_MODE15) /* AD2: N/C */
  2016.  
  2017. DRA7XX_CORE_IOPAD(0x3554, MUX_MODE15) /* E1: N/C */
  2018. DRA7XX_CORE_IOPAD(0x3558, MUX_MODE15) /* G2: N/C */
  2019. DRA7XX_CORE_IOPAD(0x355C, MUX_MODE15) /* H7: N/C */
  2020. DRA7XX_CORE_IOPAD(0x3560, MUX_MODE15) /* G1: N/C */
  2021.  
  2022. DRA7XX_CORE_IOPAD(0x356C, MUX_MODE15) /* F3: N/C */
  2023.  
  2024. DRA7XX_CORE_IOPAD(0x3574, MUX_MODE15) /* E2: N/C */
  2025.  
  2026. DRA7XX_CORE_IOPAD(0x3584, MUX_MODE15) /* E4: N/C */
  2027.  
  2028. DRA7XX_CORE_IOPAD(0x3594, MUX_MODE15) /* F6: N/C */
  2029.  
  2030. DRA7XX_CORE_IOPAD(0x35A4, MUX_MODE15) /* C4: N/C */
  2031. DRA7XX_CORE_IOPAD(0x35A8, MUX_MODE15) /* B2: N/C */
  2032.  
  2033. DRA7XX_CORE_IOPAD(0x35C0, MUX_MODE15) /* B5: N/C */
  2034. DRA7XX_CORE_IOPAD(0x35C4, MUX_MODE15) /* A4: N/C */
  2035.  
  2036. DRA7XX_CORE_IOPAD(0x35D0, MUX_MODE15) /* B11: N/C */
  2037.  
  2038. DRA7XX_CORE_IOPAD(0x3644, MUX_MODE15) /* U3: N/C */
  2039.  
  2040. DRA7XX_CORE_IOPAD(0x3680, MUX_MODE15) /* AB10: N/C */
  2041.  
  2042. DRA7XX_CORE_IOPAD(0x36BC, MUX_MODE15) /* G13: N/C */
  2043.  
  2044. DRA7XX_CORE_IOPAD(0x36C4, MUX_MODE15) /* E12: N/C */
  2045.  
  2046. DRA7XX_CORE_IOPAD(0x36CC, MUX_MODE15) /* C12: N/C */
  2047. DRA7XX_CORE_IOPAD(0x36D0, MUX_MODE15) /* D12: N/C */
  2048.  
  2049. DRA7XX_CORE_IOPAD(0x36FC, MUX_MODE15) /* E15: N/C */
  2050. DRA7XX_CORE_IOPAD(0x3700, MUX_MODE15) /* A20: N/C */
  2051.  
  2052. DRA7XX_CORE_IOPAD(0x370C, MUX_MODE15) /* C15: N/C */
  2053. DRA7XX_CORE_IOPAD(0x3710, MUX_MODE15) /* A16: N/C */
  2054. DRA7XX_CORE_IOPAD(0x3714, MUX_MODE15) /* D15: N/C */
  2055. DRA7XX_CORE_IOPAD(0x3718, MUX_MODE15) /* B16: N/C */
  2056. DRA7XX_CORE_IOPAD(0x371C, MUX_MODE15) /* B17: N/C */
  2057. DRA7XX_CORE_IOPAD(0x3720, MUX_MODE15) /* A17: N/C */
  2058. DRA7XX_CORE_IOPAD(0x3724, MUX_MODE15) /* B18: N/C */
  2059. DRA7XX_CORE_IOPAD(0x3728, MUX_MODE15) /* F15: N/C */
  2060.  
  2061. DRA7XX_CORE_IOPAD(0x3744, MUX_MODE15) /* AA3: N/C */
  2062. DRA7XX_CORE_IOPAD(0x3748, MUX_MODE15) /* AB9: N/C */
  2063. DRA7XX_CORE_IOPAD(0x374C, MUX_MODE15) /* AB3: N/C */
  2064. DRA7XX_CORE_IOPAD(0x3750, MUX_MODE15) /* AA4: N/C */
  2065.  
  2066. DRA7XX_CORE_IOPAD(0x3770, MUX_MODE15) /* Y9: N/C */
  2067. DRA7XX_CORE_IOPAD(0x3774, MUX_MODE15) /* AC5: N/C */
  2068. DRA7XX_CORE_IOPAD(0x3778, MUX_MODE15) /* AB4: N/C */
  2069.  
  2070. DRA7XX_CORE_IOPAD(0x37A4, MUX_MODE15) /* A25: N/C */
  2071. DRA7XX_CORE_IOPAD(0x37A8, MUX_MODE15) /* F16: N/C */
  2072. DRA7XX_CORE_IOPAD(0x37AC, MUX_MODE15) /* B25: N/C */
  2073. DRA7XX_CORE_IOPAD(0x37B0, MUX_MODE15) /* A24: N/C */
  2074.  
  2075. DRA7XX_CORE_IOPAD(0x37D0, MUX_MODE15) /* G20: N/C */
  2076. DRA7XX_CORE_IOPAD(0x37D4, MUX_MODE15) /* G19: N/C */
  2077.  
  2078. DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15) /* AD17: N/C */
  2079. DRA7XX_CORE_IOPAD(0x381C, MUX_MODE15) /* AC17: N/C */
  2080. DRA7XX_CORE_IOPAD(0x3820, MUX_MODE15) /* AB16: N/C */
  2081. DRA7XX_CORE_IOPAD(0x3824, MUX_MODE15) /* AC16: N/C */
  2082. >;
  2083. };
  2084.  
  2085. cape_pins_default: cape_pins_default {
  2086. pinctrl-single,pins = <
  2087. DRA7XX_CORE_IOPAD(0x379C, MUX_MODE14) /* AB8: P8.3: mmc3_dat6.off */
  2088. DRA7XX_CORE_IOPAD(0x37A0, MUX_MODE14) /* AB5: P8.4: mmc3_dat7.off */
  2089. DRA7XX_CORE_IOPAD(0x378C, MUX_MODE14) /* AC9: P8.5: mmc3_dat2.off */
  2090. DRA7XX_CORE_IOPAD(0x3790, MUX_MODE14) /* AC3: P8.6: mmc3_dat3.off */
  2091. DRA7XX_CORE_IOPAD(0x36EC, MUX_MODE14) /* G14: P8.7: mcasp1_axr14.off */
  2092. DRA7XX_CORE_IOPAD(0x36F0, MUX_MODE14) /* F14: P8.8: mcasp1_axr15.off */
  2093. DRA7XX_CORE_IOPAD(0x3698, MUX_MODE14) /* E17: P8.9: xref_clk1.off */
  2094. DRA7XX_CORE_IOPAD(0x36E8, MUX_MODE14) /* A13: P8.10: mcasp1_axr13.off */
  2095. DRA7XX_CORE_IOPAD(0x3510, MUX_MODE14) /* AH4: P8.11: vin1a_d7.off */
  2096. DRA7XX_CORE_IOPAD(0x350C, MUX_MODE14) /* AG6: P8.12: vin1a_d6.off */
  2097. DRA7XX_CORE_IOPAD(0x3590, PIN_INPUT | MUX_MODE12) /* D3: P8.13: vin2a_d10.off */
  2098. DRA7XX_CORE_IOPAD(0x3598, MUX_MODE14) /* D5: P8.14: vin2a_d12.off */
  2099. DRA7XX_CORE_IOPAD(0x3570, MUX_MODE14) /* D1: P8.15a: vin2a_d2.off */
  2100. DRA7XX_CORE_IOPAD(0x35B4, MUX_MODE13) /* A3: P8.15b: vin2a_d19.off */
  2101. DRA7XX_CORE_IOPAD(0x35BC, MUX_MODE13) /* B4: P8.16: vin2a_d21.off */
  2102. DRA7XX_CORE_IOPAD(0x3624, MUX_MODE14) /* A7: P8.17: vout1_d18.off */
  2103. DRA7XX_CORE_IOPAD(0x3588, PIN_INPUT | MUX_MODE12) /* F5: P8.18: vin2a_d8.off */
  2104. DRA7XX_CORE_IOPAD(0x358C, PIN_INPUT | MUX_MODE12) /* E6: P8.19: vin2a_d9.off */
  2105. DRA7XX_CORE_IOPAD(0x3780, MUX_MODE14) /* AC4: P8.20: mmc3_cmd.off */
  2106. DRA7XX_CORE_IOPAD(0x377C, MUX_MODE14) /* AD4: P8.21: mmc3_clk.off */
  2107. DRA7XX_CORE_IOPAD(0x3798, MUX_MODE14) /* AD6: P8.22: mmc3_dat5.off */
  2108. DRA7XX_CORE_IOPAD(0x3794, MUX_MODE14) /* AC8: P8.23: mmc3_dat4.off */
  2109. DRA7XX_CORE_IOPAD(0x3788, MUX_MODE14) /* AC6: P8.24: mmc3_dat1.off */
  2110. DRA7XX_CORE_IOPAD(0x3784, MUX_MODE14) /* AC7: P8.25: mmc3_dat0.off */
  2111. DRA7XX_CORE_IOPAD(0x35B8, MUX_MODE13) /* B3: P8.26: vin2a_d20.off */
  2112. DRA7XX_CORE_IOPAD(0x35D8, MUX_MODE14) /* E11: P8.27a: vout1_vsync.off */
  2113. DRA7XX_CORE_IOPAD(0x3628, MUX_MODE14) /* A8: P8.27b: vout1_d19.off */
  2114. DRA7XX_CORE_IOPAD(0x35C8, MUX_MODE14) /* D11: P8.28a: vout1_clk.off */
  2115. DRA7XX_CORE_IOPAD(0x362C, MUX_MODE14) /* C9: P8.28b: vout1_d20.off */
  2116. DRA7XX_CORE_IOPAD(0x35D4, MUX_MODE14) /* C11: P8.29a: vout1_hsync.off */
  2117. DRA7XX_CORE_IOPAD(0x3630, MUX_MODE14) /* A9: P8.29b: vout1_d21.off */
  2118. DRA7XX_CORE_IOPAD(0x35CC, MUX_MODE14) /* B10: P8.30a: vout1_de.off */
  2119. DRA7XX_CORE_IOPAD(0x3634, MUX_MODE14) /* B9: P8.30b: vout1_d22.off */
  2120. DRA7XX_CORE_IOPAD(0x3614, MUX_MODE14) /* C8: P8.31a: vout1_d14.off */
  2121. DRA7XX_CORE_IOPAD(0x373C, MUX_MODE14) /* G16: P8.31b: mcasp4_axr0.off */
  2122. DRA7XX_CORE_IOPAD(0x3618, MUX_MODE14) /* C7: P8.32a: vout1_d15.off */
  2123. DRA7XX_CORE_IOPAD(0x3740, MUX_MODE14) /* D17: P8.32b: mcasp4_axr1.off */
  2124. DRA7XX_CORE_IOPAD(0x3610, MUX_MODE14) /* C6: P8.33a: vout1_d13.off */
  2125. DRA7XX_CORE_IOPAD(0x34E8, MUX_MODE14) /* AF9: P8.33b: vin1a_fld0.off */
  2126. DRA7XX_CORE_IOPAD(0x3608, MUX_MODE14) /* D8: P8.34a: vout1_d11.off */
  2127. DRA7XX_CORE_IOPAD(0x3564, MUX_MODE14) /* G6: P8.34b: vin2a_vsync0.off */
  2128. DRA7XX_CORE_IOPAD(0x360C, MUX_MODE14) /* A5: P8.35a: vout1_d12.off */
  2129. DRA7XX_CORE_IOPAD(0x34E4, MUX_MODE14) /* AD9: P8.35b: vin1a_de0.off */
  2130. DRA7XX_CORE_IOPAD(0x3604, MUX_MODE14) /* D7: P8.36a: vout1_d10.off */
  2131. DRA7XX_CORE_IOPAD(0x3568, MUX_MODE14) /* F2: P8.36b: vin2a_d0.off */
  2132. DRA7XX_CORE_IOPAD(0x35FC, MUX_MODE14) /* E8: P8.37a: vout1_d8.off */
  2133. DRA7XX_CORE_IOPAD(0x3738, MUX_MODE14) /* A21: P8.37b: mcasp4_fsx.off */
  2134. DRA7XX_CORE_IOPAD(0x3600, MUX_MODE14) /* D9: P8.38a: vout1_d9.off */
  2135. DRA7XX_CORE_IOPAD(0x3734, MUX_MODE14) /* C18: P8.38b: mcasp4_aclkx.off */
  2136. DRA7XX_CORE_IOPAD(0x35F4, MUX_MODE14) /* F8: P8.39: vout1_d6.off */
  2137. DRA7XX_CORE_IOPAD(0x35F8, MUX_MODE14) /* E7: P8.40: vout1_d7.off */
  2138. DRA7XX_CORE_IOPAD(0x35EC, MUX_MODE14) /* E9: P8.41: vout1_d4.off */
  2139. DRA7XX_CORE_IOPAD(0x35F0, MUX_MODE14) /* F9: P8.42: vout1_d5.off */
  2140. DRA7XX_CORE_IOPAD(0x35E4, MUX_MODE14) /* F10: P8.43: vout1_d2.off */
  2141. DRA7XX_CORE_IOPAD(0x35E8, MUX_MODE14) /* G11: P8.44: vout1_d3.off */
  2142. DRA7XX_CORE_IOPAD(0x35DC, MUX_MODE14) /* F11: P8.45a: vout1_d0.off */
  2143. DRA7XX_CORE_IOPAD(0x361C, MUX_MODE14) /* B7: P8.45b: vout1_d16.off */
  2144. DRA7XX_CORE_IOPAD(0x35E0, MUX_MODE14) /* G10: P8.46a: vout1_d1.off */
  2145. DRA7XX_CORE_IOPAD(0x3638, MUX_MODE14) /* A10: P8.46b: vout1_d23.off */
  2146. DRA7XX_CORE_IOPAD(0x372C, MUX_MODE14) /* B19: P9.11a: mcasp3_axr0.off */
  2147. DRA7XX_CORE_IOPAD(0x3620, MUX_MODE14) /* B8: P9.11b: vout1_d17.off */
  2148. DRA7XX_CORE_IOPAD(0x36AC, MUX_MODE14) /* B14: P9.12: mcasp1_aclkr.off */
  2149. DRA7XX_CORE_IOPAD(0x3730, MUX_MODE14) /* C17: P9.13: mcasp3_axr1.off */
  2150. DRA7XX_CORE_IOPAD(0x35AC, MUX_MODE10) /* D6: P9.14: vin2a_d17.off */
  2151. DRA7XX_CORE_IOPAD(0x3514, MUX_MODE14) /* AG4: P9.15: vin1a_d8.off */
  2152. DRA7XX_CORE_IOPAD(0x35B0, MUX_MODE13) /* C5: P9.16: vin2a_d18.off */
  2153. DRA7XX_CORE_IOPAD(0x37CC, MUX_MODE14) /* B24: P9.17a: spi2_cs0.off */
  2154. DRA7XX_CORE_IOPAD(0x36B8, MUX_MODE14) /* F12: P9.17b: mcasp1_axr1.off */
  2155. DRA7XX_CORE_IOPAD(0x37C8, MUX_MODE14) /* G17: P9.18a: spi2_d0.off */
  2156. DRA7XX_CORE_IOPAD(0x36B4, MUX_MODE14) /* G12: P9.18b: mcasp1_axr0.off */
  2157. DRA7XX_CORE_IOPAD(0x3440, PIN_INPUT_PULLUP | MUX_MODE7) /* R6: P9.19a: gpmc_a0.i2c4_scl */
  2158. DRA7XX_CORE_IOPAD(0x357C, PIN_INPUT_PULLUP | MUX_MODE12 ) /* F4: P9.19b: vin2a_d5.pr1_pru1_gpi2 */
  2159. DRA7XX_CORE_IOPAD(0x3444, PIN_INPUT_PULLUP | MUX_MODE7) /* T9: P9.20a: gpmc_a1.i2c4_sda */
  2160. DRA7XX_CORE_IOPAD(0x3578, PIN_INPUT_PULLUP | MUX_MODE12) /* D2: P9.20b: vin2a_d4.pr1_pru1_gpi1 */
  2161. DRA7XX_CORE_IOPAD(0x34F0, MUX_MODE14) /* AF8: P9.21a: vin1a_vsync0.off */
  2162. DRA7XX_CORE_IOPAD(0x37C4, MUX_MODE14) /* B22: P9.21b: spi2_d1.off */
  2163. DRA7XX_CORE_IOPAD(0x369C, MUX_MODE14) /* B26: P9.22a: xref_clk2.off */
  2164. DRA7XX_CORE_IOPAD(0x37C0, MUX_MODE14) /* A26: P9.22b: spi2_sclk.off */
  2165. DRA7XX_CORE_IOPAD(0x37B4, MUX_MODE14) /* A22: P9.23: spi1_cs1.off */
  2166. DRA7XX_CORE_IOPAD(0x368C, MUX_MODE14) /* F20: P9.24: gpio6_15.off */
  2167. DRA7XX_CORE_IOPAD(0x3694, MUX_MODE14) /* D18: P9.25: xref_clk0.off */
  2168. DRA7XX_CORE_IOPAD(0x3688, MUX_MODE14) /* E21: P9.26a: gpio6_14.off */
  2169. DRA7XX_CORE_IOPAD(0x3544, MUX_MODE14) /* AE2: P9.26b: vin1a_d20.off */
  2170. DRA7XX_CORE_IOPAD(0x35A0, MUX_MODE14) /* C3: P9.27a: vin2a_d14.off */
  2171. DRA7XX_CORE_IOPAD(0x36B0, MUX_MODE14) /* J14: P9.27b: mcasp1_fsr.off */
  2172. DRA7XX_CORE_IOPAD(0x36E0, MUX_MODE14) /* A12: P9.28: mcasp1_axr11.off */
  2173. DRA7XX_CORE_IOPAD(0x36D8, MUX_MODE14) /* A11: P9.29a: mcasp1_axr9.off */
  2174. DRA7XX_CORE_IOPAD(0x36A8, MUX_MODE14) /* D14: P9.29b: mcasp1_fsx.off */
  2175. DRA7XX_CORE_IOPAD(0x36DC, MUX_MODE14) /* B13: P9.30: mcasp1_axr10.off */
  2176. DRA7XX_CORE_IOPAD(0x36D4, MUX_MODE14) /* B12: P9.31a: mcasp1_axr8.off */
  2177. DRA7XX_CORE_IOPAD(0x36A4, MUX_MODE14) /* C14: P9.31b: mcasp1_aclkx.off */
  2178. DRA7XX_CORE_IOPAD(0x36A0, MUX_MODE14) /* C23: P9.41a: xref_clk3.off */
  2179. DRA7XX_CORE_IOPAD(0x3580, MUX_MODE14) /* C1: P9.41b: vin2a_d6.off */
  2180. DRA7XX_CORE_IOPAD(0x36E4, MUX_MODE14) /* E14: P9.42a: mcasp1_axr12.off */
  2181. DRA7XX_CORE_IOPAD(0x359C, MUX_MODE14) /* C2: P9.42b: vin2a_d13.off */
  2182. >;
  2183. };
  2184. };
  2185.  
  2186. &vip2 {
  2187. status = "okay";
  2188. };
  2189.  
  2190. &i2c1 {
  2191. status = "okay";
  2192. clock-frequency = <400000>;
  2193.  
  2194. tps659038: tps659038@58 {
  2195. compatible = "ti,tps659038";
  2196. reg = <0x58>;
  2197. interrupt-parent = <&gpio6>;
  2198. interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
  2199.  
  2200. pinctrl-names = "default";
  2201. pinctrl-0 = <&pmic_pins_default>;
  2202.  
  2203. #interrupt-cells = <2>;
  2204. interrupt-controller;
  2205.  
  2206. ti,system-power-controller;
  2207. ti,palmas-override-powerhold;
  2208.  
  2209. tps659038_pmic {
  2210. compatible = "ti,tps659038-pmic";
  2211.  
  2212. smps12-in-supply = <&vdd_5v>;
  2213. smps3-in-supply = <&vdd_5v>;
  2214. smps45-in-supply = <&vdd_5v>;
  2215. smps6-in-supply = <&vdd_5v>;
  2216. smps7-in-supply = <&vdd_5v>;
  2217. mps3-in-supply = <&vdd_5v>;
  2218. smps8-in-supply = <&vdd_5v>;
  2219. smps9-in-supply = <&vdd_5v>;
  2220. ldo1-in-supply = <&vdd_5v>;
  2221. ldo2-in-supply = <&vdd_5v>;
  2222. ldo3-in-supply = <&vdd_5v>;
  2223. ldo4-in-supply = <&vdd_5v>;
  2224. ldo9-in-supply = <&vdd_5v>;
  2225. ldoln-in-supply = <&vdd_5v>;
  2226. ldousb-in-supply = <&vdd_5v>;
  2227. ldortc-in-supply = <&vdd_5v>;
  2228.  
  2229. regulators {
  2230. vdd_mpu: smps12 {
  2231. /* VDD_MPU */
  2232. regulator-name = "smps12";
  2233. regulator-min-microvolt = <850000>;
  2234. regulator-max-microvolt = <1250000>;
  2235. regulator-always-on;
  2236. regulator-boot-on;
  2237. };
  2238.  
  2239. vdd_ddr: smps3 {
  2240. /* VDD_DDR EMIF1 EMIF2 */
  2241. regulator-name = "smps3";
  2242. regulator-min-microvolt = <1350000>;
  2243. regulator-max-microvolt = <1350000>;
  2244. regulator-always-on;
  2245. regulator-boot-on;
  2246. };
  2247.  
  2248. vdd_dspeve: smps45 {
  2249. /* VDD_DSPEVE on AM572 */
  2250. regulator-name = "smps45";
  2251. regulator-min-microvolt = < 850000>;
  2252. regulator-max-microvolt = <1250000>;
  2253. regulator-always-on;
  2254. regulator-boot-on;
  2255. };
  2256.  
  2257. vdd_gpu: smps6 {
  2258. /* VDD_GPU */
  2259. regulator-name = "smps6";
  2260. regulator-min-microvolt = < 850000>;
  2261. regulator-max-microvolt = <1250000>;
  2262. regulator-always-on;
  2263. regulator-boot-on;
  2264. };
  2265.  
  2266. vdd_core: smps7 {
  2267. /* VDD_CORE */
  2268. regulator-name = "smps7";
  2269. regulator-min-microvolt = < 850000>; /*** 1.15V */
  2270. regulator-max-microvolt = <1150000>;
  2271. regulator-always-on;
  2272. regulator-boot-on;
  2273. };
  2274.  
  2275. vdd_iva: smps8 {
  2276. /* VDD_IVAHD */ /*** 1.06V */
  2277. regulator-name = "smps8";
  2278. };
  2279.  
  2280. vdd_3v3: smps9 {
  2281. /* VDD_3V3 */
  2282. regulator-name = "smps9";
  2283. regulator-min-microvolt = <3300000>;
  2284. regulator-max-microvolt = <3300000>;
  2285. regulator-always-on;
  2286. regulator-boot-on;
  2287. };
  2288.  
  2289. vdd_sd: ldo1 {
  2290. /* VDDSHV8 - VSDMMC */
  2291. regulator-name = "ldo1";
  2292. regulator-min-microvolt = <1800000>;
  2293. regulator-max-microvolt = <3300000>;
  2294. regulator-boot-on;
  2295. regulator-always-on;
  2296. };
  2297.  
  2298. vdd_1v8: ldo2 {
  2299. /* VDDSH18V */
  2300. regulator-name = "ldo2";
  2301. regulator-min-microvolt = <1800000>;
  2302. regulator-max-microvolt = <1800000>;
  2303. regulator-always-on;
  2304. regulator-boot-on;
  2305. };
  2306.  
  2307. vdd_1v8_phy_ldo3: ldo3 {
  2308. /* R1.3a 572x V1_8PHY_LDO3: USB, SATA */
  2309. regulator-name = "ldo3";
  2310. regulator-min-microvolt = <1800000>;
  2311. regulator-max-microvolt = <1800000>;
  2312. regulator-always-on;
  2313. regulator-boot-on;
  2314. };
  2315.  
  2316. vdd_1v8_phy_ldo4: ldo4 {
  2317. /* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/
  2318. regulator-name = "ldo4";
  2319. regulator-min-microvolt = <1800000>;
  2320. regulator-max-microvolt = <1800000>;
  2321. regulator-always-on;
  2322. regulator-boot-on;
  2323. };
  2324.  
  2325. /* LDO5-8 unused */
  2326.  
  2327. vdd_rtc: ldo9 {
  2328. /* VDD_RTC */
  2329. regulator-name = "ldo9";
  2330. regulator-min-microvolt = < 840000>;
  2331. regulator-max-microvolt = <1160000>;
  2332. regulator-always-on;
  2333. regulator-boot-on;
  2334. };
  2335.  
  2336. vdd_1v8_pll: ldoln {
  2337. /* VDDA_1V8_PLL */
  2338. regulator-name = "ldoln";
  2339. regulator-min-microvolt = <1800000>;
  2340. regulator-max-microvolt = <1800000>;
  2341. regulator-always-on;
  2342. regulator-boot-on;
  2343. };
  2344.  
  2345. ldousb_reg: ldousb {
  2346. /* VDDA_3V_USB: VDDA_USBHS33 */
  2347. regulator-name = "ldousb";
  2348. regulator-min-microvolt = <3300000>;
  2349. regulator-max-microvolt = <3300000>;
  2350. regulator-always-on;
  2351. regulator-boot-on;
  2352. };
  2353.  
  2354. ldortc_reg: ldortc {
  2355. /* VDDA_RTC */
  2356. regulator-name = "ldortc";
  2357. regulator-min-microvolt = <1800000>;
  2358. regulator-max-microvolt = <1800000>;
  2359. regulator-always-on;
  2360. regulator-boot-on;
  2361. };
  2362.  
  2363. regen1: regen1 {
  2364. /* VDD_3V3_ON */
  2365. regulator-name = "regen1";
  2366. regulator-boot-on;
  2367. regulator-always-on;
  2368. };
  2369.  
  2370. regen2: regen2 {
  2371. /* Needed for PMIC internal resource */
  2372. regulator-name = "regen2";
  2373. regulator-boot-on;
  2374. regulator-always-on;
  2375. };
  2376. };
  2377. };
  2378.  
  2379. tps659038_rtc: tps659038_rtc {
  2380. compatible = "ti,palmas-rtc";
  2381. interrupt-parent = <&tps659038>;
  2382. interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
  2383. wakeup-source;
  2384. };
  2385.  
  2386. tps659038_pwr_button: tps659038_pwr_button {
  2387. compatible = "ti,palmas-pwrbutton";
  2388. interrupt-parent = <&tps659038>;
  2389. interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
  2390. wakeup-source;
  2391. ti,palmas-long-press-seconds = <12>;
  2392. };
  2393.  
  2394. tps659038_gpio: tps659038_gpio {
  2395. compatible = "ti,palmas-gpio";
  2396. gpio-controller;
  2397. #gpio-cells = <2>;
  2398. };
  2399. };
  2400.  
  2401. /* STMPE811 touch screen controller */
  2402. stmpe811@41 {
  2403. compatible = "st,stmpe811";
  2404. reg = <0x41>;
  2405. interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
  2406. interrupt-parent = <&gpio2>;
  2407. interrupt-controller;
  2408. id = <0>;
  2409. blocks = <0x5>;
  2410. irq-trigger = <0x1>;
  2411. st,mod-12b = <1>; /* 12-bit ADC */
  2412. st,ref-sel = <0>; /* internal ADC reference */
  2413. st,adc-freq = <1>; /* 3.25 MHz ADC clock speed */
  2414. st,sample-time = <4>; /* ADC converstion time: 80 clocks */
  2415.  
  2416. pinctrl-names = "default";
  2417. pinctrl-0 = <&adc_pins_default>;
  2418.  
  2419. stmpe_adc {
  2420. compatible = "st,stmpe-adc";
  2421. st,norequest-mask = <0x00>; /* mask any channels to be used by touchscreen */
  2422. adc0: iio-device@0 {
  2423. #io-channel-cells = <1>;
  2424. iio-channels = <&adc0 4>, <&adc0 1>, <&adc0 2>, <&adc0 3>, <&adc0 4>, <&adc0 5>, <&adc0 6>;
  2425. iio-channel-names = "AIN0_P9_39", "AIN1_P9_40", "AIN2_P9_37", "AIN3_P9_38",
  2426. "AIN4_P9_33", "AIN5_P9_36", "AIN6_P9_35";
  2427. };
  2428. };
  2429.  
  2430. stmpe_touchscreen {
  2431. status = "disabled";
  2432. compatible = "st,stmpe-ts";
  2433. /* 8 sample average control */
  2434. st,ave-ctrl = <3>;
  2435. /* 7 length fractional part in z */
  2436. st,fraction-z = <7>;
  2437. /*
  2438. * 50 mA typical 80 mA max touchscreen drivers
  2439. * current limit value
  2440. */
  2441. st,i-drive = <1>;
  2442. /* 1 ms panel driver settling time */
  2443. st,settling = <3>;
  2444. /* 5 ms touch detect interrupt delay */
  2445. st,touch-det-delay = <5>;
  2446. };
  2447.  
  2448. stmpe_gpio {
  2449. compatible = "st,stmpe-gpio";
  2450. };
  2451.  
  2452. stmpe_pwm {
  2453. compatible = "st,stmpe-pwm";
  2454. #pwm-cells = <2>;
  2455. };
  2456. };
  2457. };
  2458.  
  2459. &mcspi3 {
  2460. status = "okay";
  2461. ti,pindir-d0-out-d1-in;
  2462.  
  2463. sn65hvs882: sn65hvs882@0 {
  2464. compatible = "pisosr-gpio";
  2465. gpio-controller;
  2466. #gpio-cells = <2>;
  2467.  
  2468. reg = <0>;
  2469. spi-max-frequency = <1000000>;
  2470. spi-cpol;
  2471. };
  2472. };
  2473.  
  2474. &cpu0 {
  2475. vdd-supply = <&vdd_mpu>;
  2476. voltage-tolerance = <1>;
  2477. };
  2478.  
  2479. &gpu {
  2480. status = "okay";
  2481. };
  2482.  
  2483. &pruss_soc_bus1 {
  2484. status = "okay";
  2485.  
  2486. pruss1: pruss@4b200000 {
  2487. status = "okay";
  2488. };
  2489. };
  2490.  
  2491. &pruss_soc_bus2 {
  2492. status = "okay";
  2493.  
  2494. pruss2: pruss@4b280000 {
  2495. status = "okay";
  2496. };
  2497. };
  2498.  
  2499. &uart1 {
  2500. status = "okay";
  2501. };
  2502.  
  2503. &davinci_mdio {
  2504. reset-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
  2505. reset-delay-us = <2>;
  2506.  
  2507. phy0: ethernet-phy@1 {
  2508. reg = <4>;
  2509. compatible = "ethernet-phy-id004d.d072",
  2510. "ethernet-phy-ieee802.3-c22";
  2511. eee-broken-100tx;
  2512. eee-broken-1000t;
  2513. };
  2514. };
  2515.  
  2516. &mac {
  2517. slaves = <1>;
  2518. status = "okay";
  2519. };
  2520.  
  2521. &cpsw_emac0 {
  2522. phy-handle = <&phy0>;
  2523. phy-mode = "rgmii";
  2524. };
  2525.  
  2526. &ipu2 {
  2527. status = "okay";
  2528. memory-region = <&ipu2_memory_region>;
  2529. };
  2530.  
  2531. &ipu1 {
  2532. status = "okay";
  2533. memory-region = <&ipu1_memory_region>;
  2534. };
  2535.  
  2536. &dsp1 {
  2537. status = "okay";
  2538. memory-region = <&dsp1_memory_region>;
  2539. };
  2540.  
  2541. &dsp2 {
  2542. status = "okay";
  2543. memory-region = <&dsp2_memory_region>;
  2544. };
  2545.  
  2546. &mmc1 {
  2547. status = "okay";
  2548. vmmc-supply = <&vdd_3v3>;
  2549. vqmmc-supply = <&vdd_sd>;
  2550. bus-width = <4>;
  2551. cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
  2552.  
  2553. ti,needs-special-reset;
  2554. ti,dual-volt;
  2555. sd-uhs-sdr12;
  2556. sd-uhs-sdr25;
  2557. sd-uhs-sdr50;
  2558. sd-uhs-ddr50;
  2559. sd-uhs-sdr104;
  2560. mmc-hs200-1_8v;
  2561. cap-sd-highspeed;
  2562. cap-mmc-highspeed;
  2563. dmas = <&sdma_xbar 61>, <&sdma_xbar 62>;
  2564. dma-names = "tx", "rx";
  2565.  
  2566. pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
  2567. pinctrl-0 = <&mmc1_pins_default &microsd_extra_pins_default>;
  2568. pinctrl-1 = <&mmc1_pins_hs &microsd_extra_pins_default>;
  2569. pinctrl-2 = <&mmc1_pins_sdr12 &microsd_extra_pins_default>;
  2570. pinctrl-3 = <&mmc1_pins_sdr25 &microsd_extra_pins_default>;
  2571. pinctrl-4 = <&mmc1_pins_sdr50 &microsd_extra_pins_default>;
  2572. pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf &microsd_extra_pins_default>;
  2573. pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf &microsd_extra_pins_default>;
  2574. };
  2575.  
  2576. &mmc2 {
  2577. status = "okay";
  2578. vmmc-supply = <&vdd_1v8>;
  2579. vqmmc-supply = <&vdd_1v8>;
  2580. bus-width = <8>;
  2581. ti,non-removable;
  2582. non-removable;
  2583. mmc-pwrseq = <&emmc_pwrseq>;
  2584.  
  2585. ti,needs-special-reset;
  2586. dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
  2587. dma-names = "tx", "rx";
  2588. pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
  2589. pinctrl-0 = <&mmc2_pins_default>;
  2590. pinctrl-1 = <&mmc2_pins_hs>;
  2591. pinctrl-2 = <&mmc2_pins_ddr_rev20>;
  2592. pinctrl-3 = <&mmc2_pins_hs200>;
  2593. };
  2594.  
  2595. &mmc4 {
  2596. /* DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3 V signaling). */
  2597. /* HS: High speed up to 50 MHz (3.3 V signaling). */
  2598. /* SDR12: SDR up to 25 MHz (1.8 V signaling). */
  2599. /* SDR25: SDR up to 50 MHz (1.8 V signaling). */
  2600. /* SDR50: SDR up to 100 MHz (1.8 V signaling). */
  2601. /* SDR104: SDR up to 208 MHz (1.8 V signaling) */
  2602. /* DDR50: DDR up to 50 MHz (1.8 V signaling). */
  2603. status = "okay";
  2604.  
  2605. pinctrl-names = "default", "hs";
  2606. pinctrl-0 = <&mmc4_pins_default &wifibt_extra_pins_default>;
  2607. pinctrl-1 = <&mmc4_pins_hs &wifibt_extra_pins_default>;
  2608.  
  2609. ti,needs-special-reset;
  2610. vmmc-supply = <&vdd_3v3>;
  2611. cap-power-off-card;
  2612. keep-power-in-suspend;
  2613. bus-width = <4>;
  2614. ti,non-removable;
  2615. non-removable;
  2616. no-1-8-v;
  2617. max-frequency = <24000000>;
  2618.  
  2619. #address-cells = <1>;
  2620. #size-cells = <0>;
  2621. mmc-pwrseq = <&brcmf_pwrseq>;
  2622.  
  2623. brcmf: wifi@1 {
  2624. status = "okay";
  2625. reg = <1>;
  2626. compatible = "brcm,bcm4329-fmac";
  2627.  
  2628. //brcm,drive-strength = <10>;
  2629. //brcm,broken-sg-support;
  2630. //brcm,broken_sg_support;
  2631. brcm,sd-head-align = <4>;
  2632. brcm,sd_head_align = <4>;
  2633. brcm,sd_sgentry_align = <512>;
  2634.  
  2635. interrupt-parent = <&gpio3>;
  2636. interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
  2637. interrupt-names = "host-wake";
  2638. };
  2639. };
  2640.  
  2641. &usb2_phy1 {
  2642. phy-supply = <&ldousb_reg>;
  2643. };
  2644.  
  2645. &usb2_phy2 {
  2646. phy-supply = <&ldousb_reg>;
  2647. };
  2648.  
  2649. &usb1 {
  2650. status = "okay";
  2651. dr_mode = "otg";
  2652. };
  2653.  
  2654. &omap_dwc3_1 {
  2655. extcon = <&extcon_usb1>;
  2656. };
  2657.  
  2658. &usb2 {
  2659. status = "okay";
  2660. dr_mode = "host";
  2661. };
  2662.  
  2663. &bb2d {
  2664. status = "okay";
  2665. };
  2666.  
  2667. &dss {
  2668. status = "okay";
  2669. vdda_video-supply = <&vdd_1v8_pll>;
  2670. };
  2671.  
  2672. &hdmi {
  2673. status = "okay";
  2674. vdda-supply = <&vdd_1v8_phy_ldo4>;
  2675. pinctrl-names = "default";
  2676. pinctrl-0 = <&hdmi_pins_default>;
  2677.  
  2678. port {
  2679. hdmi_out: endpoint {
  2680. remote-endpoint = <&hdmi_encoder_in>;
  2681. };
  2682. };
  2683. };
  2684.  
  2685. &bandgap {
  2686. status = "okay";
  2687. };
  2688.  
  2689. &mailbox1 {
  2690. status = "okay";
  2691. };
  2692.  
  2693. &mailbox2 {
  2694. status = "okay";
  2695. };
  2696.  
  2697. &mailbox3 {
  2698. status = "okay";
  2699. };
  2700.  
  2701. &mailbox4 {
  2702. status = "okay";
  2703. };
  2704.  
  2705. &mailbox5 {
  2706. status = "okay";
  2707. };
  2708.  
  2709. &mailbox6 {
  2710. status = "okay";
  2711. };
  2712.  
  2713. &mailbox7 {
  2714. status = "okay";
  2715. };
  2716.  
  2717. &mailbox8 {
  2718. status = "okay";
  2719. };
  2720.  
  2721. &mailbox9 {
  2722. status = "okay";
  2723. };
  2724.  
  2725. &mailbox10 {
  2726. status = "okay";
  2727. };
  2728.  
  2729. &mailbox11 {
  2730. status = "okay";
  2731. };
  2732.  
  2733. &mailbox12 {
  2734. status = "okay";
  2735. };
  2736.  
  2737. &mailbox13 {
  2738. status = "okay";
  2739. };
  2740.  
  2741. &cpu_alert0 {
  2742. temperature = <55000>; /* milliCelsius */
  2743. };
  2744.  
  2745. &cpu_crit {
  2746. temperature = <85000>; /* milliCelsius */
  2747. };
  2748.  
  2749. &gpu_crit {
  2750. temperature = <85000>; /* milliCelsius */
  2751. };
  2752.  
  2753. &core_crit {
  2754. temperature = <85000>; /* milliCelsius */
  2755. };
  2756.  
  2757. &dspeve_crit {
  2758. temperature = <85000>; /* milliCelsius */
  2759. };
  2760.  
  2761. &iva_crit {
  2762. temperature = <85000>; /* milliCelsius */
  2763. };
  2764.  
  2765. &sata {
  2766. status = "disabled";
  2767. };
  2768.  
  2769. &sata_phy {
  2770. status = "disabled";
  2771. };
  2772.  
  2773. /* bluetooth */
  2774. &uart6 {
  2775. status = "okay";
  2776. };
  2777.  
  2778. /* cape header stuff */
  2779. &i2c4 {
  2780. status = "okay";
  2781. clock-frequency = <100000>;
  2782. symlink = "bone-i2c2";
  2783. };
  2784.  
  2785. /* thermal hacks */
  2786. &cpu0_opp_table {
  2787. opp_slow-400000000 {
  2788. opp-hz = /bits/ 64 <400000000>;
  2789. opp-microvolt = <860000 850000 1100000>,
  2790. <860000 850000 1100000>;
  2791. opp-supported-hw = <0xFF 0x01>;
  2792. opp-suspend;
  2793. };
  2794. };
  2795.  
  2796. #include "dra7-ipu-common-early-boot.dtsi"
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