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  1. ;******************************************************************************
  2. ;                                                                             *
  3. ;    Author              :  Nicholas Hooper                                   *
  4. ;    Assignment          :  Final                                             *
  5. ;    Filename            :  pwm_music.s                                       *
  6. ;    Date                :  04/27/2019                                        *
  7. ;    File Version        :  2.0                                               *
  8. ;                                                                             *
  9. ;    Other Files Required: p30F6010.gld, p30f6010.inc                         *
  10. ;    Tools Used:MPLAB GL : 7.01                                               *
  11. ;               Compiler : 1.30                                               *
  12. ;               Assembler: 1.30                                               *
  13. ;               Linker   : 1.30                                               *
  14. ;                                                                             *                                                                         *
  15. ;******************************************************************************
  16.  
  17.  
  18.         .equ __24FJ64GB002, 1
  19.        .include "p24FJ64GB002.inc"
  20.  
  21.  
  22. ;..............................................................................
  23. ;Configuration bits:
  24. ;..............................................................................
  25.  
  26. config __CONFIG4,(DSWDTPS_DSWDTPS3 & I2C1SEL_PRI & DSWDTOSC_LPRC & RTCOSC_SOSC & DSBOREN_OFF & DSWDTEN_OFF)    ; DSWDT Postscale Select->1:2,147,483,648 (25.7 days);
  27.  
  28. config __CONFIG3,(WPFP_WPFP0 &  WUTSEL_LEG & WPDIS_WPDIS & WPCFG_WPCFGDIS & WPEND_WPENDMEM & SOSCSEL_IO)  ; enable RA4 and RB4  (#define SOSCSEL_EC 0xFCFF)
  29.  
  30. config __CONFIG2,(POSCMOD_NONE & I2C1SEL_PRI & IOL1WAY_OFF & OSCIOFNC_ON  & FCKSM_CSECMD & FNOSC_FRCPLL & PLL96MHZ_ON & PLLDIV_NODIV & IESO_OFF)   ;   was FCKSM_CSDCMD now FCKSM_CSECMD  was OSCIOFNC_OFF was FNOSC_FRC and PLL96MHZ_OFF LDC 8/29/18, 9/18/18
  31.                                                            
  32. config __CONFIG1,(WDTPS_PS1 & FWPSA_PR128 & WINDIS_OFF & FWDTEN_OFF & ICS_PGx1 & GWRP_OFF & GCP_OFF & JTAGEN_OFF)   ;Code Protect Off, Program pin 4,5
  33.  
  34.    
  35.                        
  36.  
  37. ;..............................................................................
  38. ;Program Specific Constants (literals used in code)
  39. ;..............................................................................
  40.  
  41.         .equ SAMPLES, 64         ;Number of samples
  42.  
  43.  
  44.  
  45. ;..............................................................................
  46. ;Global Declarations:
  47. ;..............................................................................
  48.  
  49.         .global _wreg_init       ;Provide global scope to _wreg_init routine
  50.                                 ;In order to call this routine from a C file,
  51.                                 ;place "wreg_init" in an "extern" declaration
  52.                                 ;in the C file.
  53.  
  54.         .global __reset          ;The label for the first line of code.
  55.  
  56.         .global __T1Interrupt    ;Declare Timer 1 ISR name global
  57.  
  58.  
  59.  
  60. ;..............................................................................
  61. ;Constants stored in Program space
  62. ;..............................................................................
  63.  
  64.         .section .myconstbuffer, code
  65.        .palign 2                ;Align next word stored in Program space to an
  66.                                 ;address that is a multiple of 2
  67. ps_coeff:
  68.        .hword   0x0002, 0x0003, 0x0005, 0x000A
  69.  
  70.  
  71. ;..............................................................................
  72. ;Uninitialized variables in Near data memory (Lower 8Kb of RAM)
  73. ;..............................................................................
  74.  
  75.           .section .nbss, bss, near
  76. var1:     .space 2
  77. count:    .space 2
  78. counter:  .space 2
  79. setinal:  .space 2
  80. TABaddr:  .space 2
  81. temp:     .space 2
  82. portb:    .space 2
  83.  
  84. ;..............................................................................
  85. ;Code Section in Program Memory
  86. ;..............................................................................
  87.  
  88. .text                         ;Start of Code section
  89.  
  90. Tune:   .word 0X8DE0,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X8DE0,0X0,0X8DE0,0X0,0X8DE0,0X0,0X1,0X0,0X8DE0,0X0,0X8DE0,0X0,0X1,0X0,0X1,0X0,0X9F60,0X0,0X8DE0,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X8DE0,0X0,0X8DE0,0X0,0X8DE0,0X0,0X1,0X0,0X8DE0,0X0,0X8DE0,0X0,0X1,0X0,0X1,0X0,0X9F60,0X0,0X8DE0,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X8DE0,0X0,0X8DE0,0X0,0X8DE0,0X0,0X1,0X0,0X8DE0,0X0,0X8DE0,0X0,0X1,0X0,0XBD50,0X0,0XBD50,0X0,0XBD50,0X0,0X1,0X0,0XBD50,0X0,0XBD50,0X0,0XBD50,0X0,0X1,0X0,0XBD50,0X0,0XBD50,0X0,0XBD50,0X0,0X1,0X0,0XBD50,0X0,0X1,0X0,0X8DE0,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0XBD50,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X8DE0,0X0,0X1,0X0,0X8DE0,0X0,0X7E60,0X0,0X7740,0X0,0X6A40,0X0,0X5EB0,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X5EB0,0X0,0X1,0X0,0X5EB0,0X0,0X5960,0X0,0X1,0X0,0X4F90,0X0,0X46F0,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X46F0,0X0,0X1,0X0,0X46F0,0X0,0X4F90,0X0,0X1,0X0,0X5960,0X0,0X4F90,0X0,0X1,0X0,0X1,0X0,0X5960,0X0,0X5EB0,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X5EB0,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X6A40,0X0,0X1,0X0,0X6A40,0X0,0X5EB0,0X0,0X5960,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X5EB0,0X0,0X1,0X0,0X6A40,0X0,0X1,0X0,0X7740,0X0,0X1,0X0,0X7740,0X0,0X6A40,0X0,0X5EB0,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X6A40,0X0,0X1,0X0,0X7740,0X0,0X1,0X0,0X7E60,0X0,0X1,0X0,0X7E60,0X0,0X7740,0X0,0X6A40,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X5960,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X5EB0,0X0,0X1,0X0,0XBD50,0X0,0XBD50,0X0,0XBD50,0X0,0X1,0X0,0XBD50,0X0,0XBD50,0X0,0XBD50,0X0,0X1,0X0,0XBD50,0X0,0XBD50,0X0,0XBD50,0X0,0X1,0X0,0XBD50,0X0,0X1,0X0,0X8DE0,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0XBD50,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X8DE0,0X0,0X1,0X0,0X8DE0,0X0,0X7E60,0X0,0X7740,0X0,0X6A40,0X0,0X5EB0,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X5EB0,0X0,0X1,0X0,0X5EB0,0X0,0X5960,0X0,0X1,0X0,0X4F90,0X0,0X46F0,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X3BA0,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X3F30,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X4F90,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X5EB0,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X5960,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X46F0,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X4F90,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X5EB0,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X5EB0,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X5960,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X46F0,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X4B20,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X5EB0,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X7090,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X6A40,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X5960,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X5EB0,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X7740,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X8DE0,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X7E60,0X0,0X1,0X0,0X7E60,0X0,0X7740,0X0,0X6A40,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X5960,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X5EB0,0X0,0X1,0X0,0XBD50,0X0,0XBD50,0X0,0XBD50,0X0,0X1,0X0,0XBD50,0X0,0XBD50,0X0,0XBD50,0X0,0X1,0X0,0XBD50,0X0,0XBD50,0X0,0XBD50,0X0,0X1,0X0,0XBD50,0X0,0X1,0X0,0X8DE0,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0XBD50,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X8DE0,0X0,0X1,0X0,0X8DE0,0X0,0X7E60,0X0,0X7740,0X0,0X6A40,0X0,0X5EB0,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X5EB0,0X0,0X1,0X0,0X5EB0,0X0,0X5960,0X0,0X1,0X0,0X4F90,0X0,0X46F0,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X46F0,0X0,0X1,0X0,0X46F0,0X0,0X4F90,0X0,0X1,0X0,0X5960,0X0,0X4F90,0X0,0X1,0X0,0X1,0X0,0X5960,0X0,0X5EB0,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X5EB0,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X6A40,0X0,0X1,0X0,0X6A40,0X0,0X5EB0,0X0,0X5960,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X5EB0,0X0,0X1,0X0,0X6A40,0X0,0X1,0X0,0X7740,0X0,0X1,0X0,0X7740,0X0,0X6A40,0X0,0X5EB0,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X6A40,0X0,0X1,0X0,0X7740,0X0,0X1,0X0,0X7E60,0X0,0X1,0X0,0X7E60,0X0,0X7740,0X0,0X6A40,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X5960,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X5EB0,0X0,0X1,0X0,0XBD50,0X0,0XBD50,0X0,0XBD50,0X0,0X1,0X0,0XBD50,0X0,0XBD50,0X0,0XBD50,0X0,0X1,0X0,0XBD50,0X0,0XBD50,0X0,0XBD50,0X0,0X1,0X0,0XBD50,0X0,0X1,0X0,0X8DE0,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0XBD50,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X8DE0,0X0,0X1,0X0,0X8DE0,0X0,0X7E60,0X0,0X7740,0X0,0X6A40,0X0,0X5EB0,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X1,0X0,0X5EB0,0X0,0X1,0X0,0X5EB0,0X0,0X5960,0X0,0X1,0X0,0X4F90,0X0,0X46F0,0X0,0X1,0X0,
  91.  
  92.  
  93. __reset:
  94.         MOV #__SP_init, W15       ;Initalize the Stack Pointer
  95.         MOV #__SPLIM_init, W0     ;Initialize the Stack Pointer Limit Register
  96.         MOV W0, SPLIM
  97.         NOP                       ;Add NOP to follow SPLIM initialization
  98.        
  99.         CALL _wreg_init           ;Call _wreg_init subroutine
  100.                                  ;Optionally use RCALL instead of CALL
  101.  
  102.  
  103.  
  104. /*
  105. To configure the output compare module for PWM operation:
  106. 1. Configure the OCx output for one of the available Peripheral Pin Select pins.
  107. 2. Calculate the desired duty cycles and load them into the OCxR register.
  108. 3. Calculate the desired period and load it into the OCxRS register.
  109. 4. Select the current OCx as the sync source by writing 0x1F to SYNCSEL<4:0>
  110. (OCxCON2<4:0>), and clearing OCTRIG (OCxCON2<7>).
  111. 5. Select a clock source by writing the OCTSEL<2:0> (OCxCON<12:10>) bits.
  112. 6. Enable interrupts, if required, for the timer and output compare modules. The
  113. output compare interrupt is required for PWM Fault pin utilization.
  114. 7. Select the desired PWM mode in the OCM<2:0> (OCxCON1<2:0>) bits.
  115. 8. If a timer is selected as a clock source, set the TMRy prescale value and enable
  116. the time base by setting the TON (TxCON<15>) bit.
  117. */
  118.        ;<<insert more user code here>>
  119.      
  120. ;House keeping
  121.         clr  TRISB
  122.        
  123.  
  124.  
  125. ; setup pwm
  126.         BCLR    OSCCONL,#6
  127.         MOV     #0x0012,w1
  128.         MOV     w1,RPOR5
  129.         BSET    OSCCONL,#6
  130.  
  131.  
  132.         clr  T2CON
  133.         bset T2CON,#TON   ; Turn on timer 2
  134.         mov  #0x0060,w0   ; stuff with a hex 60
  135.         mov  w0,OC1R
  136.      
  137.         mov #0x0006,w0
  138.         mov w0,OC1CON1      ; edge-aligned pwm mode on ocx
  139.         mov #0xFFFF,w0
  140.         mov w0,PR2          ; stuff period register with a hex 7F
  141.  
  142.         mov  #0x8020,W0     ; turn on timer 1 and loaded prescalar with 256
  143.         mov  w0,T1CON
  144.         mov  #16000,w0      ; 5ms between pwm    
  145.         mov  w0,PR1
  146.         bset IEC0,#T1IE
  147.      
  148.         bclr  setinal,#0
  149.        
  150.         mov #tblpage(Tune),w0
  151.         mov  w0,_TBLPAG
  152.         clr  counter
  153.         clr  count
  154.        
  155. start: 
  156.         btss setinal,#0
  157.         goto start 
  158.  
  159.         mov #tbloffset(Tune),w0
  160.         add TABaddr,wreg   
  161.         TBLRDL [w0++],w0
  162.        
  163.         mov   #0xFFFF,w1  ; mask off bit 15
  164.         and   w0,w1,w0
  165.         mov  w0,temp
  166.         mov  w0,PR2
  167.         lsr  temp
  168.         mov  temp,w0
  169.         mov  w0,OC1R  
  170.        
  171.        
  172.         bclr  setinal,#0
  173.         mov  #2,w0
  174.         add  TABaddr
  175.         inc   counter
  176.         mov   counter,w3
  177.         sub   #1023,w3;1092
  178.         BRA   Z,skip2
  179.         goto start
  180. skip2:    
  181.         clr   counter  
  182.         clr   TABaddr    
  183.        
  184. goto start
  185.  
  186.  
  187.  
  188. ;..............................................................................
  189. ;Subroutine: Initialization of W registers to 0x0000
  190. ;..............................................................................
  191.  
  192. _wreg_init:
  193.         CLR W0
  194.         MOV W0, W14
  195.         REPEAT #12
  196.         MOV W0, [++W14]
  197.         CLR W14
  198.         RETURN
  199.  
  200. ;..............................................................................
  201. ;Timer 1 Interrupt Service Routine
  202. ;Example context save/restore in the ISR performed using PUSH.D/POP.D
  203. ;instruction. The instruction pushes two words W4 and W5 on to the stack on
  204. ;entry into ISR and pops the two words back into W4 and W5 on exit from the ISR
  205. ;..............................................................................
  206.  
  207. __T1Interrupt:
  208.         PUSH  w0                 ;Save context using double-word PUSH
  209.              
  210.         nop ; used for debugging with the simulator
  211.        INC   count
  212.         mov   count,w3
  213.         sub   #1,w3
  214.         BRA   NZ,isr_skip
  215.        
  216.         clr   count
  217.         bset setinal,#0
  218. isr_skip:
  219.         BCLR IFS0, #T1IF           ;Clear the Timer1 Interrupt flag Status
  220.         POP  w0                ;Retrieve context POP-ping from Stack
  221.         RETFIE                     ;Return from Interrupt Service routine
  222.  
  223.  
  224.  
  225. ;--------End of All Code Sections ---------------------------------------------
  226.  
  227. .end                               ;End of program code in this file
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