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evage

All states

Dec 2nd, 2022
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  1. module testbench();
  2. initial begin
  3.         $dumpfile("dump.vcd");
  4.         $dumpvars;
  5.     end
  6.     reg clk;
  7.     reg [1:0] res[0:13];
  8.     reg [3:0] state;
  9.     reg[15:0] out;
  10.     reg m, n;
  11.     integer args;
  12.     initial begin
  13.         res[0] <= 0; res[1] <= 0;
  14.         res[2] <= 1; res[3] <= 2;
  15.         res[4] <= 0; res[5] <= 0;
  16.         res[6] <= 2; res[7] <= 2;
  17.         res[8] <= 2; res[9] <= 2;
  18.         res[10] <= 0; res[11] <= 0;
  19.         res[12] <= 2; res[13] <= 2;
  20.         n <= 0; m <= 0;
  21.         out <= 0; state <= 0;
  22.         clk <= 0; args <= 0;
  23.     end
  24.     always #10 clk = ~clk;
  25.     always @(posedge clk) begin
  26.         n = res[args][0];
  27.         m = res[args][1];                
  28.         args = args + 1;
  29.         if (args > 13)
  30.             $finish;
  31.     end
  32.  
  33.     fsm _fsm(.n(n), .m(m), .clk(clk), .state(state), .out(out));
  34.  
  35. endmodule
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