All states

module testbench();
initial begin
        $dumpfile("dump.vcd");
        $dumpvars;
    end
    reg clk;
    reg [1:0] res[0:13];
    reg [3:0] state;
    reg[15:0] out;
    reg m, n;
    integer args;
    initial begin
        res[0] <= 0; res[1] <= 0;
        res[2] <= 1; res[3] <= 2;
        res[4] <= 0; res[5] <= 0;
        res[6] <= 2; res[7] <= 2;
        res[8] <= 2; res[9] <= 2;
        res[10] <= 0; res[11] <= 0;
        res[12] <= 2; res[13] <= 2;
        n <= 0; m <= 0;
        out <= 0; state <= 0;
        clk <= 0; args <= 0;
    end
    always #10 clk = ~clk;
    always @(posedge clk) begin
        n = res[args][0];
        m = res[args][1];
        args = args + 1;
        if (args > 13)
            $finish;
    end

    fsm _fsm(.n(n), .m(m), .clk(clk), .state(state), .out(out));

endmodule