Misc: BCD Add/Subtract (64b / 16-digit)

----

module ExBcdAdd4(a, b, c, c_in, c_out);
input [3:0]     a;
input [3:0]     b;
output[3:0]     c;
input           c_in;
output          c_out;

reg[4:0]    tCa;
reg[4:0]    tCb;

reg[3:0]    tC;
reg         tCo;
assign      c = tC;
assign      c_out = tCo;

always @*
begin
    tCa = { 1'b0, a } + { 1'b0, b } + { 4'b0, c_in };

    case(tCa)
        5'h00: tCb = 5'h00;
        5'h01: tCb = 5'h01;
        5'h02: tCb = 5'h02;
        5'h03: tCb = 5'h03;
        5'h04: tCb = 5'h04;
        5'h05: tCb = 5'h05;
        5'h06: tCb = 5'h06;
        5'h07: tCb = 5'h07;
        5'h08: tCb = 5'h08;
        5'h09: tCb = 5'h09;
        5'h0A: tCb = 5'h10;
        5'h0B: tCb = 5'h11;
        5'h0C: tCb = 5'h12;
        5'h0D: tCb = 5'h13;
        5'h0E: tCb = 5'h14;
        5'h0F: tCb = 5'h15;
        5'h10: tCb = 5'h16;
        5'h11: tCb = 5'h17;
        5'h12: tCb = 5'h18;
        5'h13: tCb = 5'h19;

        default:
        begin
            /* Out of range, but can't occur with in-range inputs. */
            tCb = 5'h00;
        end
    endcase

//  tCb = tCa + ((tCa>9)?6:0);
    tC  = tCb[3:0];
    tCo = tCb[4];
end

endmodule

---

`include "ExBcdAdd4.v"

module ExBcdAdd64(a, b, c, c_in, c_out, mode);
input [63:0]        a;
input [63:0]        b;
output[63:0]        c;
input           c_in;
output          c_out;
input           mode;

wire[63:0]  tBinv;
wire[63:0]  tBi;
wire        tCi;

assign tBinv =
{   4'h9-b[63:60], 4'h9-b[59:56],
    4'h9-b[55:52], 4'h9-b[51:48],
    4'h9-b[47:44], 4'h9-b[43:40],
    4'h9-b[39:36], 4'h9-b[35:32],
    4'h9-b[31:28], 4'h9-b[27:24],
    4'h9-b[23:20], 4'h9-b[19:16],
    4'h9-b[15:12], 4'h9-b[11: 8],
    4'h9-b[ 7: 4], 4'h9-b[ 3: 0]    };

assign  tBi = mode ? tBinv : b;
assign  tCi = mode ? !c_in : c_in;

wire[63:0]  tCa;
wire[63:0]  tCa0;
wire[63:0]  tCa1;

wire    tCarry01a;
wire    tCarry02a;
wire    tCarry03a;
wire    tCarry04a;
wire    tCarry05a;
wire    tCarry06a;
wire    tCarry07a;
wire    tCarry08a;
wire    tCarry09a;
wire    tCarry10a;
wire    tCarry11a;
wire    tCarry12a;
wire    tCarry13a;
wire    tCarry14a;
wire    tCarry15a;
wire    tCarry16a;

wire    tCarry01b;
wire    tCarry02b;
wire    tCarry03b;
wire    tCarry04b;
wire    tCarry05b;
wire    tCarry06b;
wire    tCarry07b;
wire    tCarry08b;
wire    tCarry09b;
wire    tCarry10b;
wire    tCarry11b;
wire    tCarry12b;
wire    tCarry13b;
wire    tCarry14b;
wire    tCarry15b;
wire    tCarry16b;

ExBcdAdd4   add01a(a[ 3: 0], tBi[ 3: 0], tCa0[ 3: 0], 1'b0     , tCarry01a);
ExBcdAdd4   add02a(a[ 7: 4], tBi[ 7: 4], tCa0[ 7: 4], tCarry01a, tCarry02a);
ExBcdAdd4   add01b(a[ 3: 0], tBi[ 3: 0], tCa1[ 3: 0], 1'b1     , tCarry01b);
ExBcdAdd4   add02b(a[ 7: 4], tBi[ 7: 4], tCa1[ 7: 4], tCarry01b, tCarry02b);

ExBcdAdd4   add03a(a[11: 8], tBi[11: 8], tCa0[11: 8], 1'b0     , tCarry03a);
ExBcdAdd4   add04a(a[15:12], tBi[15:12], tCa0[15:12], tCarry03a, tCarry04a);
ExBcdAdd4   add03b(a[11: 8], tBi[11: 8], tCa1[11: 8], 1'b1     , tCarry03b);
ExBcdAdd4   add04b(a[15:12], tBi[15:12], tCa1[15:12], tCarry03b, tCarry04b);

ExBcdAdd4   add05a(a[19:16], tBi[19:16], tCa0[19:16], 1'b0     , tCarry05a);
ExBcdAdd4   add06a(a[23:20], tBi[23:20], tCa0[23:20], tCarry05a, tCarry06a);
ExBcdAdd4   add05b(a[19:16], tBi[19:16], tCa1[19:16], 1'b1     , tCarry05b);
ExBcdAdd4   add06b(a[23:20], tBi[23:20], tCa1[23:20], tCarry05b, tCarry06b);

ExBcdAdd4   add07a(a[27:24], tBi[27:24], tCa0[27:24], 1'b0     , tCarry07a);
ExBcdAdd4   add08a(a[31:28], tBi[31:28], tCa0[31:28], tCarry07a, tCarry08a);
ExBcdAdd4   add07b(a[27:24], tBi[27:24], tCa1[27:24], 1'b1     , tCarry07b);
ExBcdAdd4   add08b(a[31:28], tBi[31:28], tCa1[31:28], tCarry07b, tCarry08b);

ExBcdAdd4   add09a(a[35:32], tBi[35:32], tCa0[35:32], 1'b0     , tCarry09a);
ExBcdAdd4   add10a(a[39:36], tBi[39:36], tCa0[39:36], tCarry09a, tCarry10a);
ExBcdAdd4   add09b(a[35:32], tBi[35:32], tCa1[35:32], 1'b1     , tCarry09b);
ExBcdAdd4   add10b(a[39:36], tBi[39:36], tCa1[39:36], tCarry09b, tCarry10b);

ExBcdAdd4   add11a(a[43:40], tBi[43:40], tCa0[43:40], 1'b0     , tCarry11a);
ExBcdAdd4   add12a(a[47:44], tBi[47:44], tCa0[47:44], tCarry11a, tCarry12a);
ExBcdAdd4   add11b(a[43:40], tBi[43:40], tCa1[43:40], 1'b1     , tCarry11b);
ExBcdAdd4   add12b(a[47:44], tBi[47:44], tCa1[47:44], tCarry11b, tCarry12b);

ExBcdAdd4   add13a(a[51:48], tBi[51:48], tCa0[51:48], 1'b0     , tCarry13a);
ExBcdAdd4   add14a(a[55:52], tBi[55:52], tCa0[55:52], tCarry13a, tCarry14a);
ExBcdAdd4   add13b(a[51:48], tBi[51:48], tCa1[51:48], 1'b1     , tCarry13b);
ExBcdAdd4   add14b(a[55:52], tBi[55:52], tCa1[55:52], tCarry13b, tCarry14b);

ExBcdAdd4   add15a(a[59:56], tBi[59:56], tCa0[59:56], 1'b0     , tCarry15a);
ExBcdAdd4   add16a(a[63:60], tBi[63:60], tCa0[63:60], tCarry15a, tCarry16a);
ExBcdAdd4   add15b(a[59:56], tBi[59:56], tCa1[59:56], 1'b1     , tCarry15b);
ExBcdAdd4   add16b(a[63:60], tBi[63:60], tCa1[63:60], tCarry15b, tCarry16b);

wire tCc0_0 = 1'b0   ? tCarry02b : tCarry02a;
wire tCc0_1 = tCc0_0 ? tCarry04b : tCarry04a;
wire tCc0_2 = tCc0_1 ? tCarry06b : tCarry06a;
wire tCc0_3 = tCc0_2 ? tCarry08b : tCarry08a;
wire tCc0_4 = tCc0_3 ? tCarry10b : tCarry10a;
wire tCc0_5 = tCc0_4 ? tCarry12b : tCarry12a;
wire tCc0_6 = tCc0_5 ? tCarry14b : tCarry14a;
wire tCc0_7 = tCc0_6 ? tCarry16b : tCarry16a;

wire tCc1_0 = 1'b1   ? tCarry02b : tCarry02a;
wire tCc1_1 = tCc1_0 ? tCarry04b : tCarry04a;
wire tCc1_2 = tCc1_1 ? tCarry06b : tCarry06a;
wire tCc1_3 = tCc1_2 ? tCarry08b : tCarry08a;
wire tCc1_4 = tCc1_3 ? tCarry10b : tCarry10a;
wire tCc1_5 = tCc1_4 ? tCarry12b : tCarry12a;
wire tCc1_6 = tCc1_5 ? tCarry14b : tCarry14a;
wire tCc1_7 = tCc1_6 ? tCarry16b : tCarry16a;

wire tCc_0 = tCi ? tCc1_0 : tCc0_0;
wire tCc_1 = tCi ? tCc1_1 : tCc0_1;
wire tCc_2 = tCi ? tCc1_2 : tCc0_2;
wire tCc_3 = tCi ? tCc1_3 : tCc0_3;
wire tCc_4 = tCi ? tCc1_4 : tCc0_4;
wire tCc_5 = tCi ? tCc1_5 : tCc0_5;
wire tCc_6 = tCi ? tCc1_6 : tCc0_6;
wire tCc_7 = tCi ? tCc1_7 : tCc0_7;

assign  tCa[ 7: 0] = tCi   ? tCa1[ 7: 0] : tCa0[ 7: 0];
assign  tCa[15: 8] = tCc_0 ? tCa1[15: 8] : tCa0[15: 8];
assign  tCa[23:16] = tCc_1 ? tCa1[23:16] : tCa0[23:16];
assign  tCa[31:24] = tCc_2 ? tCa1[31:24] : tCa0[31:24];
assign  tCa[39:32] = tCc_3 ? tCa1[39:32] : tCa0[39:32];
assign  tCa[47:40] = tCc_4 ? tCa1[47:40] : tCa0[47:40];
assign  tCa[55:48] = tCc_5 ? tCa1[55:48] : tCa0[55:48];
assign  tCa[63:56] = tCc_6 ? tCa1[63:56] : tCa0[63:56];

assign      c = tCa;
assign      c_out = tCc_7;

endmodule