API tools faq
paste
Advertisement
uaa

[wip:20140713] rdcide(4) merged into pciide.c

uaa
Jul 13th, 2014
269
0
Never
Add comment
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
text 10.99 KB | None | 0 0
raw download clone embed print report
  1. Index: pciide.c
  2. ===================================================================
  3. RCS file: /cvs/src/sys/dev/pci/pciide.c,v
  4. retrieving revision 1.345
  5. diff -u -p -r1.345 pciide.c
  6. --- pciide.c 24 Apr 2014 15:38:25 -0000 1.345
  7. +++ pciide.c 12 Jul 2014 22:10:54 -0000
  8. @@ -123,6 +123,7 @@ int wdcdebug_pciide_mask = WDCDEBUG_PCII
  9. #include <dev/pci/pciide_ixp_reg.h>
  10. #include <dev/pci/pciide_svwsata_reg.h>
  11. #include <dev/pci/pciide_jmicron_reg.h>
  12. +#include <dev/pci/pciide_rdc_reg.h>
  13. #include <dev/pci/cy82c693var.h>
  14.  
  15. /* functions for reading/writing 8-bit PCI registers */
  16. @@ -282,6 +283,9 @@ void phison_setup_channel(struct channel
  17. void sch_chip_map(struct pciide_softc *, struct pci_attach_args *);
  18. void sch_setup_channel(struct channel_softc *);
  19.  
  20. +void rdc_chip_map(struct pciide_softc *, struct pci_attach_args *);
  21. +void rdc_setup_channel(struct channel_softc *);
  22. +
  23. struct pciide_product_desc {
  24. u_int32_t ide_product;
  25. u_short ide_flags;
  26. @@ -1335,6 +1339,13 @@ const struct pciide_product_desc pciide_
  27. },
  28. };
  29.  
  30. +const struct pciide_product_desc pciide_rdc_products[] = {
  31. + { PCI_PRODUCT_RDC_R1012_IDE,
  32. + 0,
  33. + rdc_chip_map
  34. + },
  35. +};
  36. +
  37. struct pciide_vendor_desc {
  38. u_int32_t ide_vendor;
  39. const struct pciide_product_desc *ide_products;
  40. @@ -1379,7 +1390,9 @@ const struct pciide_vendor_desc pciide_v
  41. { PCI_VENDOR_JMICRON, pciide_jmicron_products,
  42. nitems(pciide_jmicron_products) },
  43. { PCI_VENDOR_PHISON, pciide_phison_products,
  44. - nitems(pciide_phison_products) }
  45. + nitems(pciide_phison_products) },
  46. + { PCI_VENDOR_RDC, pciide_rdc_products,
  47. + nitems(pciide_rdc_products) }
  48. };
  49.  
  50. /* options passed via the 'flags' config keyword */
  51. @@ -1581,6 +1594,7 @@ pciide_activate(struct device *self, int
  52. sc->sc_pp->chip_map == piix_chip_map ||
  53. sc->sc_pp->chip_map == amd756_chip_map ||
  54. sc->sc_pp->chip_map == phison_chip_map ||
  55. + sc->sc_pp->chip_map == rdc_chip_map ||
  56. sc->sc_pp->chip_map == ixp_chip_map ||
  57. sc->sc_pp->chip_map == acard_chip_map ||
  58. sc->sc_pp->chip_map == apollo_chip_map ||
  59. @@ -9103,4 +9117,150 @@ pio:
  60. }
  61.  
  62. pciide_print_modes(cp);
  63. +}
  64. +
  65. +void
  66. +rdc_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
  67. +{
  68. + struct pciide_channel *cp;
  69. + int channel;
  70. + u_int32_t patr;
  71. + pcireg_t interface = PCI_INTERFACE(pa->pa_class);
  72. + bus_size_t cmdsize, ctlsize;
  73. +
  74. + pciide_mapreg_dma(sc, pa);
  75. + sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32;
  76. + if (sc->sc_dma_ok) {
  77. + sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA |
  78. + WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK;
  79. + sc->sc_wdcdev.irqack = pciide_irqack;
  80. + sc->sc_wdcdev.dma_init = pciide_dma_init;
  81. + }
  82. + sc->sc_wdcdev.PIO_cap = 4;
  83. + sc->sc_wdcdev.DMA_cap = 2;
  84. + sc->sc_wdcdev.UDMA_cap = 5;
  85. + sc->sc_wdcdev.set_modes = rdc_setup_channel;
  86. + sc->sc_wdcdev.channels = sc->wdc_chanarray;
  87. + sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
  88. +
  89. + pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
  90. +
  91. + WDCDEBUG_PRINT(("rdc_chip_map: old PATR=0x%x, "
  92. + "PSD1ATR=0x%x, UDCCR=0x%x, IIOCR=0x%x\n",
  93. + pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PATR),
  94. + pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PSD1ATR),
  95. + pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_UDCCR),
  96. + pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_IIOCR)),
  97. + DEBUG_PROBE);
  98. +
  99. + for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
  100. + cp = &sc->pciide_channels[channel];
  101. +
  102. + if (pciide_chansetup(sc, channel, interface) == 0)
  103. + continue;
  104. + patr = pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PATR);
  105. + if ((patr & RDCIDE_PATR_EN(channel)) == 0) {
  106. + printf("%s: %s ignored (disabled)\n",
  107. + sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
  108. + continue;
  109. + }
  110. + pciide_map_compat_intr(pa, cp, channel, interface);
  111. + if (cp->hw_ok == 0)
  112. + continue;
  113. + pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
  114. + pciide_pci_intr);
  115. + if (cp->hw_ok == 0)
  116. + goto next;
  117. + if (pciide_chan_candisable(cp)) {
  118. + patr &= ~RDCIDE_PATR_EN(channel);
  119. + pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_PATR,
  120. + patr);
  121. + }
  122. + if (cp->hw_ok == 0)
  123. + goto next;
  124. + sc->sc_wdcdev.set_modes(&cp->wdc_channel);
  125. +next:
  126. + if (cp->hw_ok == 0)
  127. + pciide_unmap_compat_intr(pa, cp, channel, interface);
  128. + }
  129. +
  130. + WDCDEBUG_PRINT(("rdc_chip_map: PATR=0x%x, "
  131. + "PSD1ATR=0x%x, UDCCR=0x%x, IIOCR=0x%x\n",
  132. + pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PATR),
  133. + pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PSD1ATR),
  134. + pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_UDCCR),
  135. + pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_IIOCR)),
  136. + DEBUG_PROBE);
  137. +}
  138. +
  139. +void
  140. +rdc_setup_channel(struct channel_softc *chp)
  141. +{
  142. + u_int8_t drive;
  143. + u_int32_t patr, psd1atr, udccr, iiocr;
  144. + struct pciide_channel *cp = (struct pciide_channel *)chp;
  145. + struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
  146. + struct ata_drive_datas *drvp;
  147. +
  148. + patr = pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PATR);
  149. + psd1atr = pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PSD1ATR);
  150. + udccr = pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_UDCCR);
  151. + iiocr = pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_IIOCR);
  152. +
  153. + /* setup DMA */
  154. + pciide_channel_dma_setup(cp);
  155. +
  156. + /* clear modes */
  157. + patr = patr & (RDCIDE_PATR_EN(0) | RDCIDE_PATR_EN(1));
  158. + psd1atr &= ~RDCIDE_PSD1ATR_SETUP_MASK(chp->channel);
  159. + psd1atr &= ~RDCIDE_PSD1ATR_HOLD_MASK(chp->channel);
  160. + for (drive = 0; drive < 2; drive++) {
  161. + udccr &= ~RDCIDE_UDCCR_EN(chp->channel, drive);
  162. + udccr &= ~RDCIDE_UDCCR_TIM_MASK(chp->channel, drive);
  163. + iiocr &= ~RDCIDE_IIOCR_CLK_MASK(chp->channel, drive);
  164. + }
  165. + /* now setup modes */
  166. + for (drive = 0; drive < 2; drive++) {
  167. + drvp = &cp->wdc_channel.ch_drive[drive];
  168. + if ((drvp->drive_flags & DRIVE) == 0)
  169. + continue;
  170. + if (drvp->drive_flags & DRIVE_ATAPI)
  171. + patr |= RDCIDE_PATR_ATA(chp->channel, drive);
  172. + if (drive == 0) {
  173. + patr |= RDCIDE_PATR_SETUP(rdcide_setup[drvp->PIO_mode],
  174. + chp->channel);
  175. + patr |= RDCIDE_PATR_HOLD(rdcide_hold[drvp->PIO_mode],
  176. + chp->channel);
  177. + } else {
  178. + patr |= RDCIDE_PATR_DEV1_TEN(chp->channel);
  179. + psd1atr |= RDCIDE_PSD1ATR_SETUP(
  180. + rdcide_setup[drvp->PIO_mode],
  181. + chp->channel);
  182. + psd1atr |= RDCIDE_PSD1ATR_HOLD(
  183. + rdcide_hold[drvp->PIO_mode],
  184. + chp->channel);
  185. + }
  186. + if (drvp->PIO_mode > 0) {
  187. + patr |= RDCIDE_PATR_FTIM(chp->channel, drive);
  188. + patr |= RDCIDE_PATR_IORDY(chp->channel, drive);
  189. + }
  190. + if (drvp->drive_flags & DRIVE_DMA)
  191. + patr |= RDCIDE_PATR_DMAEN(chp->channel, drive);
  192. + if ((drvp->drive_flags & DRIVE_UDMA) == 0)
  193. + continue;
  194. +
  195. + if ((iiocr & RDCIDE_IIOCR_CABLE(chp->channel, drive)) == 0
  196. + && drvp->UDMA_mode > 2)
  197. + drvp->UDMA_mode = 2;
  198. + udccr |= RDCIDE_UDCCR_EN(chp->channel, drive);
  199. + udccr |= RDCIDE_UDCCR_TIM(rdcide_udmatim[drvp->UDMA_mode],
  200. + chp->channel, drive);
  201. + iiocr |= RDCIDE_IIOCR_CLK(rdcide_udmaclk[drvp->UDMA_mode],
  202. + chp->channel, drive);
  203. + }
  204. +
  205. + pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_PATR, patr);
  206. + pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_PSD1ATR, psd1atr);
  207. + pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_UDCCR, udccr);
  208. + pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_IIOCR, iiocr);
  209. }
  210. Index: pciide_rdc_reg.h
  211. ===================================================================
  212. RCS file: pciide_rdc_reg.h
  213. diff -N pciide_rdc_reg.h
  214. --- /dev/null 1 Jan 1970 00:00:00 -0000
  215. +++ pciide_rdc_reg.h 12 Jul 2014 22:10:54 -0000
  216. @@ -0,0 +1,75 @@
  217. +/* $OpenBSD$ */
  218. +/* $NetBSD: rdcide_reg.h,v 1.1 2011/04/04 14:33:51 bouyer Exp $ */
  219. +
  220. +/*
  221. + * Copyright (c) 2011 Manuel Bouyer.
  222. + *
  223. + * Redistribution and use in source and binary forms, with or without
  224. + * modification, are permitted provided that the following conditions
  225. + * are met:
  226. + * 1. Redistributions of source code must retain the above copyright
  227. + * notice, this list of conditions and the following disclaimer.
  228. + * 2. Redistributions in binary form must reproduce the above copyright
  229. + * notice, this list of conditions and the following disclaimer in the
  230. + * documentation and/or other materials provided with the distribution.
  231. + *
  232. + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  233. + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  234. + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  235. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  236. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  237. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  238. + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  239. + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  240. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  241. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  242. + *
  243. + */
  244. +
  245. +/*
  246. + * register definitions for the RDC ide controller as found in the
  247. + * PMX-1000 SoC
  248. + */
  249. +/* ATA Timing Register */
  250. +#define RDCIDE_PATR 0x40
  251. +#define RDCIDE_PATR_EN(chan) (0x8000 << ((chan) * 16))
  252. +#define RDCIDE_PATR_DEV1_TEN(chan) (0x4000 << ((chan) * 16))
  253. +#define RDCIDE_PATR_SETUP(val, chan) (((val) << 12) << ((chan) * 16))
  254. +#define RDCIDE_PATR_SETUP_MASK(chan) (0x3000 << ((chan) * 16))
  255. +#define RDCIDE_PATR_HOLD(val, chan) (((val) << 8) << ((chan) * 16))
  256. +#define RDCIDE_PATR_HOLD_MASK(chan) (0x0300 << ((chan) * 16))
  257. +#define RDCIDE_PATR_DMAEN(chan, drv) ((0x0008 << (drv * 4)) << ((chan) * 16))
  258. +#define RDCIDE_PATR_ATA(chan, drv) ((0x0004 << (drv * 4)) << ((chan) * 16))
  259. +#define RDCIDE_PATR_IORDY(chan, drv) ((0x0002 << (drv * 4)) << ((chan) * 16))
  260. +#define RDCIDE_PATR_FTIM(chan, drv) ((0x0001 << (drv * 4)) << ((chan) * 16))
  261. +
  262. +/* Primary and Secondary Device 1 ATA Timing */
  263. +#define RDCIDE_PSD1ATR 0x44
  264. +#define RDCIDE_PSD1ATR_SETUP(val, chan) (((val) << 2) << (chan * 4))
  265. +#define RDCIDE_PSD1ATR_SETUP_MASK(chan) (0x0c << (chan * 4))
  266. +#define RDCIDE_PSD1ATR_HOLD(val, chan) (((val) << 0) << (chan * 4))
  267. +#define RDCIDE_PSD1ATR_HOLD_MASK(chan) (0x03 << (chan * 4))
  268. +
  269. +const uint8_t rdcide_setup[] = {0, 0, 1, 2, 2};
  270. +const uint8_t rdcide_hold[] = {0, 0, 0, 1, 3};
  271. +
  272. +/* Ultra DMA Control and timing Register */
  273. +#define RDCIDE_UDCCR 0x48
  274. +#define RDCIDE_UDCCR_EN(chan, drv) ((1 << (drv)) << (chan * 2))
  275. +#define RDCIDE_UDCCR_TIM(val, chan, drv) (((val) << ((drv) * 4)) << (chan * 8))
  276. +#define RDCIDE_UDCCR_TIM_MASK(chan, drv) ((0x3 << ((drv) * 4)) << (chan * 8))
  277. +
  278. +const uint8_t rdcide_udmatim[] = {0, 1, 2, 1, 2, 1};
  279. +
  280. +/* IDE I/O Configuration Registers */
  281. +#define RDCIDE_IIOCR 0x54
  282. +#define RDCIDE_IIOCR_CABLE(chan, drv) ((0x10 << (drv)) << (chan * 2))
  283. +#define RDCIDE_IIOCR_CLK(val, chan, drv) (((val) << drv) << (chan * 2))
  284. +#define RDCIDE_IIOCR_CLK_MASK(chan, drv) ((0x1001 << drv) << (chan * 2))
  285. +
  286. +const uint32_t rdcide_udmaclk[] =
  287. + {0x0000, 0x0000, 0x0000, 0x0001, 0x0001, 0x1000};
  288. +
  289. +/* Miscellaneous Control Register */
  290. +#define RDCIDE_MCR 0x90
  291. +#define RDCIDE_MCR_RESET(chan) (0x01000000 << (chan))
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement
Public Pastes
Advertisement
We use cookies for various purposes including analytics. By continuing to use Pastebin, you agree to our use of cookies as described in the Cookies Policy.  OK, I Understand
Not a member of Pastebin yet?
Sign Up, it unlocks many cool features!