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- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
- ---------------------------------------------------------------------------------------------------------
- | Tool Version : Vivado v.2017.3.1 (win64) Build 2035080 Fri Oct 20 14:20:01 MDT 2017
- | Date : Wed Dec 12 17:48:50 2018
- | Host : cadence36 running 64-bit major release (build 9200)
- | Command : report_utilization -file artix7_utilization_placed.rpt -pb artix7_utilization_placed.pb
- | Design : artix7
- | Device : 7a35tcpg236-1
- | Design State : Fully Placed
- ---------------------------------------------------------------------------------------------------------
- Utilization Design Information
- Table of Contents
- -----------------
- 1. Slice Logic
- 1.1 Summary of Registers by Type
- 2. Slice Logic Distribution
- 3. Memory
- 4. DSP
- 5. IO and GT Specific
- 6. Clocking
- 7. Specific Feature
- 8. Primitives
- 9. Black Boxes
- 10. Instantiated Netlists
- 1. Slice Logic
- --------------
- +-------------------------+------+-------+-----------+-------+
- | Site Type | Used | Fixed | Available | Util% |
- +-------------------------+------+-------+-----------+-------+
- | Slice LUTs | 2 | 0 | 20800 | <0.01 |
- | LUT as Logic | 2 | 0 | 20800 | <0.01 |
- | LUT as Memory | 0 | 0 | 9600 | 0.00 |
- | Slice Registers | 0 | 0 | 41600 | 0.00 |
- | Register as Flip Flop | 0 | 0 | 41600 | 0.00 |
- | Register as Latch | 0 | 0 | 41600 | 0.00 |
- | F7 Muxes | 0 | 0 | 16300 | 0.00 |
- | F8 Muxes | 0 | 0 | 8150 | 0.00 |
- +-------------------------+------+-------+-----------+-------+
- 1.1 Summary of Registers by Type
- --------------------------------
- +-------+--------------+-------------+--------------+
- | Total | Clock Enable | Synchronous | Asynchronous |
- +-------+--------------+-------------+--------------+
- | 0 | _ | - | - |
- | 0 | _ | - | Set |
- | 0 | _ | - | Reset |
- | 0 | _ | Set | - |
- | 0 | _ | Reset | - |
- | 0 | Yes | - | - |
- | 0 | Yes | - | Set |
- | 0 | Yes | - | Reset |
- | 0 | Yes | Set | - |
- | 0 | Yes | Reset | - |
- +-------+--------------+-------------+--------------+
- 2. Slice Logic Distribution
- ---------------------------
- +--------------------------+------+-------+-----------+-------+
- | Site Type | Used | Fixed | Available | Util% |
- +--------------------------+------+-------+-----------+-------+
- | Slice | 2 | 0 | 8150 | 0.02 |
- | SLICEL | 2 | 0 | | |
- | SLICEM | 0 | 0 | | |
- | LUT as Logic | 2 | 0 | 20800 | <0.01 |
- | using O5 output only | 0 | | | |
- | using O6 output only | 2 | | | |
- | using O5 and O6 | 0 | | | |
- | LUT as Memory | 0 | 0 | 9600 | 0.00 |
- | LUT as Distributed RAM | 0 | 0 | | |
- | LUT as Shift Register | 0 | 0 | | |
- | LUT Flip Flop Pairs | 0 | 0 | 20800 | 0.00 |
- | Unique Control Sets | 0 | | | |
- +--------------------------+------+-------+-----------+-------+
- * Note: Review the Control Sets Report for more information regarding control sets.
- 3. Memory
- ---------
- +----------------+------+-------+-----------+-------+
- | Site Type | Used | Fixed | Available | Util% |
- +----------------+------+-------+-----------+-------+
- | Block RAM Tile | 0 | 0 | 50 | 0.00 |
- | RAMB36/FIFO* | 0 | 0 | 50 | 0.00 |
- | RAMB18 | 0 | 0 | 100 | 0.00 |
- +----------------+------+-------+-----------+-------+
- * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
- 4. DSP
- ------
- +-----------+------+-------+-----------+-------+
- | Site Type | Used | Fixed | Available | Util% |
- +-----------+------+-------+-----------+-------+
- | DSPs | 0 | 0 | 90 | 0.00 |
- +-----------+------+-------+-----------+-------+
- 5. IO and GT Specific
- ---------------------
- +-----------------------------+------+-------+-----------+-------+
- | Site Type | Used | Fixed | Available | Util% |
- +-----------------------------+------+-------+-----------+-------+
- | Bonded IOB | 6 | 6 | 106 | 5.66 |
- | IOB Master Pads | 2 | | | |
- | IOB Slave Pads | 4 | | | |
- | Bonded IPADs | 0 | 0 | 10 | 0.00 |
- | Bonded OPADs | 0 | 0 | 4 | 0.00 |
- | PHY_CONTROL | 0 | 0 | 5 | 0.00 |
- | PHASER_REF | 0 | 0 | 5 | 0.00 |
- | OUT_FIFO | 0 | 0 | 20 | 0.00 |
- | IN_FIFO | 0 | 0 | 20 | 0.00 |
- | IDELAYCTRL | 0 | 0 | 5 | 0.00 |
- | IBUFDS | 0 | 0 | 104 | 0.00 |
- | GTPE2_CHANNEL | 0 | 0 | 2 | 0.00 |
- | PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 |
- | PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 |
- | IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 |
- | IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 |
- | ILOGIC | 0 | 0 | 106 | 0.00 |
- | OLOGIC | 0 | 0 | 106 | 0.00 |
- +-----------------------------+------+-------+-----------+-------+
- 6. Clocking
- -----------
- +------------+------+-------+-----------+-------+
- | Site Type | Used | Fixed | Available | Util% |
- +------------+------+-------+-----------+-------+
- | BUFGCTRL | 0 | 0 | 32 | 0.00 |
- | BUFIO | 0 | 0 | 20 | 0.00 |
- | MMCME2_ADV | 0 | 0 | 5 | 0.00 |
- | PLLE2_ADV | 0 | 0 | 5 | 0.00 |
- | BUFMRCE | 0 | 0 | 10 | 0.00 |
- | BUFHCE | 0 | 0 | 72 | 0.00 |
- | BUFR | 0 | 0 | 20 | 0.00 |
- +------------+------+-------+-----------+-------+
- 7. Specific Feature
- -------------------
- +-------------+------+-------+-----------+-------+
- | Site Type | Used | Fixed | Available | Util% |
- +-------------+------+-------+-----------+-------+
- | BSCANE2 | 0 | 0 | 4 | 0.00 |
- | CAPTUREE2 | 0 | 0 | 1 | 0.00 |
- | DNA_PORT | 0 | 0 | 1 | 0.00 |
- | EFUSE_USR | 0 | 0 | 1 | 0.00 |
- | FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
- | ICAPE2 | 0 | 0 | 2 | 0.00 |
- | PCIE_2_1 | 0 | 0 | 1 | 0.00 |
- | STARTUPE2 | 0 | 0 | 1 | 0.00 |
- | XADC | 0 | 0 | 1 | 0.00 |
- +-------------+------+-------+-----------+-------+
- 8. Primitives
- -------------
- +----------+------+---------------------+
- | Ref Name | Used | Functional Category |
- +----------+------+---------------------+
- | IBUF | 4 | IO |
- | OBUF | 2 | IO |
- | LUT2 | 2 | LUT |
- +----------+------+---------------------+
- 9. Black Boxes
- --------------
- +----------+------+
- | Ref Name | Used |
- +----------+------+
- 10. Instantiated Netlists
- -------------------------
- +----------+------+
- | Ref Name | Used |
- +----------+------+
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