This recent post by u/Mrfrizzl and this post from a while ago inspired me to write a guide on what the different timings, resistances, voltages, and other memory settings on Ryzen do, and to detail how and when to change them.

That means this post is really long, as I will cover basically every setting in Ryzen DRAM Calculator and Ryzen Timing Checker. I would add more, but I’m at the character limit ¯\_(ツ)_/¯. I’ll be discussing DRAM somewhat technically, so if you only care about high frequency and tight timings, I included my personal method for tightening all timings.



Contents:

Introduction
My Methodology
Primary Timings
Secondary Timings
Tertiary Timings
Impedances and CAD_BUS Setup
Voltages
Other (Important!) Miscellaneous Memory Overclocking Features


Introduction:

I constantly see questions about Ryzen memory overclocking on this subreddit. Many commenters say, “Just put in the values from Ryzen DRAM Calculator, it just works!!!”, but for some people this doesn’t work, and others are left curious as to why it works. What do the huge number of settings the interface shows...do? There should be lots of data out there explaining what the values mean, right? Well a guide like this one may already exist...Ryzen’s been out for a while, and there’s an active Ryzen memory overclocking community...but I’ve never seen it. A lot of this information is out there, sure, but not all in one place, and not necessarily in places that are easy to find!

Like others on this sub, when I was overclocking my own memory a couple of months ago, I had a lot of trouble finding any detailed, comprehensive sources for this information. I tried googling all the timings, and often I was only met with 10-year-old threads that hardly told me anything.I want to keep others from struggling like I did, and I want to share what I’ve scraped together so that there’s at least one decent post out there.

(With that said, I will not really cover die-specifics, for that go that here)

Disclaimer: I’m in no way the most knowledgeable person regarding this, and (most of) my information comes from - my own findings from overclocking every timing on my kit (TLRED416G3000HC16CDC01) - my BIOS’s timing descriptions - browsing many forums and threads for anecdotes/data from other Ryzen owners - official blog posts from AMD - publicly available DDR data sheets Also, there are several thing I have not tested myself, and of course this is overclocking so YMMV.

Any input or corrections would be GREATLY appreciated if I made any mistakes. I don’t want to spread misinformation!



If you just want to make all the numbers smaller, here’s my personal Ryzen memory overclocking method. It’s adapted from the flowchart that downloads alongside DRAM Calculator, but changed to basically redo some steps to make sure you really find the sweet spot for your kit. It has room for improvement, and I know the calculator presets bad timings for some dies. However, my approach should mitigate this, since it doesn’t rely on these values and involves changing every timing one at a time instead of hoping the calculator values all just work. (Fair warning though, this process is very lengthy, depending on your stress test duration and by how much you reduce timings between tests.)

For the following, it’s worth mentioning that some of these settings can only be changed on high-end motherboards, while others cannot be manually changed. If I can not corroborate some information, I’ll make a note of it. Furthermore, there’s a few things that you probably won’t ever need to mess with, but they’re there.



First: what do primary timings do? How do they impact memory performance? (There’s plenty of information on these out there, but just so we’re on the same page...)

tCL: Column Access Strobe (CAS) Latency, the delay in clock cycles between when the IMC activates a column of memory for reading and when the address in the column is actually read. This is supposedly the most important timing because the CAS, i.e. the strobe capacitor, is the last thing that needs to activate before data can be read (since rows activate before columns), so a lower tCL means less cycles between when the CPU asks for some data and the data is actually read.

Overclocking guidelines? : Nothing special. Go as low as your kit allows, balancing high frequency with low true CAS latency (tCL / frequency in GHz) to optimize bandwidth with latency.



tRCDWR: Row Address Strobe (RAS) to Column Address Strobe (CAS) Delay (Write). The delay between when a row address is activated and when a column address is activated for writing. The reason for why this timing is important is pretty similar to tCL: it’s the amount of cycles between when a row is activated and when a column is activated, so lower tRCDWR means less delay before writes.

Overclocking guidelines? : Same as above.



tRCDRD: RAS to CAS Delay (Read). The delay between when a row address is activated and when a column address is activated for reading. Basically tRCDWR but for read operations.

Overclocking guidelines? : Same as above.



tRP: Row Precharge Time. The amount of time it takes to deactivate (precharge) one row of memory and activate a new row of memory (on the same rank). You can think of this as essentially the “cooldown” between memory operations on the same rank, or side, of a DIMM. (Sidenote: it’s not necessary true that rank = side, especially for 4 or more DIMMs. If you’re interested, here’s buildzoid’s video about memory ranks).

Overclocking guidelines? : Same as above.



tRAS: RAS Active Time. The minimum amount of time between a row of memory being activated and precharged. This is the amount of cycles that a row of memory can be accessed for reading/writing. Just like the name suggests, it’s how long the RAS capacitor stays active once it receives a signal from the IMC.

Overclocking guidelines? : Hearsay says that a good starting point is something near tCL + tRP. The specific value you can reach depends on the die. For example, a Micron B-die kit like mine can run tRAS very tight. I have it set to 21 (lower than tCL + tRP = 28), the lowest my BIOS allows.



CR: Command Rate. The amount of consecutive clock cycles that commands must be sent to the DRAM to ensure that the command is executed. If this is 1T, the IMC sends each command the memory once; if it’s 2T, then the IMC sends each command twice in a row. Thus, it should be pretty intuitive that a command rate of 2T can help OC stability: if there is any kind of issue with the memory not receiving/executing the command sent in the first signal, it has a second chance.

Overclocking guidelines? : Set to 1T ideally, but 2T may improve stability, especially with 4 or more DIMMs. As a sidenote, AMD recommends disabling Geardown Mode (covered later) for 1T.





Now for the secondary timings. Unfortunately I don’t have as much information on them as I do for primary timings, but it is still enough to understand what they do.

tRC: Row Cycle Time. The minimum amount of time between activation commands to the same memory bank. Just like the name suggests, this is the amount of cycles that the IMC has to wait before it can send another activation signal to a bank of memory. Now you might be wondering: what’s a bank? A bank is a logical unit of memory organization, and the location/dimensions of a bank are determined by your memory controller. That is, it’s a group of rows and columns that can be spread across multiple dies. What constitutes a bank probably varies between manufacturers and/or memory controller models, but it’s really not something to worry about.

Overclocking guidelines? : Hearsay says the lowest this can go is tRAS + tRP. I’m not sure this is a hard limit, but the logic goes as follows: tRAS is the number of cycles from activation to precharging, and tRP is the number of cycles between precharging and the activation of another row. Thus, tRAS + tRP is the number of cycles between activating one row of memory and activating another. If you’ll think back one paragraph, that’s exactly what tRC is for.



tRCPage: Page Time Line Period. I found this timing mentioned in this patent, but I’m having difficulty understanding it, it’s way above my head. It seems to be related to data degradation prevention, though.

Overclocking guidelines? : This timing defaults to 0 in my BIOS, so it’s probably not worth changing.



tRRDS: RAS to RAS Delay, Different Bank Group. The delay between two row activations across different bank groups. Once a row is activated in one bank group, the IMC has to wait this many cycles before a row can be activated in another bank group. Now you might be asking: What’s a bank group? Is that the same as a bank? I don’t know. It’s probably just a group of banks. It doesn’t really matter though.

Overclocking guidelines? : On my kit this timing went as low as my BIOS allows (4), but this may not be true for other kits.



tRRDL: RAS to RAS Delay, Same Bank Group. The delay between two row activations within one bank group. As you probably can guess, this is the same as tRRDS, but regarding a single bank group instead of multiple bank groups.

Overclocking guidelines? : On my kit this timing went as low as my BIOS allows (4), but this may not be true for other kits.



tFAW: Four Activate Window. The amount of time in which four row activations can occur within the same rank. Pretty self explanatory, if the IMC needs to access four different rows of memory within one rank of a DIMM, it will take tFAW cycles to do so.

Overclocking guidelines? : This timing isn’t just hearsay! According to AMD, the minimum for this timing is 4 * tRRDS, but if that isn’t stable, it may be worth trying 8 * tRRDS or higher.



tFAWDLR: All I know is that it’s related to tFAW.

Overclocking guidelines? : Cannot be changed in BIOS, and is locked to 0 for me.



tFAWSLR: See tFAWDLR.

Overclocking guidelines? : Cannot be changed in BIOS, and is locked to 0 for me.



tWTRS: Write to Read Delay, Different Bank Group. The delay between a successful write command and a read command across different bank groups. Once a write command has been finished on a memory address, this is the amount of cycles before a read command can be executed on a row in a different bank group.

Overclocking guidelines? : On my kit this bottomed out at the lowest value my BIOS allows (2), but this may not be true for other kits.



tWTRL: Write to Read Delay, Same Bank Group. The delay between a successful write command and a read command within one bank group. Just like with tRRDS and tRRDL, the only difference between this and tWTRS is which bank groups are involved.

Overclocking guidelines? : On my kit this bottomed out at the lowest value my BIOS allows (7), but this may not be true for other kits.



tWR: Write Recovery Time. The delay between a successful write command and the active bank being precharged. Once a write command to a memory address has finished, it takes this many cycles before the bank (not just the row) containing that address is deactivated.

Overclocking guidelines? : Hearsay says to try setting this to tRAS - tRCD, but my kit went lower, to 14 (when tRAS - tRCD = 20). According to AMD, the lowest this should be set to is 8, as any lower will cause data corruption.

Now the next 8 are all very similar, but have some slight differences between them, so I’ll format this a little differently.



tRDRD _ _ (_): Read to Read Delay. The delay between two read commands. Self explanatory, the number of cycles that must pass after the IMC sends a read command before it can send another. There are 4 variants of this:

tRDRDSC: tRDRD, Different Bank Group. Involves two rows in different bank groups.

tRDRDSCL: tRDRD, Same Bank Group. Involves two rows within one bank group.

tRDRDSD: tRDRD, Different Rank. Involves two rows in different ranks of a DIMM.

tRDRDDD: tRDRD, Different DIMM. Involves two rows on different DIMMs.

Overclocking guidelines? : From what I’ve heard these should all go down to 1 or 2 on most kits; on my kit these all are stable at 1.



tWRWR _ _ (_): Write to Write Delay. The delay between two write commands. Think tRDRD but with two write commands instead of two reads. Again, there are 4 variants:

tWRWRSC: tWRWR, Different Bank Group. Involves two rows in different bank groups.

tWRWRSCL: tWRWR, Same Bank Group. Involves two rows within one bank group.

tWRWRSD: tWRWR, Different Rank. Involves two rows in different ranks of a DIMM.

tWRWRDD: tWRWR, Different DIMM. Involves two rows on different DIMMs.

Overclocking guidelines? : Like with the tRDRD timings, these should all reach 1 or 2, with my kit able to do 1 for all.



Returning to previous formatting, here are the last 6 secondary timings:

tRFC: Refresh Cycle Time. The amount of time between a refresh command and an activation command being executed by the DRAM. Refresh commands are what make DRAM special, and are when a section of memory is read and then the data there immediately rewritten to the same addresses. Each bit of data is just a charge in a capacitor, so refreshing a section of memory prevents it from being physically lost by way of leakage. Anyway, this is the amount of cycles after a refresh command has been issued before a row of (that section of?) the memory can be read again.

Overclocking guidelines? : Hearsay says to start by setting this to around 4 * tRC or 4 * tRC + 8. My kit would not POST at this setting, though. The minimum value I was stable at is 252, while 4 * tRC = 224. Again, use these “rules” as very rough guidelines.



tCWL: CAS Write Latency. The delay between when the IMC activates a column of memory and when a write command is executed. Although not in the timing abbreviation, tCL specifically controls read operations; this timing, then, is just tCL but for write operations. (I’m not sure why it’s not as important as tCL...) According to AMD, this timing significantly impacts stability, which again makes sense, as it is related to the well-known tCL.

Overclocking guidelines? : According to the previously linked AMD “Let’s Talk DRAM!” post, tCWL should be set to roughly tCL - 1. My kit has this stable as low as 10 (with CL13), but any lower absolutely refused to POST.



tRTP: Read to Precharge Delay. The delay between a read command and a row precharge in the same rank. This is the minimum amount of cycles between a row of memory being read and a different row in the same memory rank being deactivated.

Overclocking guidelines? : Nothing special, go as low as you can.



tRDWR: Read Write Command Spacing. The amount of turn-around clocks between a read command and a write command on the same rank. I’m not entirely sure what a turn-around clock is, but I believe it refers to tRDRD/WRWR timings. Anyway, this is the amount of those cycles that must pass after a read command is sent to a memory address before the IMC can send a write command to a different address on the same rank of a DIMM. According to AMD this timing has a large effect on throughput.

Overclocking guidelines? : According to some users (and myself), this timing is somewhat tied to tWRRD, in that only one of the two can be set to a very low value, while the other must be set to a higher value. One approach to tightening these two timings is to set one to auto, lower one all the way, and then take the other off auto and manually tighten it.



tWRRD: Write Read Command Spacing. The amount of turn-around clocks between a write command and a read command on the same rank. This is basically tRDWR, but after a write command and before a read command instead of vice versa. According to AMD this timing has a large effect on throughput.

Overclocking guidelines? : See tRDWR.



tCKE: Clock Enable Time. The minimum amount of time it takes for a CKE pulse to occur. This one is one of the more technically involved timings here, so I may not have this exactly correct. From what I can tell, a CKE pulse changes a DIMM’s power state. There are two kinds: CKE LOW and CKE HIGH. CKE LOW causes the DIMM to enter powerdown mode for the duration of a clock cycle, while CKE HIGH causes the DIMM to exit powerdown mode for the rest of a cycle. CKE LOW prevents the memory from receiving unwanted commands (i.e. puts it in an idle state), whereas CKE HIGH allows the memory to receive all commands from the IMC (i.e. puts it in an active state).

Overclocking guidelines? : According to at least one overclock.net user, lowering tCKE allows for further tightening of some timings, although that needs testing and data for verification. I could only lower this timing slightly before my system stopped POSTing.



tRPPB: Row Precharge Time, Per-Bank/Single Bank. I believe this is the minimum amount of time between a row of memory being precharged and another row in the same bank being available for reading. It may be the number of extra cycles in addition to tRP that must pass between two row precharges, though I’m not sure, since the sources I found only discuss this in regard to LPDRAM. For LPDRAM, the data sheets I found say tRC = tRAS + tRPPB. However I don’t know that that applies to SDRAM.

Overclocking guidelines? : Cannot be changed in BIOS, and is locked to 0 for me.



tRCPB: Row Cycle Time, Per-Bank/Single Bank. I couldn’t find anything whatsoever on Google, so this name is only an inference based on my findings for tRPPB. I presume this is also something related to LPDRAM specifically.

Overclocking guidelines? : Cannot be changed in BIOS, and is locked to 0 for me.



tRRDDLR: I have no idea, I couldn’t find anything whatsoever on Google.

Overclocking guidelines? : Cannot be changed in BIOS, and is locked to 0 for me.



tRDRDBAN: Read to Read Timing Ban. Once a CAS has been activated for a read operation, the CAS is banned (i.e. blocked) from receiving another read activation signal until a certain number of cycles (corresponding to the Ban #) has passed. The different settings are as follows:

Ban 0 - no ban, control of signal traffic done by tRDRDSDSC, tRDRDSDDC, and tRDRDDD.

Ban 1 - bans tRDRD for one clock cycles.

Ban 2 - bans tRDRD for two clock cycles.

Overclocking guidelines? : Cannot be changed in BIOS, and is locked to Ban 2 for me.



tRDRDSCDLR: I have no idea, I couldn’t find anything whatsoever on Google.

Overclocking guidelines? : Cannot be changed in BIOS, and is locked to 0 for me.



tWRWRBAN: Write to Write Timing Ban. Basically tRDRDBAN, but regarding write operations.

Overclocking guidelines? : Cannot be changed in BIOS, and is locked to Ban 2 for me.



tWRWRSCDLR: I have no idea, I couldn’t find anything whatsoever on Google.

Overclocking guidelines? : Cannot be changed in BIOS, and is locked to 0 for me.



tWRRDSCDLR: I have no idea, I couldn’t find anything whatsoever on Google.

Overclocking guidelines? : Cannot be changed in BIOS, and is locked to 0 for me.





Now for tertiary timings. I had great difficulty finding anything about these, with the exception of tREF. I can’t change any of these in my BIOS, so this section omits overclocking guidelines. This is exclusively for those curious about what these timings are called/do. I would appreciate input if anybody knows anything about these timings.



tREF: Refresh Time. The amount of time between memory refreshes. Pretty self explanatory. The higher this is, the more cycles in between refresh command executions, i.e. the data is guaranteed to be stored for longer, but at the risk of degradation.

tMOD: MRS (Mode Register Set) Command to Non-MRS Command Delay. From what I can understand, DRAM modules contain a section of memory called the mode register, and it seems to have something to do with power states. At the very least, this timing seems to be related to tCKE, ProcODT, and RTT_NOM. To be more specific, it appears that the CKE state (LOW/HIGH) will only change if certain parameters are satisfied for at least tMOD + tMRD clock cycles.

tMODPDA: MRS (Mode Register Set) Command to Non-MRS Command Delay, Per DRAM Addressability Mode. Same as above regarding tMOD. Per DRAM Addressability Mode, or PDA, seems to save a single MRS value across a DIMM, which seems to have something to do with preventing data degradation.

tMRD: Mode Register Set Command Cycle Time. See tMOD.

tMRDPDA: Mode Register Set Command Cycle Time, Per DRAM Addressability Mode. See tMODPDA.

tSTAG: Subrefresh Staggering Delay. Seems to be related to tREF, in that it involves staggering memory refresh commands to minimize the amount of memory addresses that are being refreshed at any given moment.

tSTAGLR: I have no idea, I couldn’t find anything whatsoever on Google. Otherwise, it’s obviously related to tSTAG somehow. It’s disabled for me, which may suggest it’s some kind of offset.

tPHYWRD: I believe this is related to something called a PHY chip, which is a kind of digital-to-analog microcontroller found within the Ryzen SoC. This timing also appears to be related to write commands.

tPHYWRL: Same as above.

tPHYRDL: Same as the two above, but related to read operations instead.

tRDDATA: I have no idea, but it’s probably related to data...which is entirely unhelpful.

tWRMPR: I have no idea, I couldn’t find anything whatsoever on Google.

[The aforementioned “Let’s Talk DRAM!” post mentions a couple other timings, namely tMAW and tMAC, but Ryzen Timing Checker only shows the ones above to me. My research also shows that there’s some other obscure timings, but they’re all very technically involved and you can’t change them anyway, so I don’t feel the need to spend my time deciphering those].





That’s all the timings! Now for the termination resistances/impedances (as well as a couple timings related to one set of them). In general you should need to change these only when you’re having serious issues getting a certain frequency/set of timings stable. For example: not POSTing, instant BSODs, or constant memory errors.

Termination Resistances:

ProcODT: Processor On-Die Termination Impedance. The resistance which a memory signal travelling to the CPU terminates at. This reduces signal noise and lowers how much the signal over- and undershoots the voltage that the signal should be sent at. From what I understand, going too low can allow signal noise to send faulty signals to the memory, but going too high can actually cause a signal to be absorbed and not reach the processor. This defaults to 53.3Ω.

Overclocking guidelines? : This is probably the most important value to change in this section to improve overclock stability. Notice I only said change, as it is generally accepted that RAM kits have different “preferences” for this value; that is, higher is not necessarily better. The overclocking community recommends keeping this in the range of 40Ω-80Ω, while AMD recommends 60Ω-96Ω. (However, for values of at least 80Ω, you should ensure that your memory is receiving some airflow.) As a rule of thumb, dual rank memory requires this value to be higher than single rank memory, but this does not mean that single rank memory cannot benefit from higher values.



RTT_PARK: Park On-Die Termination Impedance. The resistance at which signals sent to a memory die will terminate when ODT is low. I believe this is related to CKE LOW/Powerdown Mode. From what I can decipher, when RTT_NOM is disabled/off, this value seems to take over. This resistance can help prevent signal integrity loss to dies in which the memory is not executing write commands. The values for this are measured in terms of fractions of RZQ, which is a reference 240Ω resistor.

Overclocking guidelines? : To be honest I’m not really sure exactly how to tune this, but theoretically (and as corroborated by Ryzen DRAM Calculator) a higher value for this may be necessary to stabilize an overclock, as it should help signal integrity. However, like with ProcODT, too high of a resistance probably causes instability by way of signal absorption. Furthermore, several users have reported lower values working better. According to one Micron data sheet, this should be disabled for single-rank DIMMs and enabled for dual-rank DIMMs, but I have not tested this myself.



RTT_NOM: Nominal On-Die Termination Impedance. For high ODT, this is the termination resistance for signals sent to a memory die not being written to, but which is connected to one that is being written to. I believe this is related to CKE HIGH pulses. This resistance can help prevent signal integrity loss when the memory is not executing write commands. The values for this are also measured in terms of fractions of RZQ.

Overclocking guidelines? : See RTT_PARK.



RTT_WR: Dynamic/Write On-Die Termination Impedance. This is the resistance at which signals sending write commands to a memory die will terminate at. This resistance can help prevent signal integrity loss when the memory is executing write commands. The values for this are also measured in terms of fractions of RZQ.

Overclocking guidelines? : Like the previous two I don’t personally know how to tune these, and simply used DRAM Calculator values, but in theory higher can improve stability. Though again, several users have reported lower values working better. The aforementioned data sheet says that memory rank does not impact whether this should be enabled or disabled, so changing this may be purely trial and error and something of a matter of kit “preference.”



CAD_BUS Resistances:

ClkDrv or CLKDrvStr(en): Clock Drive Strength/Impedance. The resistance on the MEMCLK (memory clock) drive pins on the CPU (or memory controller?). This adjusts the strength of the signal that controls memory clock. I believe this should have some effect on stabilizing memory frequency, and theoretically higher values may improve signal quality to the corresponding pin.

Overclocking guidelines? : The minimum value of 20Ω is recommended, but higher settings (to a point) may aid in stability.



AddrCmdDrv or AddrCmdDrvStr(en): Address/Command Drive Strength/Impedance. The resistance on the following CPU (or memory controller?) pins: address, RAS, CAS, WE, bank, parity. Theoretically, then, raising it can increase stability of tight timings. However, I have not tested that specifically.

Overclocking guidelines? : See ClkDrv.



CsOdtDrv or CsOdtDrvStr(en): Chip Select/On Die Termination Drive Strength/Impedance. The resistance on the CS and ODT pins on the CPU (or memory controller?). This adjusts the strength of the signals controlling Chip Select (which is self explanatory) and ODT (which in this context is related to CKE and DRAM powerdown state). As before, raising might be helpful, but isn’t necessarily.

Overclocking guidelines? : See ClkDrv.



CkeDrv or CKEDrvStr(en): CKE (Clock Enable) Drive Strength/Impedance. The resistance on the CKE pins on the CPU (or memory controller?). This adjusts the strength of the CKE signal, which I discussed previously. As before, raising might be helpful, but isn’t necessarily.

Overclocking guidelines? : See ClkDrv.



CAD_BUS Timings:

AddrCmd(Setup): Address/Command Setup Time. The setup time for the address and command pins of the CPU (or memory controller?) with respect to a memory clock. Essentially, this prepares the address and command pins a fraction of a memory clock before a read or write command must be sent. If set to 0, then the pins will set up 1/2 of a clock before the command is sent for CR=1T or 1 1/2 clocks before the command is sent for CR=2T. If set to 1, the number of clock cycles for setup will equal your command rate.

Overclocking guidelines? : You shouldn’t need to change this, and should leave at 0 ideally, but 1 might improve stability. However, I have not tested this myself.



CsOdt(Setup): CS/ODT Setup Time. The setup time for the CS and ODT pins of the CPU (or memory controller?) with respect to a memory clock. If set to 0, the pins will set up 1/2 of a clock before a read or write command is sent. If set to 1, they will set up 1 clock before.

Overclocking guidelines? : See AddrCmd(Setup).



Cke(Setup): CKE Setup Time. The setup time for the CKE pins of the CPU (or memory controller?) with respect to a memory clock. See CsOdt(Setup) for behavior.

Overclocking guidelines? : See AddrCmd(Setup).



Now if you’re still with me after all of that, let’s talk about what the different voltages do. For the sake of completeness I will include the trivial ones as well (VDIMM and VSOC). Most of these I cannot change in my BIOS, so I don’t have any personal information on the non-trivial ones.

VDIMM: DRAM Voltage. The voltage fed directly to your memory through the memory VRM. Different memory kits scale with VDIMM differently, so depending on your die this will impact memory stability differently.

Overclocking guidelines? : It is generally accepted that this can go as high as 1.45V or 1.5V, but some kits do not need/like it so high. See the r/overclocking DDR4 guide for more information.



VSOC: System on a Chip Voltage. The voltage sent through the SoC VRM; the SoC contains various interfaces and controllers, including the memory controller.

Overclocking guidelines? : More VSOC can improve stability, notably when pushing higher memory frequency. Ideally this should be kept low, somewhere in the range of 1V-1.15V, but this can be set up to 1.2V safely (though it’s in question as to whether this much voltage does much).



VTT_DDR: DDR Termination Voltage. Controls memory bus impedance. Apparently this voltage is useful for maintaining signal integrity, and is likely related to termination resistances.

Overclocking guidelines? : My BIOS doesn’t have this, but you should keep this around half of VDIMM, though raising it by a few millivolts can help stability at high frequencies.



VPP: Programming Power Voltage. Used to activate word line transistors. I’m not entirely sure what the technical significance of this is, but according to Micron, if this is too low then RAM will not function correctly. Default is 2.5V.

Overclocking guidelines? : I’m not sure what to do for this voltage as my BIOS does not have it, but DRAM Calculator suggests that either raising or lowering this by about 20-30 millivolts can improve stability.



PLL Voltage: Phase-Locked Loop Voltage. The voltage supplied to the PLL circuit. The PLL circuit essentially prevents the desynchronization of certain signals from one another, as well as mitigating certain delays. From what I understand, it can be important in maintaining stability at high frequencies. Default is 1.8V.

Overclocking guidelines? : As with VPP, I’m not sure what to do for this voltage as my BIOS does not have it, but DRAM Calculator suggests that either raising or lowering this by about 30 millivolts can improve stability.



CLDO_VDDP: DDR4 PHY Voltage. The voltage supplied to the SoC PHY chip. Changing this require a cold restart (shutdown, unplug PSU for a few seconds, and then restart). Tweaking this voltage can resolve memory holes. A memory hole is a specific range of frequencies that your memory won’t run. For example, a kit may boot fine at 3400 or 3600, but near 3466 it will fail to POST.

Overclocking guidelines? : Tweak this voltage a little lower or higher (but not above 1050 mV) to resolve a memory hole. Supposedly VDIMM - 100mV is a good value to try.



VDDP: DDR4 PHY Voltage. The voltage supplied to the SoC PHY chip, but from an external current monitor. Basically CLDO_VDDP but (I would think) a little higher, as this value does not account for some Vdroop.

Overclocking guidelines? : Update your BIOS, this no longer exists on BIOSes using the AGESA 1.0.0.6 firmware.





Last but definitely not least, I will cover some of the other miscellaneous settings.

Spread Spectrum: This setting reduces the electromagnetic interference (EMI) produced by your VRM. The point of this is to quite literally spread out the spectrum of frequencies that your memory runs at. Thus, your memory will run at a slightly wider range of frequencies than what you set in BIOS.

Overclocking guidelines? : Some have reported that this sometimes improve overclock stability, but others warn against it since the frequency variation can drastically reduce stability. It may be worth trying to turn it on, but you theoretically should keep it off unless you live somewhere where there’s a lot of EMI for whatever reason.



Geardown Mode: Overrides CR and runs some timings off an internal ½-frequency clock when storing certain values. Recall that DDR means double data rate because the effective memory clock is double the actual memory clock. What this means, then, is that all timings will be rounded up to the nearest even number, since your memory will skip half of the effective clock cycles. To further clarify why this is, if you’re running your memory at... let’s say 3000CL13, then enabling Geardown would run it at 1500CL6.5 except you can’t have decimal timings, so it would actually run it at 1500CL7, which has the same latency as 3000CL14.

Overclocking guidelines? : This lowers performance slightly for CR=1T, but according to AMD it *may** run better than CR=2T, depending on your timings.* This should be used if you’re having difficulty stabilizing a certain memory clock, while using odd timings, and if your issues are not serious enough to warrant changing things like termination resistances.



Powerdown Mode: Lowers VDIMM when the system is at idle. This can save a little bit of power, but it reportedly can cause issues with stability, and slightly increases DRAM latency.

Overclocking guidelines? : It’s off by default, so keep it off.



BankGroupSwap: Changes how applications are assigned to memory locations. According to the same AMD post linked just a couple paragraphs ago, this essentially optimizes performance for synthetic workloads (like benchmarks or compute applications) when enabled, or games when disabled.

Overclocking guidelines? : Well AMD pretty much explained it for me. Enable it for gaming, and disable it otherwise.



Memory Interleaving: Controls the mode by which memory is interleaved (shockingly). Memory interleaving is a method of increasing memory bandwidth by organizing memory blocks across multiple memory banks to prevent what are essentially “stutters” in memory access. One motherboard manual suggests that it has the following modes: Auto, None, Channel, Die, Socket.

Overclocking guidelines? : I don’t know as it does not appear in my BIOS. I believe this defaults to channel mode, and DRAM Calculator recommends keeping it at that. Apparently it is a setting that is mainly important for Threadripper and Epyc, though I would like further verification of that.



Memory Interleaving Size: Controls the memory interleaving size (another big surprise) and changes at which bit at which interleaving begins. One motherboard manual suggests that it has the following values: Auto, 256B, 512B, 1KB, 2KB.

Overclocking guidelines? : I don’t know as it does not appear in my BIOS. DRAM Calculator suggests a value of 2KB, but one overclock.net user claimed he saw improved stability and bandwidth with 256B. Apparently it is a setting that is mainly important for Threadripper and Epyc, though I would like further verification of that.



Channel Interleaving Hash: Controls hashing of address bits when memory interleaving mode is set to channel. I don’t know what this does, though.

Overclocking guidelines? : I’m clueless. This may also be something that’s more important for Threadripper and Epyc, but again I don’t know.



DRAM R1/R2/R3/R4 Tune: I have no idea.

Overclocking guidelines? : These settings only exists on the Crosshair VI Hero and Crosshair VI Extreme, and I don’t have either of those boards so I don’t know what to do. According to the creator of DRAM Calculator, 63 is the default for these settings, with 40 potentially improving overclock stability.



L1/L2 Stream HW Prefetcher: Control whether the CPU prefetches data from memory that may be accessed soon. If disabled, then (I believe) your CPU will simply not prefetch, which is, well, a bad thing for performance.

Overclocking guidelines? : I believe these settings only exists on the Crosshair VI Hero and Crosshair VI Extreme. If your BIOS shows them, keep them on.



Super I/O Clock Skew: I have no idea, but my reading about DRAM leads me to believe that clock skew is bad and something to be corrected. The logical extension of that, then, is that this setting should be left off.

Overclocking guidelines? : As corroborated by DRAM Calculator, keep it off.



Opcache: Controls whether instructions recently decoded by the CPU are stored, so as to prevent them from being re-decoded. The purpose of this is to essentially prevent the CPU from doing extra work, i.e. save power. This could also improve the efficiency and performance of the CPU in certain workloads.

Overclocking guidelines? : Supposedly enabling it increases performance, but I have not tested that. At worst, your system draws slightly less power with it enabled.



Memory Clear: Zeroes out all bits of memory upon boot (probably).

Overclocking guidelines? : I don’t know. Maybe this helps with POSTing?



And that’s all! If you read all the way through then hopefully I helped you gain a better grasp for how DRAM works and how to go about the very complicated thing that is memory overclocking. Once again, if you have any feedback or corrections on this information please let me know, I don’t want any inaccurate information in here.