amd_emmc_patch

diff --git a/sys/dev/sdhci/sdhci.c b/sys/dev/sdhci/sdhci.c
index f117fb49c88..dd6e81d7f3e 100644
--- a/sys/dev/sdhci/sdhci.c
+++ b/sys/dev/sdhci/sdhci.c
@@ -898,6 +898,8 @@ sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
    if (slot->quirks & SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 &&
        caps2 & SDHCI_CAN_MMC_HS400)
        host_caps |= MMC_CAP_MMC_HS400;
+   if (slot->quirks & SDHCI_QUIRK_AMD_FOR_MMC_HS400 && caps2 & SDHCI_CAN_SDR104)
+       host_caps |= MMC_CAP_MMC_HS400;

    /*
     * Disable UHS-I and eMMC modes if the set_uhs_timing method is the
@@ -1174,6 +1176,7 @@ sdhci_generic_set_uhs_timing(device_t brdev __unused, struct sdhci_slot *slot)
 {
    struct mmc_ios *ios;
    uint16_t hostctrl2;
+   uint16_t old_timing;

    if (slot->version < SDHCI_SPEC_300)
        return;
@@ -1182,6 +1185,7 @@ sdhci_generic_set_uhs_timing(device_t brdev __unused, struct sdhci_slot *slot)
    ios = &slot->host.ios;
    sdhci_set_clock(slot, 0);
    hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
+   old_timing = hostctrl2;
    hostctrl2 &= ~SDHCI_CTRL2_UHS_MASK;
    if (ios->clock > SD_SDR50_MAX) {
        if (ios->timing == bus_timing_mmc_hs400 ||
@@ -1202,6 +1206,15 @@ sdhci_generic_set_uhs_timing(device_t brdev __unused, struct sdhci_slot *slot)
        hostctrl2 |= SDHCI_CTRL2_UHS_SDR12;
    WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
    sdhci_set_clock(slot, ios->clock);
+
+   old_timing &= SDHCI_CTRL2_UHS_MASK;
+
+   if (slot->quirks & SDHCI_QUIRK_AMD_FOR_MMC_HS400 &&
+       (old_timing == SDHCI_CTRL2_UHS_SDR104 &&
+        ios->timing == bus_timing_hs)) {
+           hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
+           WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 & ~SDHCI_CTRL2_SAMPLING_CLOCK);
+   }
 }

 int
diff --git a/sys/dev/sdhci/sdhci.h b/sys/dev/sdhci/sdhci.h
index 76067280089..df02a854b2a 100644
--- a/sys/dev/sdhci/sdhci.h
+++ b/sys/dev/sdhci/sdhci.h
@@ -93,6 +93,10 @@
 #define    SDHCI_QUIRK_PRESET_VALUE_BROKEN         (1 << 27)
 /* Controller does not support or the support for ACMD12 is broken. */
 #define    SDHCI_QUIRK_BROKEN_AUTO_STOP            (1 << 28)
+/* Controller requires disabling the tuning bit when transitioning from HS200 to HS mode*/
+#define SDHCI_QUIRK_AMD_FOR_MMC_HS400          (1 << 29)
+
+

 /*
  * Controller registers
diff --git a/sys/dev/sdhci/sdhci_acpi.c b/sys/dev/sdhci/sdhci_acpi.c
index 844be21d64b..544006442d7 100644
--- a/sys/dev/sdhci/sdhci_acpi.c
+++ b/sys/dev/sdhci/sdhci_acpi.c
@@ -79,6 +79,11 @@ static const struct sdhci_acpi_device {
        SDHCI_QUIRK_MMC_DDR52 |
        SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
        SDHCI_QUIRK_PRESET_VALUE_BROKEN },
+   { "AMDI0040", 0, "AMD eMMC 5.0 Controller",
+       //SDHCI_QUIRK_MMC_DDR52 |
+       SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
+       SDHCI_QUIRK_32BIT_DMA_SIZE |
+       SDHCI_QUIRK_AMD_FOR_MMC_HS400 },
    { NULL, 0, NULL, 0}
 };

@@ -87,6 +92,7 @@ static char *sdhci_ids[] = {
    "80860F16",
    "80865ACA",
    "80865ACC",
+   "AMDI0040",
    NULL
 };