module if_stage(pc, instruction, pcSrc, offset, clk);
    output reg [31:0] pc = 0;
    output [31:0] instruction;

    input pcSrc, clk;
    input [31:0] offset;

    assign instruction = 0;

    always@(posedge clk)
        pc = pc + 1;

endmodule

module main;
    reg clk = 1'b0;
    reg pcSrc = 1'b0;
    wire [31:0] pc = 0;
    wire [31:0] instruction = 0;
    reg [31:0] offset = 0;
    if_stage if_stage(pc, instruction, pcSrc, offset, clk);

    initial #300 $finish;
    initial
        begin
            repeat (10)
            #10 clk = ~clk ;
        end

    initial
    begin
        $monitor("Clk:%d, PC:%d, I:%d, PCSrc:%d, Offset:%d", clk, pc, instruction, pcSrc, offset);
    end

endmodule