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[wip:20200102] add F1C100s support

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  1. diff -uNpr sunxi.orig/files.sunxi sunxi/files.sunxi
  2. --- sunxi.orig/files.sunxi 2019-12-10 12:01:47.000000000 +0900
  3. +++ sunxi/files.sunxi 2020-01-02 12:14:40.577814807 +0900
  4. @@ -77,6 +77,11 @@ device sun50ih6rccu: sunxi_ccu
  5. attach sun50ih6rccu at fdt with sunxi_h6_r_ccu
  6. file arch/arm/sunxi/sun50i_h6_r_ccu.c sunxi_h6_r_ccu
  7.  
  8. +# CCU (F1C100s)
  9. +device sunivf1c100sccu: sunxi_ccu
  10. +attach sunivf1c100sccu at fdt with suniv_f1c100s_ccu
  11. +file arch/arm/sunxi/suniv_f1c100s_ccu.c suniv_f1c100s_ccu
  12. +
  13. # Misc. clock resets
  14. device sunxiresets
  15. attach sunxiresets at fdt with sunxi_resets
  16. @@ -134,6 +139,7 @@ file arch/arm/sunxi/sun8i_h3_gpio.c sun
  17. file arch/arm/sunxi/sun9i_a80_gpio.c sunxi_gpio & soc_sun9i_a80
  18. file arch/arm/sunxi/sun50i_a64_gpio.c sunxi_gpio & soc_sun50i_a64
  19. file arch/arm/sunxi/sun50i_h6_gpio.c sunxi_gpio & soc_sun50i_h6
  20. +file arch/arm/sunxi/suniv_f1c100s_gpio.c sunxi_gpio & soc_suniv_f1c100s
  21.  
  22. # PWM
  23. device sunxipwm: pwm
  24. @@ -389,3 +395,4 @@ defflag opt_soc.h SOC_SUN50I: SOC_SUNX
  25. defflag opt_soc.h SOC_SUN50I_A64: SOC_SUN50I
  26. defflag opt_soc.h SOC_SUN50I_H5: SOC_SUN50I, SOC_SUN8I_H3
  27. defflag opt_soc.h SOC_SUN50I_H6: SOC_SUN50I
  28. +defflag opt_soc.h SOC_SUNIV_F1C100S: SOC_SUNXI
  29. diff -uNpr sunxi.orig/suniv_f1c100s_ccu.c sunxi/suniv_f1c100s_ccu.c
  30. --- sunxi.orig/suniv_f1c100s_ccu.c 1970-01-01 09:00:00.000000000 +0900
  31. +++ sunxi/suniv_f1c100s_ccu.c 2020-01-02 11:46:01.839322117 +0900
  32. @@ -0,0 +1,253 @@
  33. +/* $NetBSD: suniv_f1c100s_ccu.c,v 1.5 2017/11/09 21:52:32 jmcneill Exp $ */
  34. +
  35. +/*-
  36. + * Copyright (c) 2017 Jared McNeill <[email protected]>
  37. + * All rights reserved.
  38. + *
  39. + * Redistribution and use in source and binary forms, with or without
  40. + * modification, are permitted provided that the following conditions
  41. + * are met:
  42. + * 1. Redistributions of source code must retain the above copyright
  43. + * notice, this list of conditions and the following disclaimer.
  44. + * 2. Redistributions in binary form must reproduce the above copyright
  45. + * notice, this list of conditions and the following disclaimer in the
  46. + * documentation and/or other materials provided with the distribution.
  47. + *
  48. + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  49. + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  50. + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  51. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  52. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  53. + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  54. + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  55. + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  56. + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  57. + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  58. + * SUCH DAMAGE.
  59. + */
  60. +
  61. +#include <sys/cdefs.h>
  62. +
  63. +__KERNEL_RCSID(1, "$NetBSD: suniv_f1c100s_ccu.c,v 1.5 2017/11/09 21:52:32 jmcneill Exp $");
  64. +
  65. +#include <sys/param.h>
  66. +#include <sys/bus.h>
  67. +#include <sys/device.h>
  68. +#include <sys/systm.h>
  69. +
  70. +#include <dev/fdt/fdtvar.h>
  71. +
  72. +#include <arm/sunxi/sunxi_ccu.h>
  73. +#include <arm/sunxi/suniv_f1c100s_ccu.h>
  74. +
  75. +#define PLL_CPU_CTRL_REG 0x000
  76. +#define PLL_AUDIO_CTRL_REG 0x008
  77. +#define PLL_VIDEO_CTRL_REG 0x010
  78. +#define PLL_VE_CTRL_REG 0x018
  79. +#define PLL_DDR_CTRL_REG 0x020
  80. +#define PLL_PERIPH_CTRL_REG 0x028
  81. +#define CPU_CLK_SRC_REG 0x050
  82. +#define AHB_APB_HCLKC_CFG_REG 0x054
  83. +#define BUS_CLK_GATING_REG0 0x060
  84. +#define BUS_CLK_GATING_REG1 0x064
  85. +#define BUS_CLK_GATING_REG2 0x068
  86. +#define SDMMC0_CLK_REG 0x088
  87. +#define SDMMC1_CLK_REG 0x08c
  88. +#define DAUDIO_CLK_REG 0x0b0
  89. +#define OWA_CLK_REG 0x0b4
  90. +#define CIR_CLK_REG 0x0b8
  91. +#define USBPHY_CLK_REG 0x0cc
  92. +#define DRAM_GATING_REG 0x100
  93. +#define BE_CLK_REG 0x104
  94. +#define FE_CLK_REG 0x10c
  95. +#define TCON_CLK_REG 0x118
  96. +#define DI_CLK_REG 0x11c
  97. +#define TVE_CLK_REG 0x120
  98. +#define TVD_CLK_REG 0x124
  99. +#define CSI_CLK_REG 0x134
  100. +#define VE_CLK_REG 0x13c
  101. +#define AUDIO_CODEC_CLK_REG 0x140
  102. +#define AVS_CLK_REG 0x144
  103. +#define PLL_STABLE_TIME_REG0 0x200
  104. +#define PLL_STABLE_TIME_REG1 0x204
  105. +#define PLL_CPU_BIAS_REG 0x220
  106. +#define PLL_AUDIO_BIAS_REG 0x224
  107. +#define PLL_VIDEO_BIAS_REG 0x228
  108. +#define PLL_VE_BIAS_REG 0x22c
  109. +#define PLL_DDR_BIAS_REG 0x230
  110. +#define PLL_PERIPH_BIAS_REG 0x234
  111. +#define PLL_CPU_TUN_REG 0x250
  112. +#define PLL_DDR_TUN_REG 0x260
  113. +#define PLL_AUDIO_PAT_CTRL_REG 0x284
  114. +#define PLL_VIDEO_PAT_CTRL_REG 0x288
  115. +#define PLL_DDR_PAT_CTRL_REG 0x290
  116. +#define BUS_SOFT_RST_REG0 0x2c0
  117. +#define BUS_SOFT_RST_REG1 0x2c4
  118. +#define BUS_SOFT_RST_REG2 0x2d0
  119. +
  120. +static int suniv_f1c100s_ccu_match(device_t, cfdata_t, void *);
  121. +static void suniv_f1c100s_ccu_attach(device_t, device_t, void *);
  122. +
  123. +static const char * const compatible[] = {
  124. + "allwinner,suniv-f1c100s-ccu",
  125. + NULL
  126. +};
  127. +
  128. +CFATTACH_DECL_NEW(suniv_f1c100s_ccu, sizeof(struct sunxi_ccu_softc),
  129. + suniv_f1c100s_ccu_match, suniv_f1c100s_ccu_attach, NULL, NULL);
  130. +
  131. +static struct sunxi_ccu_reset suniv_f1c100s_ccu_resets[] = {
  132. + SUNXI_CCU_RESET(F1C100S_RST_USB_PHY0, USBPHY_CLK_REG, 0);
  133. + SUNXI_CCU_RESET(F1C100S_RST_BUS_DMA, BUS_SOFT_RST_REG0, 6);
  134. + SUNXI_CCU_RESET(F1C100S_RST_BUS_MMC0, BUS_SOFT_RST_REG0, 8);
  135. + SUNXI_CCU_RESET(F1C100S_RST_BUS_MMC1, BUS_SOFT_RST_REG0, 9);
  136. + SUNXI_CCU_RESET(F1C100S_RST_BUS_DRAM, BUS_SOFT_RST_REG0, 14);
  137. + SUNXI_CCU_RESET(F1C100S_RST_BUS_SPI0, BUS_SOFT_RST_REG0, 20);
  138. + SUNXI_CCU_RESET(F1C100S_RST_BUS_SPI1, BUS_SOFT_RST_REG0, 21);
  139. + SUNXI_CCU_RESET(F1C100S_RST_BUS_OTG, BUS_SOFT_RST_REG0, 24);
  140. + SUNXI_CCU_RESET(F1C100S_RST_BUS_VE, BUS_SOFT_RST_REG1, 0);
  141. + SUNXI_CCU_RESET(F1C100S_RST_BUS_LCD, BUS_SOFT_RST_REG1, 4);
  142. + SUNXI_CCU_RESET(F1C100S_RST_BUS_DEINTERLACE, BUS_SOFT_RST_REG1, 5);
  143. + SUNXI_CCU_RESET(F1C100S_RST_BUS_CSI, BUS_SOFT_RST_REG1, 8);
  144. + SUNXI_CCU_RESET(F1C100S_RST_BUS_TVD, BUS_SOFT_RST_REG1, 9);
  145. + SUNXI_CCU_RESET(F1C100S_RST_BUS_TVE, 10);
  146. + SUNXI_CCU_RESET(F1C100S_RST_BUS_DE_BE, BUS_SOFT_RST_REG1, 12);
  147. + SUNXI_CCU_RESET(F1C100S_RST_BUS_DE_FE, BUS_SOFT_RST_REG1, 14);
  148. + SUNXI_CCU_RESET(F1C100S_RST_BUS_CODEC, BUS_SOFT_RST_REG2, 0);
  149. + SUNXI_CCU_RESET(F1C100S_RST_BUS_SPDIF, BUS_SOFT_RST_REG2, 1);
  150. + SUNXI_CCU_RESET(F1C100S_RST_BUS_IR, BUS_SOFT_RST_REG2, 2);
  151. + SUNXI_CCU_RESET(F1C100S_RST_BUS_RSB, BUS_SOFT_RST_REG2, 3);
  152. + SUNXI_CCU_RESET(F1C100S_RST_BUS_I2S0, BUS_SOFT_RST_REG2, 12);
  153. + SUNXI_CCU_RESET(F1C100S_RST_BUS_I2C0, BUS_SOFT_RST_REG2, 16);
  154. + SUNXI_CCU_RESET(F1C100S_RST_BUS_I2C1, BUS_SOFT_RST_REG2, 17);
  155. + SUNXI_CCU_RESET(F1C100S_RST_BUS_I2C2, BUS_SOFT_RST_REG2, 18);
  156. + SUNXI_CCU_RESET(F1C100S_RST_BUS_UART0, BUS_SOFT_RST_REG2, 20);
  157. + SUNXI_CCU_RESET(F1C100S_RST_BUS_UART1, BUS_SOFT_RST_REG2, 21);
  158. + SUNXI_CCU_RESET(F1C100S_RST_BUS_UART2, BUS_SOFT_RST_REG2, 22);
  159. +};
  160. +
  161. +static const char *mod_parents[] = { "osc24m" };
  162. +
  163. +static struct sunxi_ccu_clk suniv_f1c100s_ccu_clks[] = {
  164. + SUNXI_CCU_NM(F1C100S_CLK_MMC0, "mmc0", mod_parents,
  165. + SDMMC0_CLK_REG, /* reg */
  166. + __BITS(17,16), /* n */
  167. + __BITS(3,0), /* m */
  168. + __BITS(25,24), /* sel */
  169. + __BIT(31), /* enable */
  170. + SUNXI_CCU_NM_POWER_OF_TWO),
  171. + SUNXI_CCU_NM(F1C100S_CLK_MMC1, "mmc1", mod_parents,
  172. + SDMMC1_CLK_REG, /* reg */
  173. + __BITS(17,16), /* n */
  174. + __BITS(3,0), /* m */
  175. + __BITS(25,24), /* sel */
  176. + __BIT(31), /* enable */
  177. + SUNXI_CCU_NM_POWER_OF_TWO),
  178. +
  179. + SUNXI_CCU_GATE(F1C100S_CLK_BUS_DMA, "ahb-dma", "ahb",
  180. + BUS_CLK_GATING_REG0, 6);
  181. + SUNXI_CCU_GATE(F1C100S_CLK_BUS_MMC0, "ahb-mmc0", "ahb",
  182. + BUS_CLK_GATING_REG0, 8);
  183. + SUNXI_CCU_GATE(F1C100S_CLK_BUS_MMC1, "ahb-mmc1", "ahb",
  184. + BUS_CLK_GATING_REG0, 9);
  185. + SUNXI_CCU_GATE(F1C100S_CLK_BUS_DRAM, "ahb-dram", "ahb",
  186. + BUS_CLK_GATING_REG0, 14);
  187. + SUNXI_CCU_GATE(F1C100S_CLK_BUS_SPI0, "ahb-spi0", "ahb",
  188. + BUS_CLK_GATING_REG0, 20);
  189. + SUNXI_CCU_GATE(F1C100S_CLK_BUS_SPI1, "ahb-spi1", "ahb",
  190. + BUS_CLK_GATING_REG0, 21);
  191. + SUNXI_CCU_GATE(F1C100S_CLK_BUS_OTG, "ahb-otg", "ahb",
  192. + BUS_CLK_GATING_REG0, 24);
  193. +
  194. + SUNXI_CCU_GATE(F1C100S_CLK_BUS_VE, "ahb-ve", "ahb",
  195. + BUS_CLK_GATING_REG1, 0);
  196. + SUNXI_CCU_GATE(F1C100S_CLK_BUS_LCD, "ahb-lcd", "ahb",
  197. + BUS_CLK_GATING_REG1, 4);
  198. + SUNXI_CCU_GATE(F1C100S_CLK_BUS_DEINTERLACE, "ahb-deinterlace", "ahb",
  199. + BUS_CLK_GATING_REG1, 5);
  200. + SUNXI_CCU_GATE(F1C100S_CLK_BUS_CSI, "ahb-csi", "ahb",
  201. + BUS_CLK_GATING_REG1, 8);
  202. + SUNXI_CCU_GATE(F1C100S_CLK_BUS_TVD, "ahb-tvd", "ahb",
  203. + BUS_CLK_GATING_REG1, 9);
  204. + SUNXI_CCU_GATE(F1C100S_CLK_BUS_TVE, "ahb-tve", "ahb",
  205. + BUS_CLK_GATING_REG1, 10);
  206. + SUNXI_CCU_GATE(F1C100S_CLK_BUS_DE_BE, "ahb-de_be", "ahb",
  207. + BUS_CLK_GATING_REG1, 12);
  208. + SUNXI_CCU_GATE(F1C100S_CLK_BUS_DE_FE, "ahb-de_fe", "ahb",
  209. + BUS_CLK_GATING_REG1, 14);
  210. +
  211. + SUNXI_CCU_GATE(F1C100S_CLK_BUS_CODEC, "apb-codec", "apb",
  212. + BUS_CLK_GATING_REG2, 0);
  213. + SUNXI_CCU_GATE(F1C100S_CLK_BUS_SPDIF, "apb-spdif", "apb",
  214. + BUS_CLK_GATING_REG2, 1);
  215. + SUNXI_CCU_GATE(F1C100S_CLK_BUS_IR, "apb-ir", "apb",
  216. + BUS_CLK_GATING_REG2, 2);
  217. + SUNXI_CCU_GATE(F1C100S_CLK_BUS_RSB, "apb-rsb", "apb",
  218. + BUS_CLK_GATING_REG2, 3);
  219. + SUNXI_CCU_GATE(F1C100S_CLK_BUS_I2S0, "apb-i2s0", "apb",
  220. + BUS_CLK_GATING_REG2, 12);
  221. + SUNXI_CCU_GATE(F1C100S_CLK_BUS_I2C0, "apb-i2c0", "apb",
  222. + BUS_CLK_GATING_REG2, 16);
  223. + SUNXI_CCU_GATE(F1C100S_CLK_BUS_I2C1, "apb-i2c1", "apb",
  224. + BUS_CLK_GATING_REG2, 17);
  225. + SUNXI_CCU_GATE(F1C100S_CLK_BUS_I2C2, "apb-i2c2", "apb",
  226. + BUS_CLK_GATING_REG2, 18);
  227. + SUNXI_CCU_GATE(F1C100S_CLK_BUS_UART0, "apb-uart0", "apb",
  228. + BUS_CLK_GATING_REG2, 20);
  229. + SUNXI_CCU_GATE(F1C100S_CLK_BUS_UART1, "apb-uart1", "apb",
  230. + BUS_CLK_GATING_REG2, 21);
  231. + SUNXI_CCU_GATE(F1C100S_CLK_BUS_UART2, "apb-uart2", "apb",
  232. + BUS_CLK_GATING_REG2, 22);
  233. +
  234. + SUNXI_CCU_GATE(F1C100S_CLK_USB_PHY0, "usb-phy", "osc24m",
  235. + USBPHY_CLK_REG, 1);
  236. +
  237. + SUNXI_CCU_GATE(F1C100S_CLK_DRAM_VE, "dram-ve", "pll_ddr",
  238. + DRAM_GATING_REG, 0);
  239. + SUNXI_CCU_GATE(F1C100S_CLK_DRAM_CSI, "dram-csi", "pll_ddr",
  240. + DRAM_GATING_REG, 1);
  241. + SUNXI_CCU_GATE(F1C100S_CLK_DRAM_DEINTERLACE, "dram-deinterlace", "pll-ddr",
  242. + DRAM_GATING_REG, 2);
  243. + SUNXI_CCU_GATE(F1C100S_CLK_DRAM_TVD, "dram-tvd", "pll_ddr",
  244. + DRAM_GATING_REG, 3);
  245. + SUNXI_CCU_GATE(F1C100S_CLK_DRAM_DE_FE, "dram-de-fe", "pll_ddr",
  246. + DRAM_GATING_REG, 24);
  247. + SUNXI_CCU_GATE(F1C100S_CLK_DRAM_DE_BE, "dram-de-be", "pll_ddr",
  248. + DRAM_GATING_REG, 26);
  249. +
  250. + SUNXI_CCU_GATE(F1C100S_CLK_CODEC, "codec", "pll_audio",
  251. + DAUDIO_CLK_REG, 31);
  252. +};
  253. +
  254. +static int
  255. +suniv_f1c100s_ccu_match(device_t parent, cfdata_t cf, void *aux)
  256. +{
  257. + struct fdt_attach_args * const faa = aux;
  258. +
  259. + return of_match_compatible(faa->faa_phandle, compatible);
  260. +}
  261. +
  262. +static void
  263. +suniv_f1c100s_ccu_attach(device_t parent, device_t self, void *aux)
  264. +{
  265. + struct sunxi_ccu_softc * const sc = device_private(self);
  266. + struct fdt_attach_args * const faa = aux;
  267. +
  268. + sc->sc_dev = self;
  269. + sc->sc_phandle = faa->faa_phandle;
  270. + sc->sc_bst = faa->faa_bst;
  271. +
  272. + sc->sc_resets = suniv_f1c100s_ccu_resets;
  273. + sc->sc_nresets = __arraycount(suniv_f1c100s_ccu_resets);
  274. +
  275. + sc->sc_clks = suniv_f1c100s_ccu_clks;
  276. + sc->sc_nclks = __arraycount(suniv_f1c100s_ccu_clks);
  277. +
  278. + if (sunxi_ccu_attach(sc) != 0)
  279. + return;
  280. +
  281. + aprint_naive("\n");
  282. + aprint_normal(": F1C100s CCU\n");
  283. +
  284. + sunxi_ccu_print(sc);
  285. +}
  286. diff -uNpr sunxi.orig/suniv_f1c100s_ccu.h sunxi/suniv_f1c100s_ccu.h
  287. --- sunxi.orig/suniv_f1c100s_ccu.h 1970-01-01 09:00:00.000000000 +0900
  288. +++ sunxi/suniv_f1c100s_ccu.h 2020-01-02 07:55:33.254354111 +0900
  289. @@ -0,0 +1,115 @@
  290. +/* $NetBSD: suniv_f1c100s_ccu.h,v 1.1 2017/08/25 00:07:03 jmcneill Exp $ */
  291. +
  292. +/*-
  293. + * Copyright (c) 2017 Jared McNeill <[email protected]>
  294. + * All rights reserved.
  295. + *
  296. + * Redistribution and use in source and binary forms, with or without
  297. + * modification, are permitted provided that the following conditions
  298. + * are met:
  299. + * 1. Redistributions of source code must retain the above copyright
  300. + * notice, this list of conditions and the following disclaimer.
  301. + * 2. Redistributions in binary form must reproduce the above copyright
  302. + * notice, this list of conditions and the following disclaimer in the
  303. + * documentation and/or other materials provided with the distribution.
  304. + *
  305. + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  306. + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  307. + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  308. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  309. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  310. + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  311. + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  312. + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  313. + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  314. + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  315. + * SUCH DAMAGE.
  316. + */
  317. +
  318. +#ifndef _SUNIV_F1C100S_CCU_H
  319. +#define _SUNIV_F1C100S_CCU_H
  320. +
  321. +#define F1C100S_RST_USB_PHY0 0
  322. +#define F1C100S_RST_BUS_DMA 1
  323. +#define F1C100S_RST_BUS_MMC0 2
  324. +#define F1C100S_RST_BUS_MMC1 3
  325. +#define F1C100S_RST_BUS_DRAM 4
  326. +#define F1C100S_RST_BUS_SPI0 5
  327. +#define F1C100S_RST_BUS_SPI1 6
  328. +#define F1C100S_RST_BUS_OTG 7
  329. +#define F1C100S_RST_BUS_VE 8
  330. +#define F1C100S_RST_BUS_LCD 9
  331. +#define F1C100S_RST_BUS_DEINTERLACE 10
  332. +#define F1C100S_RST_BUS_CSI 11
  333. +#define F1C100S_RST_BUS_TVD 12
  334. +#define F1C100S_RST_BUS_TVE 13
  335. +#define F1C100S_RST_BUS_DE_BE 14
  336. +#define F1C100S_RST_BUS_DE_FE 15
  337. +#define F1C100S_RST_BUS_CODEC 16
  338. +#define F1C100S_RST_BUS_SPDIF 17
  339. +#define F1C100S_RST_BUS_IR 18
  340. +#define F1C100S_RST_BUS_RSB 19
  341. +#define F1C100S_RST_BUS_I2S0 20
  342. +#define F1C100S_RST_BUS_I2C0 21
  343. +#define F1C100S_RST_BUS_I2C1 22
  344. +#define F1C100S_RST_BUS_I2C2 23
  345. +#define F1C100S_RST_BUS_UART0 24
  346. +#define F1C100S_RST_BUS_UART1 25
  347. +#define F1C100S_RST_BUS_UART2 26
  348. +
  349. +#define F1C100S_CLK_CPU 11
  350. +#define F1C100S_CLK_BUS_DMA 14
  351. +#define F1C100S_CLK_BUS_MMC0 15
  352. +#define F1C100S_CLK_BUS_MMC1 16
  353. +#define F1C100S_CLK_BUS_DRAM 17
  354. +#define F1C100S_CLK_BUS_SPI0 18
  355. +#define F1C100S_CLK_BUS_SPI1 19
  356. +#define F1C100S_CLK_BUS_OTG 20
  357. +#define F1C100S_CLK_BUS_VE 21
  358. +#define F1C100S_CLK_BUS_LCD 22
  359. +#define F1C100S_CLK_BUS_DEINTERLACE 23
  360. +#define F1C100S_CLK_BUS_CSI 24
  361. +#define F1C100S_CLK_BUS_TVD 25
  362. +#define F1C100S_CLK_BUS_TVE 26
  363. +#define F1C100S_CLK_BUS_DE_BE 27
  364. +#define F1C100S_CLK_BUS_DE_FE 28
  365. +#define F1C100S_CLK_BUS_CODEC 29
  366. +#define F1C100S_CLK_BUS_SPDIF 30
  367. +#define F1C100S_CLK_BUS_IR 31
  368. +#define F1C100S_CLK_BUS_RSB 32
  369. +#define F1C100S_CLK_BUS_I2S0 33
  370. +#define F1C100S_CLK_BUS_I2C0 34
  371. +#define F1C100S_CLK_BUS_I2C1 35
  372. +#define F1C100S_CLK_BUS_I2C2 36
  373. +#define F1C100S_CLK_BUS_PIO 37
  374. +#define F1C100S_CLK_BUS_UART0 38
  375. +#define F1C100S_CLK_BUS_UART1 39
  376. +#define F1C100S_CLK_BUS_UART2 40
  377. +#define F1C100S_CLK_MMC0 41
  378. +#define F1C100S_CLK_MMC0_SAMPLE 42
  379. +#define F1C100S_CLK_MMC0_OUTPUT 43
  380. +#define F1C100S_CLK_MMC1 44
  381. +#define F1C100S_CLK_MMC1_SAMPLE 45
  382. +#define F1C100S_CLK_MMC1_OUTPUT 46
  383. +#define F1C100S_CLK_I2S 47
  384. +#define F1C100S_CLK_SPDIF 48
  385. +#define F1C100S_CLK_USB_PHY0 49
  386. +#define F1C100S_CLK_DRAM_VE 50
  387. +#define F1C100S_CLK_DRAM_CSI 51
  388. +#define F1C100S_CLK_DRAM_DEINTERLACE 52
  389. +#define F1C100S_CLK_DRAM_TVD 53
  390. +#define F1C100S_CLK_DRAM_DE_FE 54
  391. +#define F1C100S_CLK_DRAM_DE_BE 55
  392. +#define F1C100S_CLK_DE_BE 56
  393. +#define F1C100S_CLK_DE_FE 57
  394. +#define F1C100S_CLK_TCON 58
  395. +#define F1C100S_CLK_DEINTERLACE 59
  396. +#define F1C100S_CLK_TVE2_CLK 60
  397. +#define F1C100S_CLK_TVE1_CLK 61
  398. +#define F1C100S_CLK_TVD 62
  399. +#define F1C100S_CLK_CSI 63
  400. +#define F1C100S_CLK_VE 64
  401. +#define F1C100S_CLK_CODEC 65
  402. +#define F1C100S_CLK_AVS 66
  403. +
  404. +#endif /* !_SUNIV_F1C100S_CCU_H */
  405. diff -uNpr sunxi.orig/suniv_f1c100s_gpio.c sunxi/suniv_f1c100s_gpio.c
  406. --- sunxi.orig/suniv_f1c100s_gpio.c 1970-01-01 09:00:00.000000000 +0900
  407. +++ sunxi/suniv_f1c100s_gpio.c 2020-01-02 06:25:14.982772662 +0900
  408. @@ -0,0 +1,101 @@
  409. +/* $NetBSD: suniv_f1c100s_gpio.c,v 1.4 2018/04/03 16:01:25 bouyer Exp $ */
  410. +
  411. +/*-
  412. + * Copyright (c) 2016 Emmanuel Vadot <[email protected]>
  413. + * All rights reserved.
  414. + *
  415. + * Redistribution and use in source and binary forms, with or without
  416. + * modification, are permitted provided that the following conditions
  417. + * are met:
  418. + * 1. Redistributions of source code must retain the above copyright
  419. + * notice, this list of conditions and the following disclaimer.
  420. + * 2. Redistributions in binary form must reproduce the above copyright
  421. + * notice, this list of conditions and the following disclaimer in the
  422. + * documentation and/or other materials provided with the distribution.
  423. + *
  424. + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  425. + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  426. + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  427. + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  428. + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  429. + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  430. + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  431. + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  432. + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  433. + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  434. + * SUCH DAMAGE.
  435. + *
  436. + */
  437. +
  438. +#include <sys/cdefs.h>
  439. +__KERNEL_RCSID(0, "$NetBSD: suniv_f1c100s_gpio.c,v 1.4 2018/04/03 16:01:25 bouyer Exp $");
  440. +
  441. +#include <sys/param.h>
  442. +#include <sys/systm.h>
  443. +#include <sys/kernel.h>
  444. +#include <sys/types.h>
  445. +
  446. +#include <arm/sunxi/sunxi_gpio.h>
  447. +
  448. +static const struct sunxi_gpio_pins f1c100s_pins[] = {
  449. + {"PA0", 0, 0, {"gpio_in", "gpio_out", "tp", NULL, "i2s", "uart1", "spi1"}},
  450. + {"PA1", 0, 1, {"gpio_in", "gpio_out", "tp", NULL, "i2s", "uart1", "spi1"}},
  451. + {"PA2", 0, 2, {"gpio_in", "gpio_out", "tp", "pwm0", "i2s", "uart1", "spi1"}},
  452. + {"PA3", 0, 3, {"gpio_in", "gpio_out", "tp", "ir", "i2s", "uart1", "spi1"}},
  453. +
  454. + {"PB3", 1, 3, {"gpio_in", "gpio_out", "ddr", "ir"}},
  455. +
  456. + {"PC0", 2, 0, {"gpio_in", "gpio_out", "spi0", "mmc1"}},
  457. + {"PC1", 2, 1, {"gpio_in", "gpio_out", "spi0", "mmc1"}},
  458. + {"PC2", 2, 2, {"gpio_in", "gpio_out", "spi0", "mmc1"}},
  459. + {"PC3", 2, 3, {"gpio_in", "gpio_out", "spi0", "uart0"}},
  460. +
  461. + {"PD0", 3, 0, {"gpio_in", "gpio_out", "lcd", "twi0", "rsb", NULL, "irq"}, 6, 0},
  462. + {"PD1", 3, 1, {"gpio_in", "gpio_out", "lcd", "uart1", NULL, NULL, "irq"}, 6, 1},
  463. + {"PD2", 3, 2, {"gpio_in", "gpio_out", "lcd", "uart1", NULL, NULL, "irq"}, 6, 2},
  464. + {"PD3", 3, 3, {"gpio_in", "gpio_out", "lcd", "uart1", NULL, NULL, "irq"}, 6, 3},
  465. + {"PD4", 3, 4, {"gpio_in", "gpio_out", "lcd", "uart1", NULL, NULL, "irq"}, 6, 4},
  466. + {"PD5", 3, 5, {"gpio_in", "gpio_out", "lcd", "twi1", NULL, NULL, "irq"}, 6, 5},
  467. + {"PD6", 3, 6, {"gpio_in", "gpio_out", "lcd", "twi1", NULL, NULL, "irq"}, 6, 6},
  468. + {"PD7", 3, 7, {"gpio_in", "gpio_out", "lcd", "i2s", NULL, NULL, "irq"}, 6, 7},
  469. + {"PD8", 3, 8, {"gpio_in", "gpio_out", "lcd", "i2s", NULL, NULL, "irq"}, 6, 8},
  470. + {"PD9", 3, 9, {"gpio_in", "gpio_out", "lcd", "i2s", NULL, NULL, "irq"}, 6, 9},
  471. + {"PD10", 3, 10, {"gpio_in", "gpio_out", "lcd", "i2s", NULL, NULL, "irq"}, 6, 10},
  472. + {"PD11", 3, 11, {"gpio_in", "gpio_out", "lcd", "i2s", NULL, NULL, "irq"}, 6, 11},
  473. + {"PD12", 3, 12, {"gpio_in", "gpio_out", "lcd", "twi0", "rsb", NULL, "irq"}, 6, 12},
  474. + {"PD13", 3, 13, {"gpio_in", "gpio_out", "lcd", "uart2", NULL, NULL, "irq"}, 6, 13},
  475. + {"PD14", 3, 14, {"gpio_in", "gpio_out", "lcd", "uart2", NULL, NULL, "irq"}, 6, 14},
  476. + {"PD15", 3, 15, {"gpio_in", "gpio_out", "lcd", "uart2", "twi2", NULL, "irq"}, 6, 15},
  477. + {"PD16", 3, 16, {"gpio_in", "gpio_out", "lcd", "uart2", "twi2", NULL, "irq"}, 6, 16},
  478. + {"PD17", 3, 17, {"gpio_in", "gpio_out", "lcd", "owa", NULL, NULL, "irq"}, 6, 17},
  479. + {"PD18", 3, 18, {"gpio_in", "gpio_out", "lcd", "spi0", NULL, NULL, "irq"}, 6, 18},
  480. + {"PD19", 3, 19, {"gpio_in", "gpio_out", "lcd", "spi0", NULL, NULL, "irq"}, 6, 19},
  481. + {"PD20", 3, 20, {"gpio_in", "gpio_out", "lcd", "spi0", NULL, NULL, "irq"}, 6, 20},
  482. + {"PD21", 3, 21, {"gpio_in", "gpio_out", "lcd", "spi0", NULL, NULL, "irq"}, 6, 21},
  483. +
  484. + {"PE0", 4, 0, {"gpio_in", "gpio_out", "csi", "lcd", "twi2", "uart0", "irq"}, 6, 0},
  485. + {"PE1", 4, 1, {"gpio_in", "gpio_out", "csi", "lcd", "twi2", "uart0", "irq"}, 6, 1},
  486. + {"PE2", 4, 2, {"gpio_in", "gpio_out", "csi", "lcd", "clk_out", NULL, "irq"}, 6, 2},
  487. + {"PE3", 4, 3, {"gpio_in", "gpio_out", "csi", "lcd", "i2s", "rsb", "irq"}, 6, 3},
  488. + {"PE4", 4, 4, {"gpio_in", "gpio_out", "csi", "lcd", "i2s", "rsb", "irq"}, 6, 4},
  489. + {"PE5", 4, 5, {"gpio_in", "gpio_out", "csi", "lcd", "i2s", NULL, "irq"}, 6, 5},
  490. + {"PE6", 4, 6, {"gpio_in", "gpio_out", "csi", "pwm1", "i2s", "owa", "irq"}, 6, 6},
  491. + {"PE7", 4, 7, {"gpio_in", "gpio_out", "csi", "uart2", "spi1", NULL, "irq"}, 6, 7},
  492. + {"PE8", 4, 8, {"gpio_in", "gpio_out", "csi", "uart2", "spi1", NULL, "irq"}, 6, 8},
  493. + {"PE9", 4, 9, {"gpio_in", "gpio_out", "csi", "uart2", "spi1", NULL, "irq"}, 6, 9},
  494. + {"PE10", 4, 10, {"gpio_in", "gpio_out", "csi", "uart2", "spi1", NULL, "irq"}, 6, 10},
  495. + {"PE11", 4, 11, {"gpio_in", "gpio_out", "clk_out", "twi0", "ir", NULL, "irq"}, 6, 11},
  496. + {"PE12", 4, 12, {"gpio_in", "gpio_out", "i2s", "twi0", "pwm0", NULL, "irq"}, 6, 12},
  497. +
  498. + {"PF0", 5, 0, {"gpio_in", "gpio_out", "mmc0", "jtag", "ir", NULL, "irq"}, 6, 0},
  499. + {"PF1", 5, 1, {"gpio_in", "gpio_out", "mmc0", "jtag", NULL, NULL, "irq"}, 6, 1},
  500. + {"PF2", 5, 2, {"gpio_in", "gpio_out", "mmc0", "uart0", NULL, NULL, "irq"}, 6, 2},
  501. + {"PF3", 5, 3, {"gpio_in", "gpio_out", "mmc0", "jtag", NULL, NULL, "irq"}, 6, 3},
  502. + {"PF4", 5, 4, {"gpio_in", "gpio_out", "mmc0", "uart0", NULL, NULL, "irq"}, 6, 4},
  503. + {"PF5", 5, 5, {"gpio_in", "gpio_out", "mmc0", "jtag", "pwm1", NULL, "irq"}, 6, 5},
  504. +};
  505. +
  506. +const struct sunxi_gpio_padconf suniv_f1c100s_padconf = {
  507. + .npins = __arraycount(f1c100s_pins),
  508. + .pins = f1c100s_pins,
  509. +};
  510. diff -uNpr sunxi.orig/sunxi_gpio.c sunxi/sunxi_gpio.c
  511. --- sunxi.orig/sunxi_gpio.c 2019-10-02 12:02:11.000000000 +0900
  512. +++ sunxi/sunxi_gpio.c 2020-01-02 06:24:53.495296344 +0900
  513. @@ -117,6 +117,9 @@ static const struct of_compat_data compa
  514. { "allwinner,sun50i-h6-pinctrl", (uintptr_t)&sun50i_h6_padconf },
  515. { "allwinner,sun50i-h6-r-pinctrl", (uintptr_t)&sun50i_h6_r_padconf },
  516. #endif
  517. +#ifdef SOC_SUNIV_F1C100S
  518. + { "allwinner,suniv-f1c100s-pinctrl", (uintptr_t)&suniv_f1c100s_padconf },
  519. +#endif
  520. { NULL }
  521. };
  522.  
  523. diff -uNpr sunxi.orig/sunxi_intc.c sunxi/sunxi_intc.c
  524. --- sunxi.orig/sunxi_intc.c 2017-10-25 12:01:15.000000000 +0900
  525. +++ sunxi/sunxi_intc.c 2020-01-02 06:25:00.230385161 +0900
  526. @@ -44,26 +44,53 @@ __KERNEL_RCSID(0, "$NetBSD: sunxi_intc.c
  527. #include <arm/pic/picvar.h>
  528. #include <arm/fdt/arm_fdtvar.h>
  529.  
  530. -#define INTC_MAX_SOURCES 96
  531. -#define INTC_MAX_GROUPS 3
  532. +#define SUNXI_INTC_MAX_SOURCES 96
  533. +#define SUNXI_INTC_MAX_GROUPS 3
  534.  
  535. -#define INTC_VECTOR_REG 0x00
  536. -#define INTC_BASE_ADDR_REG 0x04
  537. -#define INTC_PROTECT_REG 0x08
  538. -#define INTC_PROTECT_EN __BIT(0)
  539. -#define INTC_NMII_CTRL_REG 0x0c
  540. -#define INTC_IRQ_PEND_REG(n) (0x10 + ((n) * 4))
  541. -#define INTC_FIQ_PEND_REG(n) (0x20 + ((n) * 4))
  542. -#define INTC_SEL_REG(n) (0x30 + ((n) * 4))
  543. -#define INTC_EN_REG(n) (0x40 + ((n) * 4))
  544. -#define INTC_MASK_REG(n) (0x50 + ((n) * 4))
  545. -#define INTC_RESP_REG(n) (0x60 + ((n) * 4))
  546. -#define INTC_FORCE_REG(n) (0x70 + ((n) * 4))
  547. -#define INTC_SRC_PRIO_REG(n) (0x80 + ((n) * 4))
  548. -
  549. -static const char * const compatible[] = {
  550. - "allwinner,sun4i-a10-ic",
  551. - NULL
  552. +#define SUNIV_INTC_MAX_SOURCES 64
  553. +#define SUNIV_INTC_MAX_GROUPS 2
  554. +
  555. +#define INTC_MAX_SOURCES(sc) ((sc)->sc_conf->max_sources)
  556. +#define INTC_MAX_GROUPS(sc) ((sc)->sc_conf->max_groups)
  557. +
  558. +#define INTC_VECTOR_REG 0x00
  559. +#define INTC_BASE_ADDR_REG 0x04
  560. +#define INTC_PROTECT_REG(sc) ((sc)->sc_conf->protect_reg_offset)
  561. +#define INTC_PROTECT_EN __BIT(0)
  562. +#define INTC_IRQ_PEND_REG(n) (0x10 + ((n) * 4))
  563. +#define INTC_EN_REG(sc, n) \
  564. + ((sc)->sc_conf->en_reg_offset + ((n) * 4))
  565. +#define INTC_MASK_REG(sc, n) \
  566. + ((sc)->sc_conf->mask_reg_offset + ((n) * 4))
  567. +
  568. +struct sunxi_intc_config {
  569. + int max_sources;
  570. + int max_groups;
  571. + int protect_reg_offset;
  572. + int en_reg_offset;
  573. + int mask_reg_offset;
  574. +};
  575. +
  576. +static const struct sunxi_intc_config sun4i_a10_ic_config = {
  577. + .max_sources = SUNXI_INTC_MAX_SOURCES,
  578. + .max_groups = SUNXI_INTC_MAX_GROUPS,
  579. + .protect_reg_offset = 0x08,
  580. + .en_reg_offset = 0x40,
  581. + .mask_reg_offset = 0x50,
  582. +};
  583. +
  584. +static const struct sunxi_intc_config suniv_ic_config = {
  585. + .max_sources = SUNIV_INTC_MAX_SOURCES,
  586. + .max_groups = SUNIV_INTC_MAX_GROUPS,
  587. + .protect_reg_offset = 0, /* no PROTECT_REG */
  588. + .en_reg_offset = 0x20,
  589. + .mask_reg_offset = 0x30,
  590. +};
  591. +
  592. +static const struct of_compat_data compat_data[] = {
  593. + { "allwinner,sun4i-a10-ic", (uintptr_t)&sun4i_a10_ic_config },
  594. + { "allwinner,suniv-ic", (uintptr_t)&suniv_ic_config },
  595. + { NULL }
  596. };
  597.  
  598. struct sunxi_intc_softc {
  599. @@ -72,7 +99,9 @@ struct sunxi_intc_softc {
  600. bus_space_handle_t sc_bsh;
  601. int sc_phandle;
  602.  
  603. - uint32_t sc_enabled_irqs[INTC_MAX_GROUPS];
  604. + const struct sunxi_intc_config *sc_conf;
  605. +
  606. + uint32_t sc_enabled_irqs[SUNXI_INTC_MAX_GROUPS];
  607.  
  608. struct pic_softc sc_pic;
  609. };
  610. @@ -95,8 +124,8 @@ sunxi_intc_unblock_irqs(struct pic_softc
  611.  
  612. KASSERT((mask & sc->sc_enabled_irqs[group]) == 0);
  613. sc->sc_enabled_irqs[group] |= mask;
  614. - INTC_WRITE(sc, INTC_EN_REG(group), sc->sc_enabled_irqs[group]);
  615. - INTC_WRITE(sc, INTC_MASK_REG(group), ~sc->sc_enabled_irqs[group]);
  616. + INTC_WRITE(sc, INTC_EN_REG(sc, group), sc->sc_enabled_irqs[group]);
  617. + INTC_WRITE(sc, INTC_MASK_REG(sc, group), ~sc->sc_enabled_irqs[group]);
  618. }
  619.  
  620. static void
  621. @@ -106,14 +135,16 @@ sunxi_intc_block_irqs(struct pic_softc *
  622. const u_int group = irqbase / 32;
  623.  
  624. sc->sc_enabled_irqs[group] &= ~mask;
  625. - INTC_WRITE(sc, INTC_EN_REG(group), sc->sc_enabled_irqs[group]);
  626. - INTC_WRITE(sc, INTC_MASK_REG(group), ~sc->sc_enabled_irqs[group]);
  627. + INTC_WRITE(sc, INTC_EN_REG(sc, group), sc->sc_enabled_irqs[group]);
  628. + INTC_WRITE(sc, INTC_MASK_REG(sc, group), ~sc->sc_enabled_irqs[group]);
  629. }
  630.  
  631. static void
  632. sunxi_intc_establish_irq(struct pic_softc *pic, struct intrsource *is)
  633. {
  634. - KASSERT(is->is_irq < INTC_MAX_SOURCES);
  635. + struct sunxi_intc_softc * const sc = PICTOSOFTC(pic);
  636. +
  637. + KASSERT(is->is_irq < INTC_MAX_SOURCES(sc));
  638. KASSERT(is->is_type == IST_LEVEL);
  639. }
  640.  
  641. @@ -133,10 +164,12 @@ static void *
  642. sunxi_intc_fdt_establish(device_t dev, u_int *specifier, int ipl, int flags,
  643. int (*func)(void *), void *arg)
  644. {
  645. + struct sunxi_intc_softc * const sc = device_private(dev);
  646. +
  647. /* 1st cell is the interrupt number */
  648. const u_int irq = be32toh(specifier[0]);
  649.  
  650. - if (irq >= INTC_MAX_SOURCES) {
  651. + if (irq >= INTC_MAX_SOURCES(sc)) {
  652. #ifdef DIAGNOSTIC
  653. device_printf(dev, "IRQ %u is invalid\n", irq);
  654. #endif
  655. @@ -196,16 +229,14 @@ sunxi_intc_irq_handler(void *frame)
  656. struct sunxi_intc_softc * const sc = intc_softc;
  657. const int oldipl = ci->ci_cpl;
  658. const uint32_t oldipl_mask = __BIT(oldipl);
  659. - int ipl_mask = 0;
  660. + int i, ipl_mask = 0;
  661.  
  662. ci->ci_data.cpu_nintr++;
  663.  
  664. - if (sc->sc_enabled_irqs[0])
  665. - ipl_mask |= sunxi_intc_find_pending_irqs(sc, 0);
  666. - if (sc->sc_enabled_irqs[1])
  667. - ipl_mask |= sunxi_intc_find_pending_irqs(sc, 1);
  668. - if (sc->sc_enabled_irqs[2])
  669. - ipl_mask |= sunxi_intc_find_pending_irqs(sc, 2);
  670. + for (i = 0; i < INTC_MAX_GROUPS(sc); i++) {
  671. + if (sc->sc_enabled_irqs[i])
  672. + ipl_mask |= sunxi_intc_find_pending_irqs(sc, i);
  673. + }
  674.  
  675. if ((ipl_mask & ~oldipl_mask) > oldipl_mask)
  676. pic_do_pending_ints(I32_bit, oldipl, frame);
  677. @@ -216,7 +247,7 @@ sunxi_intc_match(device_t parent, cfdata
  678. {
  679. struct fdt_attach_args * const faa = aux;
  680.  
  681. - return of_match_compatible(faa->faa_phandle, compatible);
  682. + return of_match_compat_data(faa->faa_phandle, compat_data);
  683. }
  684.  
  685. static void
  686. @@ -241,22 +272,24 @@ sunxi_intc_attach(device_t parent, devic
  687. aprint_error(": couldn't map registers\n");
  688. return;
  689. }
  690. + sc->sc_conf = (void *)of_search_compatible(phandle, compat_data)->data;
  691.  
  692. aprint_naive("\n");
  693. aprint_normal(": Interrupt Controller\n");
  694.  
  695. /* Disable IRQs */
  696. - for (i = 0; i < INTC_MAX_GROUPS; i++) {
  697. - INTC_WRITE(sc, INTC_EN_REG(i), 0);
  698. - INTC_WRITE(sc, INTC_MASK_REG(i), ~0U);
  699. + for (i = 0; i < INTC_MAX_GROUPS(sc); i++) {
  700. + INTC_WRITE(sc, INTC_EN_REG(sc, i), 0);
  701. + INTC_WRITE(sc, INTC_MASK_REG(sc, i), ~0U);
  702. INTC_WRITE(sc, INTC_IRQ_PEND_REG(i),
  703. INTC_READ(sc, INTC_IRQ_PEND_REG(i)));
  704. }
  705. /* Disable user mode access to intc registers */
  706. - INTC_WRITE(sc, INTC_PROTECT_REG, INTC_PROTECT_EN);
  707. + if (INTC_PROTECT_REG(sc))
  708. + INTC_WRITE(sc, INTC_PROTECT_REG(sc), INTC_PROTECT_EN);
  709.  
  710. sc->sc_pic.pic_ops = &sunxi_intc_picops;
  711. - sc->sc_pic.pic_maxsources = INTC_MAX_SOURCES;
  712. + sc->sc_pic.pic_maxsources = INTC_MAX_SOURCES(sc);
  713. snprintf(sc->sc_pic.pic_name, sizeof(sc->sc_pic.pic_name), "intc");
  714. pic_add(&sc->sc_pic, 0);
  715.  
  716. diff -uNpr sunxi.orig/sunxi_timer.c sunxi/sunxi_timer.c
  717. --- sunxi.orig/sunxi_timer.c 2019-06-15 12:01:42.000000000 +0900
  718. +++ sunxi/sunxi_timer.c 2020-01-02 06:25:04.595255627 +0900
  719. @@ -91,9 +91,11 @@ __KERNEL_RCSID(0, "$NetBSD: sunxi_timer.
  720. #define LOSC_CTRL_OSC32K_AUTO_SWT_EN __BIT(14)
  721. #define LOSC_CTRL_OSC32K_SEL __BIT(0)
  722.  
  723. -static const char * const compatible[] = {
  724. - "allwinner,sun4i-a10-timer",
  725. - NULL
  726. +static const struct of_compat_data compat_data[] = {
  727. + { "allwinner,sun4i-a10-timer", 6 },
  728. + { "allwinner,sun8i-v3s-timer", 3 },
  729. + { "allwinner,suniv-f1c100s-timer", 3 },
  730. + { NULL }
  731. };
  732.  
  733. struct sunxi_timer_softc {
  734. @@ -103,6 +105,8 @@ struct sunxi_timer_softc {
  735. int sc_phandle;
  736. struct clk *sc_clk;
  737.  
  738. + int sc_ntimers;
  739. +
  740. struct timecounter sc_tc;
  741. struct timecounter sc_tc_losc;
  742. };
  743. @@ -178,7 +182,7 @@ sunxi_timer_match(device_t parent, cfdat
  744. {
  745. struct fdt_attach_args * const faa = aux;
  746.  
  747. - return of_match_compatible(faa->faa_phandle, compatible);
  748. + return of_match_compat_data(faa->faa_phandle, compat_data);
  749. }
  750.  
  751. static void
  752. @@ -211,6 +215,7 @@ sunxi_timer_attach(device_t parent, devi
  753. aprint_error(": couldn't map registers\n");
  754. return;
  755. }
  756. + sc->sc_ntimers = of_search_compatible(phandle, compat_data)->data;
  757.  
  758. aprint_naive("\n");
  759. aprint_normal(": Timer\n");
  760. @@ -230,9 +235,6 @@ sunxi_timer_attach(device_t parent, devi
  761. TIMER_WRITE(sc, TMR2_CTRL_REG,
  762. __SHIFTIN(TMR2_CTRL_CLK_SRC_OSC24M, TMR2_CTRL_CLK_SRC) |
  763. TMR2_CTRL_RELOAD | TMR2_CTRL_EN);
  764. - /* Enable Timer 4 (timecounter for LOSC) */
  765. - TIMER_WRITE(sc, TMR4_INTV_VALUE_REG, ~0u);
  766. - TIMER_WRITE(sc, TMR4_CTRL_REG, TMR4_CTRL_RELOAD | TMR4_CTRL_EN);
  767.  
  768. /* Timecounter setup */
  769. tc->tc_get_timecount = sunxi_timer_get_timecount;
  770. @@ -242,26 +244,31 @@ sunxi_timer_attach(device_t parent, devi
  771. tc->tc_quality = 200;
  772. tc->tc_priv = sc;
  773. tc_init(tc);
  774. - tc_losc->tc_get_timecount = sunxi_timer_get_timecount_losc;
  775. - tc_losc->tc_counter_mask = ~0u;
  776. - tc_losc->tc_frequency = 32768;
  777. - tc_losc->tc_name = "LOSC";
  778. - tc_losc->tc_quality = 150;
  779. - tc_losc->tc_priv = sc;
  780. - /*
  781. - * LOSC is optional to implement in hardware.
  782. - * Make sure it ticks before registering it.
  783. - */
  784. - reg = __SHIFTIN(LOSC_CTRL_KEY_FIELD_V, LOSC_CTRL_KEY_FIELD) |
  785. - LOSC_CTRL_OSC32K_AUTO_SWT_EN |
  786. - LOSC_CTRL_OSC32K_SEL;
  787. - TIMER_WRITE(sc, LOSC_CTRL_REG, reg);
  788. - ticks = sunxi_timer_get_timecount_losc(tc_losc);
  789. - delay(100);
  790. - if (ticks != sunxi_timer_get_timecount_losc(tc_losc))
  791. - tc_init(tc_losc);
  792. - else
  793. - TIMER_WRITE(sc, LOSC_CTRL_REG, reg & ~LOSC_CTRL_OSC32K_SEL);
  794. +
  795. + /* Timer 4 (timecounter for LOSC) is optional */
  796. + if (sc->sc_ntimers > 3) {
  797. + tc_losc->tc_get_timecount = sunxi_timer_get_timecount_losc;
  798. + tc_losc->tc_counter_mask = ~0u;
  799. + tc_losc->tc_frequency = 32768;
  800. + tc_losc->tc_name = "LOSC";
  801. + tc_losc->tc_quality = 150;
  802. + tc_losc->tc_priv = sc;
  803. +
  804. + /* Make sure it ticks before registering it. */
  805. + TIMER_WRITE(sc, TMR4_INTV_VALUE_REG, ~0u);
  806. + TIMER_WRITE(sc, TMR4_CTRL_REG, TMR4_CTRL_RELOAD | TMR4_CTRL_EN);
  807. + reg = __SHIFTIN(LOSC_CTRL_KEY_FIELD_V, LOSC_CTRL_KEY_FIELD) |
  808. + LOSC_CTRL_OSC32K_AUTO_SWT_EN |
  809. + LOSC_CTRL_OSC32K_SEL;
  810. + TIMER_WRITE(sc, LOSC_CTRL_REG, reg);
  811. + ticks = sunxi_timer_get_timecount_losc(tc_losc);
  812. + delay(100);
  813. + if (ticks != sunxi_timer_get_timecount_losc(tc_losc))
  814. + tc_init(tc_losc);
  815. + else
  816. + TIMER_WRITE(sc, LOSC_CTRL_REG,
  817. + reg & ~LOSC_CTRL_OSC32K_SEL);
  818. + }
  819.  
  820. /* Use this as the OS timer in UP configurations */
  821. if (!arm_has_mpext_p) {
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