// Generator : SpinalHDL v1.6.4    git head : 598c18959149eb18e5eee5b0aa3eef01ecaa41a1
// Component : Playground
// Git hash  : 29349219b196ff75f1ad04e2876db9c95bc17b55

`timescale 1ns/1ps

module Playground (
  input               clk_26,
  input               gba_but_l,
  output              backlight
);

  wire                pll_PLLOUTGLOBAL;
  wire                pll_LOCK;
  wire                bufferCC_1_io_dataOut;
  wire                core_clk;
  wire                core_reset;
  wire                _zz_1;
  reg                 gba_but_l_regNext;

  SB_PLL40_CORE #(
    .FEEDBACK_PATH("SIMPLE"),
    .PLLOUT_SELECT("GENCLK"),
    .DIVR(1),
    .DIVF(76),
    .DIVQ(5),
    .FILTER_RANGE(1)
  ) pll (
    .REFERENCECLK    (clk_26            ), //i
    .PLLOUTGLOBAL    (pll_PLLOUTGLOBAL  ), //o
    .LOCK            (pll_LOCK          ), //o
    .RESETB          (1'b1              )  //i
  );
  BufferCC bufferCC_1 (
    .io_dataIn     (1'b0                   ), //i
    .io_dataOut    (bufferCC_1_io_dataOut  ), //o
    .core_clk      (core_clk               ), //i
    ._zz_1         (_zz_1                  )  //i
  );
  assign core_clk = pll_PLLOUTGLOBAL;
  assign _zz_1 = (! pll_LOCK);
  assign core_reset = bufferCC_1_io_dataOut;
  assign backlight = gba_but_l_regNext;
  always @(posedge core_clk) begin
    gba_but_l_regNext <= gba_but_l;
  end


endmodule

module BufferCC (
  input               io_dataIn,
  output              io_dataOut,
  input               core_clk,
  input               _zz_1
);

  (* async_reg = "true" *) reg                 buffers_0;
  (* async_reg = "true" *) reg                 buffers_1;

  assign io_dataOut = buffers_1;
  always @(posedge core_clk or posedge _zz_1) begin
    if(_zz_1) begin
      buffers_0 <= 1'b1;
      buffers_1 <= 1'b1;
    end else begin
      buffers_0 <= io_dataIn;
      buffers_1 <= buffers_0;
    end
  end


endmodule