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  1. U-Boot SPL 2024.01_armbian-2024.01-S0913-P7738-Ha5c2-Vb198-B1a8f-R448a (Jan 14 2026 - 08:02:11 +0000)
  2. MBUS port 0 cfg0 0200000d cfg1 00800100
  3. MBUS port 1 cfg0 06000009 cfg1 01000400
  4. MBUS port 2 cfg0 0200000d cfg1 00600100
  5. MBUS port 3 cfg0 0100000d cfg1 00200080
  6. MBUS port 4 cfg0 07000009 cfg1 01000640
  7. MBUS port 5 cfg0 0100000d cfg1 00200080
  8. MBUS port 6 cfg0 01000009 cfg1 00400080
  9. MBUS port 7 cfg0 0100000d cfg1 00400080
  10. MBUS port 8 cfg0 0100000d cfg1 00400080
  11. MBUS port 9 cfg0 04000009 cfg1 00400100
  12. MBUS port 10 cfg0 2000030d cfg1 040017e8
  13. MBUS port 11 cfg0 04000009 cfg1 00400120
  14. DRAM: 512 MiB
  15. SPL malloc() before relocation used 0x0 bytes (0 KB)
  16. >>SPL: board_init_r()
  17. Trying to boot from MMC1
  18. init mmc 0 resource
  19. init mmc 0 clock and io
  20. mmc 0 set mod-clk req 24000000 parent 24000000 n 1 m 1 rate 24000000
  21. clock is disabled (0Hz)
  22. set ios: bus_width: 0, clock: 0
  23. set ios: bus_width: 1, clock: 0
  24. clock is enabled (400000Hz)
  25. set ios: bus_width: 1, clock: 400000
  26. mmc 0 set mod-clk req 400000 parent 24000000 n 4 m 15 rate 400000
  27. mmc 0, cmd 0(0x80008000), arg 0x00000000
  28. mmc resp 0x00000000
  29. mmc 0, cmd 8(0x80000148), arg 0x000001aa
  30. mmc resp 0x000001aa
  31. mmc 0, cmd 55(0x80000177), arg 0x00000000
  32. mmc resp 0x00000120
  33. mmc 0, cmd 41(0x80000069), arg 0x40300000
  34. mmc resp 0xc0ff8000
  35. mmc 0, cmd 2(0x800001c2), arg 0x00000000
  36. mmc resp 0x8800aa39 0x30888888 0x50505344 0x00000041
  37. mmc 0, cmd 3(0x80000143), arg 0x00000000
  38. mmc resp 0x02150500
  39. mmc 0, cmd 9(0x800001c9), arg 0x02150000
  40. mmc resp 0x0a400083 0xff9fc01f 0x53590000 0x400e0032
  41. mmc 0, cmd 7(0x80000147), arg 0x02150000
  42. mmc resp 0x00000700
  43. mmc 0, cmd 55(0x80000177), arg 0x02150000
  44. mmc resp 0x00000920
  45. mmc 0, cmd 51(0x80002373), arg 0x00000000
  46. trans data 8 bytes
  47. cacl timeout 78 msec
  48. mmc resp 0x00000920
  49. mmc 0, cmd 6(0x80002346), arg 0x00fffff1
  50. trans data 64 bytes
  51. cacl timeout 78 msec
  52. mmc resp 0x00000900
  53. mmc 0, cmd 55(0x80000177), arg 0x02150000
  54. mmc resp 0x00000920
  55. mmc 0, cmd 6(0x80000146), arg 0x00000002
  56. mmc resp 0x00000920
  57. set ios: bus_width: 4, clock: 400000
  58. mmc 0 set mod-clk req 400000 parent 24000000 n 4 m 15 rate 400000
  59. mmc 0, cmd 6(0x80002346), arg 0x80fffff1
  60. trans data 64 bytes
  61. cacl timeout 78 msec
  62. data timeout 80
  63. clock is enabled (25000000Hz)
  64. set ios: bus_width: 4, clock: 25000000
  65. mmc 0 set mod-clk req 25000000 parent 600000000 n 2 m 12 rate 25000000
  66. mmc 0, cmd 55(0x80000177), arg 0x02150000
  67. mmc resp 0x00000920
  68. mmc 0, cmd 6(0x80000146), arg 0x00000000
  69. mmc resp 0x00000920
  70. set ios: bus_width: 1, clock: 25000000
  71. mmc 0 set mod-clk req 25000000 parent 600000000 n 2 m 12 rate 25000000
  72. mmc 0, cmd 6(0x80002346), arg 0x80fffff1
  73. trans data 64 bytes
  74. cacl timeout 78 msec
  75. mmc resp 0x00000900
  76. clock is enabled (50000000Hz)
  77. set ios: bus_width: 1, clock: 50000000
  78. mmc 0 set mod-clk req 50000000 parent 600000000 n 1 m 12 rate 50000000
  79. spl_mmc_boot_mode(): user part
  80. spl: mmc boot mode: raw
  81. mmc 0, cmd 16(0x80000150), arg 0x00000200
  82. mmc resp 0x00000900
  83. mmc 0, cmd 17(0x80002351), arg 0x00000050
  84. trans data 512 bytes
  85. cacl timeout 78 msec
  86. mmc resp 0x00000900
  87. hdr read sector 50, count=1
  88. mkimage signature not found - ih_magic = 0
  89. mmc 0, cmd 16(0x80000150), arg 0x00000200
  90. mmc resp 0x00000900
  91. mmc 0, cmd 18(0x80003352), arg 0x00000050
  92. trans data 786432 bytes
  93. cacl timeout 78 msec
  94. mmc resp 0x00000900
  95. mmc cmd 12 check rsp busy
  96. read 600 sectors to 4a000000
  97. Jumping to U-Boot...
  98. SPL malloc() used 0x198 bytes (0 KB)
  99. image entry point: 0x4a000000
  100.  
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