Demux

module multiplexer( x,y, a , b   );
    input x , y;
    output a , b;
    assign a = ( y & (~x ) );
    assign b = ( y & x );
endmodule


module Test;
    reg x , y;
    wire a , b;

    multiplexer uut(
        .x( x ),.y( y ),
        .a( a ),
        .b( b )

    );
    initial begin
       // $dumpfile("adder4bit.vcd");
        //$dumpvars(0,adder4b_test);
        x = 0;
        y = 0;
        #10;

        x = 0;
        y = 1;
        #10;

        x = 1;
        y = 0;
        #10;

        x = 1;
        y = 1;
        #10;



    end

    initial begin
          $monitor("t=%4d X=%b, Y=%b , A=%b, B=%b\n",$time,x , y , a , b);
         end



endmodule