library ieee;
use ieee.std_logic_1164.all;

entity kombimreze_tb is
end kombimreze_tb;

architecture kombimreze_tb of kombimreze_tb is
	signal iSW : std_logic_vector(7 downto 0);
	signal iINV : std_logic;

	signal oLED : std_logic_vector(7 downto 0);
	signal oSIGN : std_logic;
	signal oGREAT : std_logic;


component kombimreze
	port(
		iSW : in std_logic_vector(7 downto 0);
		iINV : in std_logic;

		oLED : out std_logic_vector(7 downto 0);
		oSIGN : out std_logic;
		oGREAT : out std_logic
	 );
end component;

begin

	uut : kombimreze port map (
	 iSW => iSW,
	 iINV => iINV,
	 oLED => oLED,
	 oSIGN => oSIGN,
	 oGREAT => oGREAT
	 );

stimulus : process
begin

	iSW <= "11110100";
	iINV <= '0';
	wait for 100 ns;
	iINV <= '1';
	wait for 100 ns;

	iSW <= "01101001";
	iINV <= '1';
	wait for 100 ns;
	iINV <= '0';
	wait for 100 ns;

	iSW <= "11011001";
	iINV <= '0';
	wait for 100 ns;
	iINV <= '1';
	wait for 100 ns;

	iSW <= "10011001";
	iINV <= '0';
	wait for 100 ns;
	iINV <= '1';

	iSW <= "10011101";
	iINV <= '0';
	wait for 100 ns;
	iINV <= '1';

	iSW <= "11111111";
	iINV <= '0';
	wait for 100 ns;
	iINV <= '1';

	wait;


end process stimulus;
end architecture;