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  1. Debug: 10400 136766 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_flash fillb 0x8000000 0xbb 192
  2. Debug: 10401 136766 command.c:143 script_debug(): command - ocd_flash ocd_flash fillb 0x8000000 0xbb 192
  3. Debug: 10403 136772 target.c:2345 target_read_u32(): address: 0x40022004, value: 0x00000007
  4. Debug: 10404 136772 target.c:2433 target_write_u32(): address: 0x4002200c, value: 0x89abcdef
  5. Debug: 10405 136776 target.c:2433 target_write_u32(): address: 0x4002200c, value: 0x02030405
  6. Debug: 10406 136786 target.c:2345 target_read_u32(): address: 0x40022004, value: 0x00000006
  7. Debug: 10407 136786 target.c:2433 target_write_u32(): address: 0x40022010, value: 0x8c9daebf
  8. Debug: 10408 136790 target.c:2433 target_write_u32(): address: 0x40022010, value: 0x13141516
  9. Debug: 10409 136797 target.c:2345 target_read_u32(): address: 0x40022004, value: 0x00000004
  10. Debug: 10410 136797 target.c:1832 target_alloc_working_area_try(): allocated new working area of 16 bytes at address 0x20000000
  11. Debug: 10411 136797 target.c:1694 print_wa_layout(): * 0x20000000-0x2000000f (16 bytes)
  12. Debug: 10412 136797 target.c:1694 print_wa_layout(): 0x20000010-0x20003fff (16368 bytes)
  13. Debug: 10413 136797 target.c:2136 target_write_buffer(): writing buffer of 16 byte at 0x20000000
  14. Debug: 10414 136802 target.c:1832 target_alloc_working_area_try(): allocated new working area of 15360 bytes at address 0x20000010
  15. Debug: 10415 136802 target.c:1694 print_wa_layout(): * 0x20000000-0x2000000f (16 bytes)
  16. Debug: 10416 136802 target.c:1694 print_wa_layout(): * 0x20000010-0x20003c0f (15360 bytes)
  17. Debug: 10417 136802 target.c:1694 print_wa_layout(): 0x20003c10-0x20003fff (1008 bytes)
  18. Debug: 10418 136807 target.c:2345 target_read_u32(): address: 0x40022004, value: 0x00000004
  19. Debug: 10419 136812 target.c:2345 target_read_u32(): address: 0x40022004, value: 0x00000004
  20. Debug: 10420 136812 target.c:2433 target_write_u32(): address: 0x40022004, value: 0x00000404
  21. Debug: 10421 136824 target.c:2345 target_read_u32(): address: 0x40022004, value: 0x00000404
  22. Debug: 10422 136824 target.c:2433 target_write_u32(): address: 0x40022004, value: 0x0000040c
  23. Debug: 10423 136829 target.c:2136 target_write_buffer(): writing buffer of 192 byte at 0x20000010
  24. Debug: 10424 136840 ftdi.c:1177 ftdi_swd_queue_cmd(): Increased SWD command queue to 80 elements
  25. Debug: 10425 136846 target.c:1579 target_call_event_callbacks(): target event 3 (resume-start)
  26. Debug: 10426 136846 armv7m.c:148 armv7m_restore_context():
  27. Debug: 10427 136846 armv7m.c:280 armv7m_write_core_reg(): write core reg 19 value 0x1
  28. Debug: 10428 136855 cortex_m.c:1661 cortex_m_store_core_reg_u32(): write special reg 19 value 0x1
  29. Debug: 10429 136855 armv7m.c:280 armv7m_write_core_reg(): write core reg 18 value 0x0
  30. Debug: 10430 136861 cortex_m.c:1605 cortex_m_store_core_reg_u32(): write core reg 18 value 0x0
  31. Debug: 10431 136861 armv7m.c:280 armv7m_write_core_reg(): write core reg 16 value 0x1000000
  32. Debug: 10432 136866 cortex_m.c:1605 cortex_m_store_core_reg_u32(): write core reg 16 value 0x1000000
  33. Debug: 10433 136866 armv7m.c:280 armv7m_write_core_reg(): write core reg 15 value 0x20000000
  34. Debug: 10434 136871 cortex_m.c:1605 cortex_m_store_core_reg_u32(): write core reg 15 value 0x20000000
  35. Debug: 10435 136871 armv7m.c:280 armv7m_write_core_reg(): write core reg 14 value 0x0
  36. Debug: 10436 136876 cortex_m.c:1605 cortex_m_store_core_reg_u32(): write core reg 14 value 0x0
  37. Debug: 10437 136876 armv7m.c:280 armv7m_write_core_reg(): write core reg 12 value 0x0
  38. Debug: 10438 136881 cortex_m.c:1605 cortex_m_store_core_reg_u32(): write core reg 12 value 0x0
  39. Debug: 10439 136881 armv7m.c:280 armv7m_write_core_reg(): write core reg 11 value 0x0
  40. Debug: 10440 136887 cortex_m.c:1605 cortex_m_store_core_reg_u32(): write core reg 11 value 0x0
  41. Debug: 10441 136887 armv7m.c:280 armv7m_write_core_reg(): write core reg 10 value 0x0
  42. Debug: 10442 136893 cortex_m.c:1605 cortex_m_store_core_reg_u32(): write core reg 10 value 0x0
  43. Debug: 10443 136893 armv7m.c:280 armv7m_write_core_reg(): write core reg 9 value 0x0
  44. Debug: 10444 136898 cortex_m.c:1605 cortex_m_store_core_reg_u32(): write core reg 9 value 0x0
  45. Debug: 10445 136898 armv7m.c:280 armv7m_write_core_reg(): write core reg 8 value 0x0
  46. Debug: 10446 136903 cortex_m.c:1605 cortex_m_store_core_reg_u32(): write core reg 8 value 0x0
  47. Debug: 10447 136903 armv7m.c:280 armv7m_write_core_reg(): write core reg 7 value 0x0
  48. Debug: 10448 136909 cortex_m.c:1605 cortex_m_store_core_reg_u32(): write core reg 7 value 0x0
  49. Debug: 10449 136909 armv7m.c:280 armv7m_write_core_reg(): write core reg 6 value 0x0
  50. Debug: 10450 136915 cortex_m.c:1605 cortex_m_store_core_reg_u32(): write core reg 6 value 0x0
  51. Debug: 10451 136915 armv7m.c:280 armv7m_write_core_reg(): write core reg 5 value 0x0
  52. Debug: 10452 136921 cortex_m.c:1605 cortex_m_store_core_reg_u32(): write core reg 5 value 0x0
  53. Debug: 10453 136921 armv7m.c:280 armv7m_write_core_reg(): write core reg 4 value 0x0
  54. Debug: 10454 136927 cortex_m.c:1605 cortex_m_store_core_reg_u32(): write core reg 4 value 0x0
  55. Debug: 10455 136927 armv7m.c:280 armv7m_write_core_reg(): write core reg 3 value 0x0
  56. Debug: 10456 136933 cortex_m.c:1605 cortex_m_store_core_reg_u32(): write core reg 3 value 0x0
  57. Debug: 10457 136933 armv7m.c:280 armv7m_write_core_reg(): write core reg 2 value 0x30
  58. Debug: 10458 136937 cortex_m.c:1605 cortex_m_store_core_reg_u32(): write core reg 2 value 0x30
  59. Debug: 10459 136938 armv7m.c:280 armv7m_write_core_reg(): write core reg 1 value 0x20000010
  60. Debug: 10460 136943 cortex_m.c:1605 cortex_m_store_core_reg_u32(): write core reg 1 value 0x20000010
  61. Debug: 10461 136943 armv7m.c:280 armv7m_write_core_reg(): write core reg 0 value 0x8000000
  62. Debug: 10462 136948 cortex_m.c:1605 cortex_m_store_core_reg_u32(): write core reg 0 value 0x8000000
  63. Debug: 10463 136953 target.c:1579 target_call_event_callbacks(): target event 16 (debug-resumed)
  64. Debug: 10464 136953 cortex_m.c:784 cortex_m_resume(): target debug resumed at 0x20000000
  65. Debug: 10465 136953 target.c:1579 target_call_event_callbacks(): target event 4 (resume-end)
  66. Debug: 10466 136959 cortex_m.c:590 cortex_m_halt(): target->state: unknown
  67. Warn : 10467 136959 cortex_m.c:598 cortex_m_halt(): target was in unknown state when halt was requested
  68. Debug: 10468 136959 ftdi.c:1248 ftdi_swd_switch_seq(): JTAG-to-SWD
  69. Info : 10469 136964 adi_v5_swd.c:136 swd_connect(): SWD DPIDR 0x0bc11477
  70. Debug: 10470 136964 arm_adi_v5.c:653 dap_dp_init(): stm32l0.dap
  71. Debug: 10471 136969 arm_adi_v5.c:698 dap_dp_init(): DAP: wait CDBGPWRUPACK
  72. Debug: 10472 136969 arm_adi_v5.h:447 dap_dp_poll_register(): DAP: poll 4, mask 0x20000000, value 0x20000000
  73. Debug: 10473 136973 arm_adi_v5.c:706 dap_dp_init(): DAP: wait CSYSPWRUPACK
  74. Debug: 10474 136973 arm_adi_v5.h:447 dap_dp_poll_register(): DAP: poll 4, mask 0x80000000, value 0x80000000
  75. Debug: 10475 136996 target.c:1901 target_free_working_area_restore(): freed 15360 bytes of working area at address 0x20000010
  76. Debug: 10476 136996 target.c:1694 print_wa_layout(): * 0x20000000-0x2000000f (16 bytes)
  77. Debug: 10477 136996 target.c:1694 print_wa_layout(): 0x20000010-0x20003fff (16368 bytes)
  78. Debug: 10478 136996 target.c:1901 target_free_working_area_restore(): freed 16 bytes of working area at address 0x20000000
  79. Debug: 10479 136996 target.c:1694 print_wa_layout(): 0x20000000-0x20003fff (16384 bytes)
  80. Error: 10480 136996 core.c:104 flash_driver_write(): error writing to flash at address 0x08000000 at offset 0x00000000
  81. Debug: 10481 136997 command.c:651 run_command(): Command 'flash fillb' failed with error code -4
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