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  1. .NOLIST
  2. .INCLUDE "m128def.inc"
  3. .LIST
  4.  
  5. init:
  6. .def podminka = r16
  7. .def reg = r17
  8. .def pocet = r18
  9. .def timer = r19
  10. .def krok = r20
  11. .def cas = r21
  12. ldi reg, 0x0F ;prvni 4 bity jsou vystupni (radky), druhe 4 jsou vstupni (sloupce)
  13. out ddrb, reg
  14. ldi reg, 0xFF
  15. out ddre, reg
  16. ldi reg, low(RAMEND)
  17. out spl, reg
  18. ldi reg, high(RAMEND)
  19. out sph, reg
  20.  
  21. pocatek:
  22. ldi Xh, high(0x0120)
  23. ldi Xl, low(0x0120)
  24. ldi pocet, 0
  25.  
  26. test:
  27. cpi pocet, 15
  28. brne test_1rad
  29. jmp init_displej
  30. test_1rad:
  31. ldi reg, 0b11111110 ;0 aktivuji prvni radek
  32. out portb, reg
  33. in reg, pinb
  34. ulozeni_EE: ;cislice z prava urcuji aktivni sloupec
  35. cpi reg, 0xEE
  36. brne ulozeni_DE
  37. st X+, reg
  38. inc pocet
  39. jmp test
  40. ulozeni_DE: ;cislice z prava urcuji aktivni sloupec
  41. cpi reg, 0xDE
  42. brne ulozeni_BE
  43. st X+, reg
  44. inc pocet
  45. jmp test
  46. ulozeni_BE: ;cislice z prava urcuji aktivni sloupec
  47. cpi reg, 0xBE
  48. brne ulozeni_7E
  49. st X+, reg
  50. inc pocet
  51. jmp test
  52. ulozeni_7E: ;cislice z prava urcuji aktivni sloupec
  53. cpi reg, 0x7E
  54. brne test_2rad
  55. jmp test
  56.  
  57. test_2rad:
  58. ldi reg, 0b11111101 ;0 aktivuji prvni radek
  59. out portb, reg
  60. in reg, pinb
  61. ulozeni_ED: ;cislice z prava urcuji aktivni sloupec
  62. cpi reg, 0xED
  63. brne ulozeni_DD
  64. st X+, reg
  65. inc pocet
  66. jmp test
  67. ulozeni_DD: ;cislice z prava urcuji aktivni sloupec
  68. cpi reg, 0xDD
  69. brne ulozeni_BD
  70. st X+, reg
  71. inc pocet
  72. jmp test
  73. ulozeni_BD: ;cislice z prava urcuji aktivni sloupec
  74. cpi reg, 0xBD
  75. brne ulozeni_7D
  76. st X+, reg
  77. inc pocet
  78. jmp test
  79. ulozeni_7D: ;cislice z prava urcuji aktivni sloupec
  80. cpi reg, 0x7D
  81. brne test_3rad
  82. st X+, reg
  83. inc pocet
  84. jmp test
  85.  
  86. test_3rad:
  87. ldi reg, 0b11111011 ;0 aktivuji prvni radek
  88. out portb, reg
  89. in reg, pinb
  90. ulozeni_EB: ;cislice z prava urcuji aktivni sloupec
  91. cpi reg, 0xEB
  92. brne ulozeni_DB
  93. st X+, reg
  94. inc pocet
  95. jmp test
  96. ulozeni_DB: ;cislice z prava urcuji aktivni sloupec
  97. cpi reg, 0xDB
  98. brne ulozeni_BB
  99. st X+, reg
  100. inc pocet
  101. jmp test
  102. ulozeni_BB: ;cislice z prava urcuji aktivni sloupec
  103. cpi reg, 0xBB
  104. brne ulozeni_7B
  105. st X+, reg
  106. inc pocet
  107. jmp test
  108. ulozeni_7B: ;cislice z prava urcuji aktivni sloupec
  109. cpi reg, 0x7B
  110. brne test_4rad
  111. st X+, reg
  112. inc pocet
  113. jmp test
  114.  
  115. test_4rad:
  116. ldi reg, 0b11110111 ;0 aktivuji prvni radek
  117. out portb, reg
  118. in reg, pinb
  119. ulozeni_E7: ;cislice z prava urcuji aktivni sloupec
  120. cpi reg, 0xE7
  121. brne ulozeni_D7
  122. st X+, reg
  123. inc pocet
  124. jmp test
  125. ulozeni_D7: ;cislice z prava urcuji aktivni sloupec
  126. cpi reg, 0xD7
  127. brne ulozeni_B7
  128. st X+, reg
  129. inc pocet
  130. jmp test
  131. ulozeni_B7: ;cislice z prava urcuji aktivni sloupec
  132. cpi reg, 0xB7
  133. brne ulozeni_77
  134. st X+, reg
  135. inc pocet
  136. jmp test
  137. ulozeni_77: ;cislice z prava urcuji aktivni sloupec
  138. cpi reg, 0x77
  139. breq dal
  140. jmp test
  141. dal:
  142. cpi pocet, 5
  143. breq init_displej
  144. jmp test
  145.  
  146. init_displej:
  147. ldi Xh, high(0x0120)
  148. ldi Xl, low(0x0120)
  149. cteni:
  150. ld reg, X+
  151. cpi reg, 0xEE
  152. brne d1
  153. jmp svitN1
  154. d1:
  155. cpi reg, 0xDE
  156. brne d2
  157. jmp svitN2
  158. d2:
  159. cpi reg, 0xBE
  160. breq svitN3
  161. cpi reg, 0xED
  162. breq svitN4
  163. cpi reg, 0xDD
  164. breq svitN5
  165. cpi reg, 0xBD
  166. breq svitN6
  167. cpi reg, 0x7D
  168. breq svitF1
  169. cpi reg, 0xEB
  170. breq svitN7
  171. cpi reg, 0xDB
  172. breq svitN8
  173. cpi reg, 0xBB
  174. breq svitN9
  175. cpi reg, 0x7B
  176. breq svitF2
  177. cpi reg, 0xE7
  178. breq svitHV
  179. cpi reg, 0xD7
  180. breq svitN0
  181. cpi reg, 0xB7
  182. breq svitKR
  183. jmp init_displej
  184.  
  185. svitN1:
  186. ldi cas, 0xFF
  187. nastN1:
  188. ldi Zl, low(N1*2)
  189. ldi Zh, high(N1*2)
  190. ldi krok, 0
  191. dec cas
  192. cpi cas, 0
  193. brne krokN1
  194. jmp cteni
  195. krokN1:
  196. lpm reg, Z+
  197. out porte, reg
  198. call delay
  199. call podminka_esc
  200. inc krok
  201. cpi krok, 10
  202. breq nastN1
  203. jmp krokN1
  204.  
  205. svitN2:
  206. ldi cas, 0xFF
  207. nastN2:
  208. ldi Zl, low(N2*2)
  209. ldi Zh, high(N2*2)
  210. ldi krok, 0
  211. dec cas
  212. cpi cas, 0
  213. brne krokN2
  214. jmp cteni
  215. krokN2:
  216. lpm reg, Z+
  217. out porte, reg
  218. call delay
  219. call podminka_esc
  220. inc krok
  221. cpi krok, 10
  222. breq nastN2
  223. jmp krokN2
  224.  
  225. svitN3:
  226. ldi cas, 0xFF
  227. nastN3:
  228. ldi Zl, low(N3*2)
  229. ldi Zh, high(N3*2)
  230. ldi krok, 0
  231. dec cas
  232. cpi cas, 0
  233. brne krokN3
  234. jmp cteni
  235. krokN3:
  236. lpm reg, Z+
  237. out porte, reg
  238. call delay
  239. call podminka_esc
  240. inc krok
  241. cpi krok, 10
  242. breq nastN3
  243. jmp krokN3
  244.  
  245. svitN4:
  246. ldi cas, 0xFF
  247. nastN4:
  248. ldi Zl, low(N4*2)
  249. ldi Zh, high(N4*2)
  250. ldi krok, 0
  251. dec cas
  252. cpi cas, 0
  253. brne krokN4
  254. jmp cteni
  255. krokN4:
  256. lpm reg, Z+
  257. out porte, reg
  258. call delay
  259. call podminka_esc
  260. inc krok
  261. cpi krok, 10
  262. breq nastN4
  263. jmp krokN4
  264.  
  265. svitN5:
  266. ldi cas, 0xFF
  267. nastN5:
  268. ldi Zl, low(N5*2)
  269. ldi Zh, high(N5*2)
  270. ldi krok, 0
  271. dec cas
  272. cpi cas, 0
  273. brne krokN5
  274. jmp cteni
  275. krokN5:
  276. lpm reg, Z+
  277. out porte, reg
  278. call delay
  279. call podminka_esc
  280. inc krok
  281. cpi krok, 10
  282. breq nastN5
  283. jmp krokN5
  284.  
  285. svitN6:
  286. ldi cas, 0xFF
  287. nastN6:
  288. ldi Zl, low(N6*2)
  289. ldi Zh, high(N6*2)
  290. ldi krok, 0
  291. dec cas
  292. cpi cas, 0
  293. brne krokN6
  294. jmp cteni
  295. krokN6:
  296. lpm reg, Z+
  297. out porte, reg
  298. call delay
  299. call podminka_esc
  300. inc krok
  301. cpi krok, 10
  302. breq nastN6
  303. jmp krokN6
  304.  
  305. svitF1:
  306. ldi cas, 0xFF
  307. nastF1:
  308. ldi Zl, low(F1*2)
  309. ldi Zh, high(F1*2)
  310. ldi krok, 0
  311. dec cas
  312. cpi cas, 0
  313. brne krokF1
  314. jmp cteni
  315. krokF1:
  316. lpm reg, Z+
  317. out porte, reg
  318. call delay
  319. call podminka_esc
  320. inc krok
  321. cpi krok, 10
  322. breq nastF1
  323. jmp krokF1
  324.  
  325. svitN7:
  326. ldi cas, 0xFF
  327. nastN7:
  328. ldi Zl, low(N7*2)
  329. ldi Zh, high(N7*2)
  330. ldi krok, 0
  331. dec cas
  332. cpi cas, 0
  333. brne krokN7
  334. jmp cteni
  335. krokN7:
  336. lpm reg, Z+
  337. out porte, reg
  338. call delay
  339. call podminka_esc
  340. inc krok
  341. cpi krok, 10
  342. breq nastN7
  343. jmp krokN7
  344.  
  345. svitN8:
  346. ldi cas, 0xFF
  347. nastN8:
  348. ldi Zl, low(N8*2)
  349. ldi Zh, high(N8*2)
  350. ldi krok, 0
  351. dec cas
  352. cpi cas, 0
  353. brne krokN8
  354. jmp cteni
  355. krokN8:
  356. lpm reg, Z+
  357. out porte, reg
  358. call delay
  359. call podminka_esc
  360. inc krok
  361. cpi krok, 10
  362. breq nastN8
  363. jmp krokN8
  364.  
  365. svitN9:
  366. ldi cas, 0xFF
  367. nastN9:
  368. ldi Zl, low(N9*2)
  369. ldi Zh, high(N9*2)
  370. ldi krok, 0
  371. dec cas
  372. cpi cas, 0
  373. brne krokN9
  374. jmp cteni
  375. krokN9:
  376. lpm reg, Z+
  377. out porte, reg
  378. call delay
  379. call podminka_esc
  380. inc krok
  381. cpi krok, 10
  382. breq nastN9
  383. jmp krokN9
  384.  
  385. svitF2:
  386. ldi cas, 0xFF
  387. nastF2:
  388. ldi Zl, low(F2*2)
  389. ldi Zh, high(F2*2)
  390. ldi krok, 0
  391. dec cas
  392. cpi cas, 0
  393. brne krokF2
  394. jmp cteni
  395. krokF2:
  396. lpm reg, Z+
  397. out porte, reg
  398. call delay
  399. call podminka_esc
  400. inc krok
  401. cpi krok, 10
  402. breq nastF2
  403. jmp krokF2
  404.  
  405. svitHV:
  406. ldi cas, 0xFF
  407. nastHV:
  408. ldi Zl, low(HV*2)
  409. ldi Zh, high(HV*2)
  410. ldi krok, 0
  411. dec cas
  412. cpi cas, 0
  413. brne krokHV
  414. jmp cteni
  415. krokHV:
  416. lpm reg, Z+
  417. out porte, reg
  418. call delay
  419. call podminka_esc
  420. inc krok
  421. cpi krok, 10
  422. breq nastHV
  423. jmp krokHV
  424.  
  425. svitN0:
  426. ldi cas, 0xFF
  427. nastN0:
  428. ldi Zl, low(N0*2)
  429. ldi Zh, high(N0*2)
  430. ldi krok, 0
  431. dec cas
  432. cpi cas, 0
  433. brne krokN0
  434. jmp cteni
  435. krokN0:
  436. lpm reg, Z+
  437. out porte, reg
  438. call delay
  439. call podminka_esc
  440. inc krok
  441. cpi krok, 10
  442. breq nastN0
  443. jmp krokN0
  444.  
  445. svitKR:
  446. ldi cas, 0xFF
  447. nastKR:
  448. ldi Zl, low(KR*2)
  449. ldi Zh, high(KR*2)
  450. ldi krok, 0
  451. dec cas
  452. cpi cas, 0
  453. brne krokKR
  454. jmp cteni
  455. krokKR:
  456. lpm reg, Z+
  457. out porte, reg
  458. call delay
  459. call podminka_esc
  460. inc krok
  461. cpi krok, 10
  462. breq nastKR
  463. jmp krokKR
  464.  
  465. N1:
  466. .DB 0b00001000, 0b10001000, 0b00000100, 0b10000100
  467. .DB 0b00000010, 0b10000010, 0b01111111, 0b11111111
  468. .DB 0b00000000, 0b10000000
  469.  
  470. N2:
  471. .DB 0b01000110, 0b11000110, 0b01100001, 0b11100001
  472. .DB 0b01010001, 0b11010001, 0b01001001, 0b11001001
  473. .DB 0b01000110, 0b11000110
  474.  
  475. N3:
  476. .DB 0b01000001, 0b11000001, 0b01001001, 0b11001001
  477. .DB 0b01001001, 0b11001001, 0b01001001, 0b11001001
  478. .DB 0b00110110, 0b10110110
  479.  
  480. N4:
  481. .DB 0b00001111, 0b10001111, 0b00001000, 0b10001000
  482. .DB 0b01111100, 0b11111100, 0b00001000, 0b10001000
  483. .DB 0b00001000, 0b10001000
  484.  
  485. N5:
  486. .DB 0b00101111, 0b10101111, 0b01000101, 0b11000101
  487. .DB 0b01000101, 0b11000101, 0b01000101, 0b11000101
  488. .DB 0b00111001, 0b10111001
  489.  
  490. N6:
  491. .DB 0b00111110, 0b10111110, 0b01000101, 0b11000101
  492. .DB 0b01000101, 0b11000101, 0b01000101, 0b11000101
  493. .DB 0b00111001, 0b10111001
  494.  
  495. F1:
  496. .DB 0b01111111, 0b11111111, 0b01000001, 0b11000001
  497. .DB 0b01000001, 0b11000001, 0b01000001, 0b11000001
  498. .DB 0b01111111, 0b11111111
  499.  
  500. N7:
  501. .DB 0b01000001, 0b11000001, 0b00100001, 0b10100001
  502. .DB 0b00010001, 0b10010001, 0b00001001, 0b10001001
  503. .DB 0b00000111, 0b10000111
  504.  
  505. N8:
  506. .DB 0b00110110, 0b10110110, 0b01001001, 0b11001001
  507. .DB 0b01001001, 0b11001001, 0b01001001, 0b11001001
  508. .DB 0b00110110, 0b10110110
  509.  
  510. N9:
  511. .DB 0b00100110, 0b10100110, 0b01001001, 0b11001001
  512. .DB 0b01001001, 0b11001001, 0b01001001, 0b11001001
  513. .DB 0b00111110, 0b10111110
  514.  
  515. F2:
  516. .DB 0b01111111, 0b11111111, 0b01000001, 0b11000001
  517. .DB 0b01111111, 0b11111111, 0b01000001, 0b11000001
  518. .DB 0b01111111, 0b11111111
  519.  
  520. HV:
  521. .DB 0b00101010, 0b10101010, 0b00011100, 0b10011100
  522. .DB 0b01111111, 0b11111111, 0b00011100, 0b10011100
  523. .DB 0b00101010, 0b10101010
  524.  
  525. N0:
  526. .DB 0b00111110, 0b10111110, 0b01000001, 0b11000001
  527. .DB 0b01000001, 0b11000001, 0b01000001, 0b11000001
  528. .DB 0b00111110, 0b10111110
  529.  
  530. KR:
  531. .DB 0b00010100, 0b10010100, 0b01111111, 0b11111111
  532. .Db 0b00010100, 0b10010100, 0b01111111, 0b11111111
  533. .Db 0b00010100, 0b10010100
  534.  
  535. podminka_esc:
  536. ldi podminka, 0xFE
  537. out portb, podminka
  538. in podminka, pinb
  539. cpi podminka, 0x7E
  540. breq dalp
  541. ret
  542. dalp:
  543. jmp pocatek
  544.  
  545. delay:
  546. ldi timer, 0xFF
  547. time:
  548. dec timer
  549. brne time
  550. ret
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