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  1. ; --COPYRIGHT--,BSD_EX
  2. ; Copyright (c) 2012, Texas Instruments Incorporated
  3. ; All rights reserved.
  4. ;
  5. ; Redistribution and use in source and binary forms, with or without
  6. ; modification, are permitted provided that the following conditions
  7. ; are met:
  8. ;
  9. ; * Redistributions of source code must retain the above copyright
  10. ; notice, this list of conditions and the following disclaimer.
  11. ;
  12. ; * Redistributions in binary form must reproduce the above copyright
  13. ; notice, this list of conditions and the following disclaimer in the
  14. ; documentation and/or other materials provided with the distribution.
  15. ;
  16. ; * Neither the name of Texas Instruments Incorporated nor the names of
  17. ; its contributors may be used to endorse or promote products derived
  18. ; from this software without specific prior written permission.
  19. ;
  20. ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21. ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  22. ; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  23. ; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  24. ; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  25. ; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  26. ; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  27. ; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  28. ; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  29. ; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  30. ; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31. ;
  32. ; ******************************************************************************
  33. ;
  34. ; MSP430 CODE EXAMPLE DISCLAIMER
  35. ;
  36. ; MSP430 code examples are self-contained low-level programs that typically
  37. ; demonstrate a single peripheral function or device feature in a highly
  38. ; concise manner. For this the code may rely on the device's power-on default
  39. ; register values and settings such as the clock configuration and care must
  40. ; be taken when combining code from several examples to avoid potential side
  41. ; effects. Also see www.ti.com/grace for a GUI- and www.ti.com/msp430ware
  42. ; for an API functional library-approach to peripheral configuration.
  43. ;
  44. ; --/COPYRIGHT--
  45. ;******************************************************************************
  46. ; MSP430xG46x Demo - Timer_A, Toggle P5.1, TACCR0 Cont. Mode ISR, DCO SMCLK
  47. ;
  48. ; Description: Toggle P5.1 using software and TA_0 ISR. Toggles every
  49. ; 50000 SMCLK cycles. SMCLK provides clock source for TACLK.
  50. ; During the TA_0 ISR, P5.1 is toggled and 50000 clock cycles are added
  51. ; to TACCR0. TA_0 ISR is triggered every 50000 cycles. CPU is normally off
  52. ; and used only during TA_ISR.
  53. ; ACLK = 32.768kHz, MCLK = SMCLK = TACLK = default DCO
  54. ;
  55. ; MSP430xG461x
  56. ; -----------------
  57. ; /|\| XIN|-
  58. ; | | | 32kHz
  59. ; --|RST XOUT|-
  60. ; | |
  61. ; | P5.1|-->LED
  62. ;
  63. ; S. Karthikeyan/ K.Venkat
  64. ; Texas Instruments Inc.
  65. ; Dec 2006
  66. ; Built with IAR Embedded Workbench Version: 3.41A
  67. ;******************************************************************************
  68. #include <msp430.h>
  69. ;-------------------------------------------------------------------------------
  70. RSEG CSTACK ; Define stack segment
  71. ;-------------------------------------------------------------------------------
  72. RSEG CODE ; Assemble to Flash memory
  73. ;-----------------------------------------------------------------------------
  74. ; ******************* 1. Инициализация таймера и LCD-дисплея ******************
  75.  
  76. RESET mov.w #SFE(CSTACK), SP ; Initialize stackpointer
  77. mov.b #LCDON + LCD4MUX + LCDFREQ_128, &LCDACTL ; 4mux LCD, ACLK/128
  78. mov.b #0x0F, &LCDAPCTL0 ; Segments 0-13
  79. mov.b #0x1C, &P5SEL ; set COM pins for LCD
  80. ClearLCD mov.w #20, R15 ; 15 LCD memory bytes to clear
  81. Clear1 mov.b #0, LCDM1(R15) ; Write zeros in LCD RAM locations
  82. ; to clear display
  83. dec R15 ; All LCD mem clear?
  84. jc Clear1 ; More LCD mem to clear go, use JC
  85. StopWDT mov.w #WDTPW+WDTHOLD, &WDTCTL ; Stop WDT
  86. SetupFLL bis.b #XCAP14PF, &FLL_CTL0 ; Configure load caps
  87. OFIFGcheck bic.b #OFIFG, &IFG1 ; Clear OFIFG
  88. mov.w #047FFh, R15 ; Wait for OFIFG to set again if
  89. OFIFGwait dec.w R15 ; not stable yet
  90. jnz OFIFGwait
  91. bit.b #OFIFG, &IFG1 ; Has it set again?
  92. jnz OFIFGcheck ; If so, wait some more
  93. SetupP5 bis.b #002h, &P5DIR ; P5.1 output
  94. SetupC0 mov.w #CCIE, &TACCTL0 ; TACCR0 interrupt enabled
  95.  
  96. ; CCIE and CCIFG (bits 4 and 0) are
  97. ;more interrupts associated
  98. ; with the CCR's.
  99. mov.w #50000, &TACCR0 ;
  100. SetupTA mov.w #TASSEL_2+MC_2, &TACTL ; SMCLK, continuous mode
  101.  
  102. ; ****************** 2. Установка начальных значений **************************
  103. Mainloop mov.w #01024d, R7 ; number
  104. mov.w #10d, R8 ; skip
  105. MOV #0, R9
  106. MOV #0, R10
  107. MOV #0, R11
  108. MOV #0, R12
  109. mov.w #6, R13 ; NA SKOL'KO INCREMENTIr\RO
  110. bis.w #CPUOFF+GIE, SR ; CPU off, interrupts enabled
  111. nop ; Required for debugger
  112.  
  113. ;bis.w #GIE, SR ; interrupts enabled
  114. ;jmp $
  115. ;nop
  116.  
  117. ; ****************** 3. Обработчик прерывания *********************************
  118.  
  119. TA0_ISR; DEC NUMBER
  120. ;------------------------------------------------------------------------------
  121. add.w #50000, &TACCR0 ; Add Offset to TACCR0
  122. dec.w R8
  123. jz run
  124. reti
  125. run:
  126. dec.w R7 ; number
  127. mov.w R7, R4
  128. call #ITOA ; int to string
  129. mov.w #10d, R8
  130. reti
  131.  
  132. ; * 4. Функция ITOA, переводящая число в строку и выводящая его на LCD-дисплей *
  133. ITOA:
  134.  
  135. MOV.W #00d, R6
  136.  
  137. MOV.B LCD_Tab(R9), LCDM3(R6)
  138. INC R6
  139. MOV.B LCD_Tab(R10), LCDM3(R6)
  140. INC R6
  141. MOV.B LCD_Tab(R11), LCDM3(R6)
  142. INC R6
  143. MOV.B LCD_Tab(R12), LCDM3(R6)
  144. INC R6
  145.  
  146. ; MOYA VSTAVKA
  147. CMP #10, R13
  148. JL UND
  149. SUB #16, R13
  150. INC R10
  151.  
  152. UND: DADD R13, R9
  153. CMP #10, R9
  154. JL ext
  155. SUB #16, R9
  156. INC R10
  157. CMP #10, R10
  158. JL ext
  159. MOV #0, R10
  160. INC R11
  161. CMP #10, R11
  162. JL ext
  163. MOV #0, R11
  164. INC R12
  165.  
  166.  
  167. ext: RET
  168.  
  169.  
  170. ; Digits code for 4-mux mode
  171. a EQU 080h ; .
  172. b EQU 040h ; left bottom
  173. c EQU 020h ; middle
  174. d EQU 001h ; top
  175. e EQU 002h ; right top
  176. f EQU 008h ; bottom
  177. g EQU 004h ; right bottom
  178. h EQU 010h ; left top
  179.  
  180. LCD_Tab DB b+d+e+f+g+h ; +a ; Displays '0'
  181. DB e+g ; +a ; Displays '1'
  182. DB d+e+c+b+f ; +a ; Displays '2'
  183. DB d+e+c+g+f ; +a ; Displays '3'
  184. DB h+c+e+g ; +a ; Displays '4'
  185. DB d+h+c+g+f ; +a ; Displays '5'
  186. DB d+h+c+b+f+g ; +a ; Displays '6'
  187. DB d+e+g ; +a ; Displays '7'
  188. DB b+c+d+e+f+g+h ;+a ; Displays '8'
  189. DB c+d+e+f+g+h ; +a ; Displays '9'
  190.  
  191.  
  192. ;------------------------------------------------------------------------------
  193. COMMON INTVEC ; Interrupt Vectors
  194. ;------------------------------------------------------------------------------
  195. ORG RESET_VECTOR ; MSP430 RESET Vector
  196. DW RESET ;
  197. ORG TIMERA0_VECTOR ; Timer_A0 Vector
  198. DW TA0_ISR ;
  199. END
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