lab 6

library ieee;
use ieee.std_logic_1164.all;
entity Topo is
port ( LEDR: out std_logic_vector(3 downto 0);
CLOCK_50: in std_logic;
KEY: in std_logic_vector(2 downto 0);
HEX0: out std_logic_vector(6 downto 0)
);
end Topo;
architecture topo_beh of Topo is
component FSM_Conta
port (
clock: in std_logic;
x: in std_logic;
y: out std_logic_vector(3 downto 0);
rst: in std_logic
);
end component;

component decod7seg
port(
C: in std_logic_vector(3 downto 0);
G: out std_logic_vector(6 downto 0)
);
end component;

component div_freq
port(
reset: in std_logic;
clock: in std_logic;
C1Hz: out std_logic
);
end component;

signal F: std_logic;
signal Y: std_logic_vector(3 downto 0);

Begin
L0: div_freq port map (KEY(), CLOCK_50, F);
L1: FSM_Conta port map (F, KEY(1), Y, KEY(0));
L2: decod7seg port map (Y, HEX0);
LEDR <= Y;
end topo_beh;

--------------------------------------------------------------------------fsm_conta

library ieee;
use ieee.std_logic_1164.all;
entity FSM_Conta is port(
clock: in std_logic;
x: in std_logic;
y: out std_logic_vector(3 downto 0);
rst: in std_logic
);

end FSM_Conta;

architecture bhv of FSM_Conta is
type STATES is (E0, E1, E2, E3, E4);
signal EA, PE: STATES;
signal contagem: std_logic_vector(3 downto 0);
begin
P1: process(clock, rst)
begin
if rst= '0' then
	EA <= E0;
elsif clock'event and clock= '0' then
	EA <= PE;
end if;
end process;
P2: process(EA)
begin
case EA is
when E0 =>
			  contagem <= "0001";
			  if x='1' then PE <= E1; else PE <= E0; end if;

when E1 =>
			  contagem <= "0010";
			  if x='1' then PE <= E2; else PE <= E1; end if;
when E2 =>
			  contagem <= "0011";
			  if x='1' then PE <= E3; else PE <= E2; end if;
when E3 =>
			  contagem <= "0100";
			  if x='1' then PE <= E4; else PE <= E3; end if;
when E4 =>
			  contagem <= "0101";
			  if x='1' then PE <= E0; else PE <= E4; end if;
end case;

end process;

y <= contagem;
end bhv;