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-- Company:
-- Engineer:
--
-- Create Date:    11:10:12 01/28/2020
-- Design Name:
-- Module Name:    progetto_TD_vhdl - Bank_entrance
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity progetto_TD_vhdl is
    Port ( --Inputs:
			  buttonA : in  STD_LOGIC;			--pulsante apertura portaA
           buttonB : in  STD_LOGIC;			--pulsante apertura portaB
           sensorA : in STD_LOGIC;			--sensore passaggio porta A
			  sensorB : in STD_LOGIC;			--sensore passaggio porta B
			  sensorC : in STD_LOGIC;			--rilevazione persona tra le due porte
			  md_detection : in STD_LOGIC;	--rilevazione metal detector

			  --Outputs:
           doorA : out  STD_LOGIC;			--apertura porta A
           doorB : out  STD_LOGIC;			--apertura porta B
           alarm : out  STD_LOGIC;			--attivazione allarme di sicurezza

			  clk : in  STD_LOGIC;
           rst : in  STD_LOGIC);
end progetto_TD_vhdl;

architecture Bank_entrance of progetto_TD_vhdl is
signal exit_temp : STD_LOGIC_VECTOR (0 to 2);

type state is ( s0, s1, s2, s3, s4, s5, s6, s7 );			--dichiarazione stati automa
signal current_state, next_state : state;

begin
	process(clk)
	begin
		if ( rising_edge ( clk ) ) then
			if ( rst = '1' ) then
				current_state <= s7;
			else
				current_state <= next_state;
			end if;
		end if;
	end process;

	next_state_and_output_moore: process(current_state, buttonA, buttonB,
													 sensorA, sensorB, sensorC, md_detection)
	begin
		case current_state is
			when s0 =>	exit_temp <= "000";
							if ( buttonA <= '1' and buttonB <= '0' ) then
								next_state <= s1;
							elsif (  buttonB <= '1' ) then
								next_state <= s5;
							else
								next_state <= s0;
							end if;
			when s1 =>	exit_temp <= "100";
							if( sensorC <= '1' and sensorA <= '0') then
								next_state <= s2;
							else
								next_state <= s1;
							end if;
			when s2 =>	exit_temp <= "000";
							if ( sensorC <= '1' and md_detection <= '0' ) then
								next_state <= s3;
							elsif ( sensorC <= '1' and md_detection <= '1' ) then
								next_state <= s4;
							else
								next_state <= s2;
							end if;
			when s3 =>	exit_temp <= "010";
							if ( sensorC <= '0' and sensorB <= '0' ) then
								next_state<=s0;
							else
								next_state<=s3;
							end if;
			when s4=>	exit_temp <= "101";
							if( sensorC <= '0' and sensorB <= '0' and md_detection <= '0' ) then
								next_state <= s0;
							else
								next_state <= s4;
							end if;
			when s5=> 	exit_temp <= "010";
							if( sensorC <= '1' and sensorB <= '0' )then
								next_state <= s6;
							else
								next_state <= s5;
							end if;
			when s6=> 	exit_temp <= "000";
							--wait for clk;
							next_state <= s7;
			when s7=> 	exit_temp <= "100";
							if( sensorC <= '0' and sensorA <= '0' )  then
								next_state <= s0;
							else
								next_state <= s7;
							end if;
		end case;
	end process;

	update_exit : process ( exit_temp )
	begin
			if(exit_temp<="000") then
				doorA<='0';
				doorB<='0';
				alarm<='0';
			elsif(exit_temp<="101") then
				doorA<='1';
				doorB<='0';
				alarm<='1';
			elsif(exit_temp<="100") then
				doorA<='1';
				doorB<='0';
				alarm<='0';
			elsif(exit_temp<="010") then
				doorA<='0';
				doorB<='1';
				alarm<='0';
			else
				doorA<='-';
				doorB<='-';
				alarm<='-';
			end if;
		end process;

end Bank_entrance;