/**
 * clock_t.h - clock peripheral configuration template
 *
 * Author: kimballr
 *   Date: 02/08/2012
 * Version: 0.01
 *
 */

#ifndef CLOCK_T_H_
#define CLOCK_T_H_

#include <msp430.h>

#define CLOCK_T_VERSION 0x0001 // 00.01

/**
 * BasicClock traits no clock out
 */
typedef struct {
    static const bool hasBasicClockPlus = true;
    static const bool hasCSClock = true;

    static void OutputSMCLK() { }
} BCSClockTraits, LaunchpadClockTraits;

/**
 * BasicClock traits clock out on P1.4
 */
typedef struct {
    static const bool hasBasicClockPlus = true;
    static const bool hasCSClock = true;

    static void OutputSMCLK() {
        P1DIR |= BIT4; P1SEL |= BIT4;
    }
} BCSDebugClockTraits, LaunchpadDebugClockTraits;

/**
 * BasicClock traits clock out on P1.4
 */
typedef struct {
    static const bool hasBasicClockPlus = false;
    static const bool hasCSClock = true;
    static void OutputSMCLK() {
        P1DIR |= BIT4; P1SEL |= BIT4;
    }
} UCSDebugClockTraits;

/**
 * CS traits clock out on J.0 - clock on the msp430fr5739
 *
 * The clock system module supports low system cost and low power consumption. Using three internal
 * clock signals, the user can select the best balance of performance and low power consumption. The
 * clock module can be configured to operate without any external components, with one or two external
 * crystals, or with resonators, under full software control
 */
typedef struct {
    static const bool hasBasicClockPlus = false;
    static const bool hasCSClock = true;

    static void OutputSMCLK() {
#ifdef __MSP430_HAS_CS__
        PJSEL0 |= BIT0;
        PJSEL1 &= ~BIT0;
        PJDIR |= BIT0;
#endif
    }
} FraunchpadDebugClockTraits;

/**
 * CLK_t - master clock template
 */
template <
    uint32_t MCLK = 1024000UL,
    typename ClockTraits = LaunchpadDebugClockTraits,
    uint32_t SMCLK = MCLK,
    uint32_t ACLK = 12000UL
    >
struct CLK_t {
    static const uint32_t MCLK_FREQ = MCLK;

    /**
     * init() - initialize the clock for the given MCLK_FREQ
     */
    static void init() {
        ClockTraits::OutputSMCLK();
        // default clock usually around 1.024MHz
        // do nothing to initialize, just use the default clock
    }

    static void OutputSMCLK() { ClockTraits::OutputSMCLK(); }
};

typedef CLK_t<> DefaultBCSMCLK;
typedef CLK_t<1024000UL,FraunchpadDebugClockTraits> DefaultCSMCLK;

/**
 * 16MHz BCS calibrated clock
 */
template<>
struct CLK_t<16000000UL> {
    static void init() {
        DefaultBCSMCLK::OutputSMCLK();

        DCOCTL = 0;
        BCSCTL1 = CALBC1_16MHZ;
        DCOCTL = CALDCO_16MHZ;

        { volatile uint16_t n; for(n=0; n < 0xffff; n++); }
    }
};

/**
 * 12MHz BCS calibrated clock
 */
template<>
struct CLK_t<12000000UL> {
    static void init() {
        DefaultBCSMCLK::OutputSMCLK();

        DCOCTL = 0;
        BCSCTL1 = CALBC1_12MHZ;
        DCOCTL = CALDCO_12MHZ;

        { volatile uint16_t n; for(n=0; n < 0xffff; n++); }
    }
};

/**
 * 8MHz BCS calibrated clock
 */
template<>
struct CLK_t<8000000UL> {
    static void init() {
        DefaultBCSMCLK::OutputSMCLK();

        DCOCTL = 0;
        BCSCTL1 = CALBC1_8MHZ;
        DCOCTL = CALDCO_8MHZ;

        { volatile uint16_t n; for(n=0; n < 0xffff; n++); }
    }
};

/**
 * 1MHz BCS calibrated clock
 */
template<>
struct CLK_t<1000000UL> {
    static void init() {
        DefaultBCSMCLK::OutputSMCLK();

        DCOCTL = 0;
        BCSCTL1 = CALBC1_1MHZ;
        DCOCTL = CALDCO_1MHZ;
    }
};

/**
 * 8MHz CS+ calibrated clock found on FRAM chip
 */
template<>
struct CLK_t<8000000UL, FraunchpadDebugClockTraits> {
    static void init() {
#ifdef __MSP430_HAS_CS__
        FraunchpadDebugClockTraits::OutputSMCLK();
        // Use 8MHz DCO factory calibration

        CSCTL0_H = 0xA5;// CS_KEY
        CSCTL1 |= DCOFSEL0 | DCOFSEL1;// Set max. DCO setting
        CSCTL2 = SELA_3 | SELS_3 | SELM_3;// set ACLK = MCLK = DCO
        CSCTL3 = DIVA_0 | DIVS_0 | DIVM_0;// set all dividers
        CSCTL0_H = 0x01;// Lock Register

        { volatile uint16_t n; for(n=0; n < 0xffff; n++); }
#endif
    }
};

/**
 * 24MHz CS+ calibrated clock found on FRAM chip
 */
template<>
struct CLK_t<24000000UL, FraunchpadDebugClockTraits> {
    static void init() {
#ifdef __MSP430_HAS_CS__
        FraunchpadDebugClockTraits::OutputSMCLK();

        CSCTL0_H = 0xA5; // CS_KEY
        CSCTL1 |= DCORSEL | DCOFSEL0 | DCOFSEL1;// Set max. DCO setting
        CSCTL2 = SELA_3 + SELS_3 + SELM_3;// set ACLK = MCLK = DCO
        CSCTL3 = DIVA_0 + DIVS_0 + DIVM_0;// set all dividers
        CSCTL0_H = 0x01;// Lock Register
        { volatile uint16_t n; for (n = 0; n < 0xffff; n++); }
#endif
    }
};

#endif /* CLOCK_T_H_ */