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  1. clock enable_cnt prepare_cnt rate accuracy phase
  2. ----------------------------------------------------------------------------------------
  3. spi0.1-tx_lo_dummy 0 0 1200000000 0 0
  4. spi0.1-rx_lo_dummy 0 0 1200000000 0 0
  5. spi0.0-tx_lo_dummy 0 0 1200000000 0 0
  6. spi0.0-rx_lo_dummy 0 0 1200000000 0 0
  7. clock-generator3 0 0 148499999 0 0
  8. clock-generator2 0 0 299999997 0 0
  9. ad9361_ext_refclk 8 8 10000000 0 0
  10. spi0.1-bb_refclk 1 1 20000000 0 0
  11. spi0.1-bbpll_clk 1 1 960000000 0 0
  12. spi0.1-adc_clk 1 1 480000000 0 0
  13. spi0.1-dac_clk 1 1 240000000 0 0
  14. spi0.1-t2_clk 1 1 120000000 0 0
  15. spi0.1-t1_clk 1 1 60000000 0 0
  16. spi0.1-clktf_clk 1 1 60000000 0 0
  17. spi0.1-tx_sampl_clk 1 1 60000000 0 0
  18. spi0.1-r2_clk 0 0 240000000 0 0
  19. spi0.1-r1_clk 0 0 120000000 0 0
  20. spi0.1-clkrf_clk 0 0 60000000 0 0
  21. spi0.1-rx_sampl_clk 0 0 60000000 0 0
  22. spi0.1-rx_refclk 1 1 20000000 0 0
  23. spi0.1-rx_rfpll_int 1 1 1200000000 0 0
  24. spi0.1-rx_rfpll 1 1 1200000000 0 0
  25. spi0.1-tx_refclk 1 1 20000000 0 0
  26. spi0.1-tx_rfpll_int 1 1 1200000000 0 0
  27. spi0.1-tx_rfpll 1 1 1200000000 0 0
  28. spi0.0-bb_refclk 1 1 20000000 0 0
  29. spi0.0-bbpll_clk 1 1 960000000 0 0
  30. spi0.0-adc_clk 1 1 480000000 0 0
  31. spi0.0-dac_clk 1 1 240000000 0 0
  32. spi0.0-t2_clk 1 1 120000000 0 0
  33. spi0.0-t1_clk 1 1 60000000 0 0
  34. spi0.0-clktf_clk 1 1 60000000 0 0
  35. spi0.0-tx_sampl_clk 1 1 60000000 0 0
  36. spi0.0-r2_clk 0 0 240000000 0 0
  37. spi0.0-r1_clk 0 0 120000000 0 0
  38. spi0.0-clkrf_clk 0 0 60000000 0 0
  39. spi0.0-rx_sampl_clk 0 0 60000000 0 0
  40. spi0.0-rx_refclk 1 1 20000000 0 0
  41. spi0.0-rx_rfpll_int 1 1 606299998 0 0
  42. spi0.0-rx_rfpll 1 1 606299998 0 0
  43. spi0.0-tx_refclk 1 1 20000000 0 0
  44. spi0.0-tx_rfpll_int 1 1 1200000000 0 0
  45. spi0.0-tx_rfpll 1 1 1200000000 0 0
  46. dp_aclk 1 1 100000000 100 0
  47. aux_ref_clk 0 0 27000000 0 0
  48. gt_crx_ref_clk 0 0 108000000 0 0
  49. pss_alt_ref_clk 0 0 0 0 0
  50. video_clk 0 0 27000000 0 0
  51. pss_ref_clk 3 3 33330000 0 0
  52. vpll_post_src 0 0 33330000 0 0
  53. vpll_pre_src 0 0 33330000 0 0
  54. vpll_int 0 0 2999700000 0 0
  55. vpll_half 0 0 1499850000 0 0
  56. vpll_int_mux 0 0 1499850000 0 0
  57. vpll 0 0 1499850000 0 0
  58. dp_video_ref_mux 0 0 1499850000 0 0
  59. dp_video_ref_div1 0 0 299970000 0 0
  60. dp_video_ref_div2 0 0 299970000 0 0
  61. dp_video_ref 0 0 299970000 0 0
  62. vpll_to_lpd 0 0 499950000 0 0
  63. dpll_post_src 0 0 33330000 0 0
  64. dpll_pre_src 0 0 33330000 0 0
  65. dpll_int 0 0 2133120000 0 0
  66. dpll_half 0 0 1066560000 0 0
  67. dpll_int_mux 0 0 1066560000 0 0
  68. dpll 0 0 1066560000 0 0
  69. dpll_to_lpd 0 0 533280000 0 0
  70. apll_post_src 0 0 33330000 0 0
  71. apll_pre_src 1 1 33330000 0 0
  72. apll_int 1 1 2399760000 0 0
  73. apll_half 1 1 1199880000 0 0
  74. apll_int_mux 1 1 1199880000 0 0
  75. apll 1 1 1199880000 0 0
  76. dpdma_ref_mux 1 1 1199880000 0 0
  77. dpdma_ref_div1 1 1 599940000 0 0
  78. dpdma_ref 1 1 599940000 0 0
  79. gdma_ref_mux 0 0 1199880000 0 0
  80. gdma_ref_div1 0 0 599940000 0 0
  81. gdma_ref 0 0 599940000 0 0
  82. acpu_mux 0 0 1199880000 0 0
  83. acpu 0 0 1199880000 0 0
  84. rpll_post_src 0 0 33330000 0 0
  85. rpll_pre_src 1 1 33330000 0 0
  86. rpll_int 1 1 2408447994 0 0
  87. rpll_half 1 1 1204223997 0 0
  88. rpll_int_mux 1 1 1204223997 0 0
  89. rpll 2 2 1204223997 0 0
  90. spi1_ref_mux 0 0 1204223997 0 0
  91. spi1_ref_div1 0 0 100352000 0 0
  92. spi1_ref_div2 0 0 100352000 0 0
  93. spi1_ref 0 0 100352000 0 0
  94. spi0_ref_mux 1 1 1204223997 0 0
  95. spi0_ref_div1 1 1 100352000 0 0
  96. spi0_ref_div2 1 1 100352000 0 0
  97. spi0_ref 1 1 100352000 0 0
  98. rpll_to_fpd 1 1 24576000 0 0
  99. dp_stc_ref_mux 0 0 24576000 0 0
  100. dp_stc_ref_div1 0 0 1638400 0 0
  101. dp_stc_ref_div2 0 0 1638400 0 0
  102. dp_stc_ref 0 0 1638400 0 0
  103. dp_audio_ref_mux 1 1 24576000 0 0
  104. dp_audio_ref_div1 1 1 24576000 0 0
  105. dp_audio_ref_div2 1 1 24576000 0 0
  106. dp_audio_ref 1 1 24576000 0 0
  107. iopll_post_src 0 0 33330000 0 0
  108. iopll_pre_src 1 1 33330000 0 0
  109. iopll_int 1 1 2999700000 0 0
  110. iopll_half 1 1 1499850000 0 0
  111. iopll_int_mux 1 1 1499850000 0 0
  112. iopll 10 14 1499850000 0 0
  113. gem3_ref_ung_mux 1 1 1499850000 0 0
  114. gem3_ref_ung_div1 1 1 124987500 0 0
  115. gem3_ref_ung 1 1 124987500 0 0
  116. gem3_ref 2 2 124987500 0 0
  117. gem3_tx 1 1 124987500 0 0
  118. gem2_ref_ung_mux 0 0 1499850000 0 0
  119. gem2_ref_ung_div1 0 0 62493750 0 0
  120. gem2_ref_ung 0 0 62493750 0 0
  121. gem2_ref 0 0 62493750 0 0
  122. gem2_tx 0 0 62493750 0 0
  123. gem1_ref_ung_mux 0 0 1499850000 0 0
  124. gem1_ref_ung_div1 0 0 62493750 0 0
  125. gem1_ref_ung 0 0 62493750 0 0
  126. gem1_ref 0 0 62493750 0 0
  127. gem1_tx 0 0 62493750 0 0
  128. gem0_ref_ung_mux 0 0 1499850000 0 0
  129. gem0_ref_ung_div1 0 0 62493750 0 0
  130. gem0_ref_ung 0 0 62493750 0 0
  131. gem0_ref 0 0 62493750 0 0
  132. gem0_tx 0 0 62493750 0 0
  133. pl3_ref_mux 0 0 1499850000 0 0
  134. pl3_ref_div1 0 0 46870313 0 0
  135. pl3_ref_div2 0 0 9374063 0 0
  136. pl3_ref 0 0 9374063 0 0
  137. pl2_ref_mux 1 1 1499850000 0 0
  138. pl2_ref_div1 1 1 499950000 0 0
  139. pl2_ref_div2 1 1 499950000 0 0
  140. pl2_ref 3 3 499950000 0 0
  141. pl1_ref_mux 0 0 1499850000 0 0
  142. pl1_ref_div1 0 0 249975000 0 0
  143. pl1_ref_div2 0 0 249975000 0 0
  144. pl1_ref 0 0 249975000 0 0
  145. pl0_ref_mux 1 1 1499850000 0 0
  146. pl0_ref_div1 1 1 99990000 0 0
  147. pl0_ref_div2 1 1 99990000 0 0
  148. pl0_ref 1 1 99990000 0 0
  149. ams_ref_mux 1 1 1499850000 0 0
  150. ams_ref_div1 1 1 49995000 0 0
  151. ams_ref_div2 1 1 49995000 0 0
  152. ams_ref 1 1 49995000 0 0
  153. adma_ref_mux 0 0 1499850000 0 0
  154. adma_ref_div1 0 0 499950000 0 0
  155. adma_ref 0 0 499950000 0 0
  156. can1_ref_mux 0 0 1499850000 0 0
  157. can1_ref_div1 0 0 99990000 0 0
  158. can1_ref_div2 0 0 99990000 0 0
  159. can1_ref 0 0 99990000 0 0
  160. can1 0 0 99990000 0 0
  161. can0_ref_mux 0 0 1499850000 0 0
  162. can0_ref_div1 0 0 46870313 0 0
  163. can0_ref_div2 0 0 46870313 0 0
  164. can0_ref 0 0 46870313 0 0
  165. can0 0 0 46870313 0 0
  166. i2c1_ref_mux 0 1 1499850000 0 0
  167. i2c1_ref_div1 0 1 99990000 0 0
  168. i2c1_ref_div2 0 1 99990000 0 0
  169. i2c1_ref 0 1 99990000 0 0
  170. i2c0_ref_mux 0 1 1499850000 0 0
  171. i2c0_ref_div1 0 1 99990000 0 0
  172. i2c0_ref_div2 0 1 99990000 0 0
  173. i2c0_ref 0 1 99990000 0 0
  174. nand_ref_mux 0 0 1499850000 0 0
  175. nand_ref_div1 0 0 46870313 0 0
  176. nand_ref_div2 0 0 9374063 0 0
  177. nand_ref 0 0 9374063 0 0
  178. uart1_ref_mux 0 1 1499850000 0 0
  179. uart1_ref_div1 0 1 99990000 0 0
  180. uart1_ref_div2 0 1 99990000 0 0
  181. uart1_ref 0 1 99990000 0 0
  182. uart0_ref_mux 1 1 1499850000 0 0
  183. uart0_ref_div1 1 1 99990000 0 0
  184. uart0_ref_div2 1 1 99990000 0 0
  185. uart0_ref 1 1 99990000 0 0
  186. sdio1_ref_mux 1 1 1499850000 0 0
  187. sdio1_ref_div1 1 1 187481250 0 0
  188. sdio1_ref_div2 1 1 187481250 0 0
  189. sdio1_ref 1 1 187481250 0 0
  190. sdio0_ref_mux 0 0 1499850000 0 0
  191. sdio0_ref_div1 0 0 99990000 0 0
  192. sdio0_ref_div2 0 0 99990000 0 0
  193. sdio0_ref 0 0 99990000 0 0
  194. qspi_ref_mux 0 1 1499850000 0 0
  195. qspi_ref_div1 0 1 124987500 0 0
  196. qspi_ref_div2 0 1 124987500 0 0
  197. qspi_ref 0 1 124987500 0 0
  198. gem_tsu_ref_mux 1 1 1499850000 0 0
  199. gem_tsu_ref_div1 1 1 249975000 0 0
  200. gem_tsu_ref_div2 1 1 249975000 0 0
  201. gem_tsu_ref 1 1 249975000 0 0
  202. gem_tsu 1 1 249975000 0 0
  203. usb3_dual_ref_mux 1 1 1499850000 0 0
  204. usb3_dual_ref_div1 1 1 59994000 0 0
  205. usb3_dual_ref_div2 1 1 19998000 0 0
  206. usb3_dual_ref 1 1 19998000 0 0
  207. usb1_bus_ref_mux 0 0 1499850000 0 0
  208. usb1_bus_ref_div1 0 0 124987500 0 0
  209. usb1_bus_ref_div2 0 0 124987500 0 0
  210. usb1_bus_ref 0 0 124987500 0 0
  211. usb0_bus_ref_mux 1 1 1499850000 0 0
  212. usb0_bus_ref_div1 1 1 249975000 0 0
  213. usb0_bus_ref_div2 1 1 249975000 0 0
  214. usb0_bus_ref 1 1 249975000 0 0
  215. iopll_to_fpd 3 3 499950000 0 0
  216. topsw_lsbus_mux 1 1 499950000 0 0
  217. topsw_lsbus_div1 1 1 99990000 0 0
  218. topsw_lsbus 1 1 99990000 0 0
  219. wdt 2 2 99990000 0 0
  220. gpu_ref_mux 0 0 499950000 0 0
  221. gpu_ref_div1 0 0 499950000 0 0
  222. gpu_ref 0 0 499950000 0 0
  223. gpu_pp1_ref 0 0 499950000 0 0
  224. gpu_pp0_ref 0 0 499950000 0 0
  225. pcie_ref_mux 1 1 499950000 0 0
  226. pcie_ref_div1 1 1 249975000 0 0
  227. pcie_ref 1 1 249975000 0 0
  228. sata_ref_mux 1 1 499950000 0 0
  229. sata_ref_div1 1 1 249975000 0 0
  230. sata_ref 1 1 249975000 0 0
  231. can1_mio 0 0 0 0 0
  232. can0_mio 0 0 0 0 0
  233. gem3_rx 1 1 0 0 0
  234. gem2_rx 0 0 0 0 0
  235. gem1_rx 0 0 0 0 0
  236. gem0_rx 0 0 0 0 0
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