licznik_source

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity module1 is
	Port ( clk : in STD_LOGIC;
			 res : in STD_LOGIC;
			 outmod : out STD_LOGIC_VECTOR(3 downto 0));
end module1;

architecture Behavioral of module1 is
signal counter : STD_LOGIC_VECTOR (3 downto 0);
begin
	process(clk,res)
	begin
	if(rising_edge(clk)) then
		if(res='1') then
			counter <= x"0";
		else
			counter <= counter - x"1";
		end if;
	end if;
	end process;
	outmod <= counter;
end architecture;