.gate SB_DFFER C=clk_slow D=tgen_I.v_mux[0] E=tgen_I.v_ce Q=tgen_I.v_cnt[0] R=sysmgr_I.rst_out
.attr module_not_derived 00000000000000000000000000000001
.attr src "top.v:61|tgen.v:127|/opt/icestorm/bin/../share/yosys/ice40/cells_map.v:27"
.gate SB_DFFER C=clk_slow D=tgen_I.v_mux[1] E=$abc$1831$n43 Q=tgen_I.v_cnt[1] R=sysmgr_I.rst_out
.attr module_not_derived 00000000000000000000000000000001
.attr src "top.v:61|tgen.v:127|/opt/icestorm/bin/../share/yosys/ice40/cells_map.v:27"
.gate SB_DFFER C=clk_slow D=tgen_I.v_mux[2] E=tgen_I.v_ce Q=tgen_I.v_cnt[2] R=sysmgr_I.rst_out
.attr module_not_derived 00000000000000000000000000000001
.attr src "top.v:61|tgen.v:127|/opt/icestorm/bin/../share/yosys/ice40/cells_map.v:27"


    always @(posedge clk or posedge rst)
        if (rst)
            v_cnt <= 0;
        else if (v_ce)
            v_cnt <= v_mux;