MnMWizard

verilog problem 1

Jan 31st, 2021
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  1. `timescale 1ns / 1ps
  2.  
  3. //I changed the source node properties from Verilog to SystemVerilog so I could use arrays when creating inputs/outputs
  4.  
  5.  
  6. module VerilogFile(input sw[15:0], output MOTOR, output ENA, output ENB, output LED[15:0]);
  7. //Remember some sw[ ], atm 2 through 5, will not be used bc the ports will be linked to SWpos 0-3 in the master
  8.  
  9. assign ENA = sw[0];
  10. assign LED[1] = sw[0];
  11. assign LED[2] = sw[0]; //testing some stuff out
  12.  
  13. endmodule
  14.  
  15.  
  16.  
  17.   //  input [11:4] sw,
  18.    
  19. module PWM(
  20. input clock,
  21. input[3:0] SWpos, //this starts at SW2 since we're using sw[0] and sw[1] for etc.
  22. output PWM //motor "power" signal
  23.     );
  24.    
  25. reg[9:0]counter;// 2^(num of bits) = 1024
  26. reg[9:0]width;
  27. reg PWMtemp;
  28.  
  29.     initial begin
  30.         counter = 0;
  31.         width =0;
  32.         PWMtemp = 0;
  33.      end
  34.      
  35.      always@(posedge clock)begin
  36.         if(counter == 1000) //resets the counter to 0 or increments
  37.        // if(counter == 16)
  38.             counter <= 0;
  39.          else
  40.             counter <= counter +1;
  41.            
  42.         if(counter < width) begin
  43.             PWMtemp <= 1;
  44.             end
  45.            
  46.         else begin
  47.             PWMtemp <=0;
  48.          end    
  49.     end
  50. //The above if/else sets the "power" to be on whenever counter is less
  51. //  than width. The value for width is set based on SWpos below.
  52.    
  53.     always@(*)begin //not sure what * means as a sensitivity parameter but it works
  54.         case(SWpos)
  55.                 //might add more cases later to account for sw[1] being an on/off switch
  56.                 //Syntax is this - - -  (in the case that SWpos is this):(set width = ___)
  57.                  
  58.                 4'b0000:width = 10'd0;
  59.                 4'b0001:width = 10'd250;
  60.                 4'b0010:width = 10'd250;
  61.                 4'b0100:width = 10'd250;
  62.                 4'b1000:width = 10'd250;
  63.                
  64.                 4'b0011:width = 10'd500;
  65.                 4'b0110:width = 10'd500;
  66.                 4'b1100:width = 10'd500;
  67.                
  68.                 4'b0111:width = 10'd750;
  69.                 4'b1110:width = 10'd750;
  70.                
  71.                 4'b1111:width = 10'd999;
  72.                 default:width = 10'd0;
  73.  
  74.  
  75.         endcase
  76.  
  77.  end
  78.        
  79.  assign PWM = PWMtemp;
  80.    
  81. endmodule
  82.  
  83.  
  84. /*
  85. module disp(
  86.      input clk,
  87.      output reg [3:0] an,      // 4 Digits on Basys 3 Board
  88.      output reg [6:0] seg    // 7 Segment Display
  89.      );
  90.  
  91.      // Use the 2 MSBs of 19-bit counter to create 190 Hz frequency refresh
  92.      reg [18:0] count;
  93.      always @ (posedge clk)
  94.           count = count + 1;
  95.  
  96.      // This wire is driven by the 2 MSBs of the counter. We'll use it to
  97.      // refresh the display.
  98.      wire [1:0] refresh;
  99.      assign refresh = count[18:17];
  100.  
  101.      // Usually always @ * is not recommended because it's resource intensive
  102.      // and usually unnecessary, and if you're not careful it will cause timing
  103.      // issues. This isn't an issue for a simple program like this though.
  104.      always @ (*)
  105.      if (SW1 = 0)
  106.           case(refresh)
  107.           2'b00:
  108.                begin
  109.                     an = 4'b0111;
  110.                     seg = 7'b0000111;
  111.                end
  112.           2'b01:
  113.                begin
  114.                     an = 4'b1011;
  115.                     seg = 7'0000111;
  116.                end
  117.           2'b10:
  118.                begin
  119.                     an = 4'b1101;
  120.                     seg = 7'b0000000;
  121.                end
  122.           2'b11:
  123.                begin
  124.                     an = 4'b1110;
  125.                     seg = 7'b0000000;
  126.                end
  127.           endcase
  128.     else case(refresh)
  129.           2'b00:
  130.                begin
  131.                     an = 4'b0111;
  132.                     seg = 7'b0000111;
  133.                end
  134.           2'b01:
  135.                begin
  136.                     an = 4'b1011;
  137.                     seg = 7'0000000;
  138.                end
  139.           2'b10:
  140.                begin
  141.                     an = 4'b1101;
  142.                     seg = 7'b0000000;
  143.                end
  144.           2'b11:
  145.                begin
  146.                     an = 4'b1110;
  147.                     seg = 7'b0000000;
  148.                end
  149.           endcase
  150. */
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