iuliaa

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Dec 11th, 2019
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  1. module rgst #(
  2. parameter w = 8 //register's width
  3. )(
  4. input clk,
  5. input rst_b, //asynchronous reset; active low
  6. input [w-1:0] d,
  7. input ld,
  8. input clr, //synchronous reset; active high
  9. output reg [w-1:0] q
  10. );
  11.  
  12. always @ (posedge clk, negedge rst_b)
  13. if (!rst_b)
  14. q <= 1'd0;
  15. else if (clr)
  16. q <= 1'd0;
  17. else if (ld)
  18. q <= d;
  19. endmodule
  20.  
  21. module atan_const (input [3:0] itr, output reg [15:0] atan);
  22. always @ (*)
  23. case (itr)
  24. 4'd0: atan = 16'h3244;
  25. 4'd1: atan = 16'h1dac;
  26. 4'd2: atan = 16'h0fae;
  27. 4'd3: atan = 16'h07f5;
  28. 4'd4: atan = 16'h03ff;
  29. 4'd5: atan = 16'h0200;
  30. 4'd6: atan = 16'h0100;
  31. 4'd7: atan = 16'h0080;
  32. 4'd8: atan = 16'h0040;
  33. 4'd9: atan = 16'h0020;
  34. 4'd10: atan = 16'h0010;
  35. 4'd11: atan = 16'h0008;
  36. 4'd12: atan = 16'h0004;
  37. 4'd13: atan = 16'h0002;
  38. 4'd14: atan = 16'h0001;
  39. default:atan = 16'h0000;
  40. endcase
  41. endmodule
  42.  
  43. module cntr #(parameter w=8)(input clk, rst_b, c_up, clr, output reg [w-1] q);
  44. always @ (posedge clk, negedge rst_b)
  45. if (!rst_b)
  46. q <= 1'd0;
  47. else if (clr)
  48. q <= 1'd0;
  49. else
  50. q<=q+c_up;
  51. endmodule
  52.  
  53. module add_sub (input [15:0] a, b,input s, output [15:0] o);
  54. assign o = s ? a-b : a+b;
  55. endmodule
  56.  
  57. module arsh (input [15:0] a, input [3:0] i, output [15:0] o);
  58. assign o=$unsigned($signed(a)>>>i);
  59. endmodule
  60.  
  61. module cntr_u(input clk, rst_b, bgn, [3:0] itr, output fin, ld, init);
  62. reg [2:0] st; wire [2;0] st_next;
  63. assign st_next[0] = st[0]&~bgn|st[2];
  64. assign st_next[1] = st[0]& bgn | st[1] &(itr!=4'd15);
  65. assign st_next[2] = st[1]&(itr==4'd15);
  66. assign init =st[0]& bgn;
  67. assign ld=st[0]&bgn|st[1];
  68. assign fin = st[2];
  69. always @ (posedge clk,negedge rst_b)
  70. if(!rst_b)
  71. st<=3'd1;
  72. else
  73. st<=st_next;
  74. endmodule
  75.  
  76. module cordic (input clk, rst_b, bgn, [15:0] theta, output fin , [15:0] cos);
  77. wire [15:0] x_new, x_out, y_new, y_out,z_new, z_out,atan,x_rsh,y_rsh;
  78. wire [3:0] i;
  79. wire init, ld;
  80. ctrl_u u0(.clk(clk),.rst_b(rst_b),.bgn(bgn),.itr(i),.fin(fin), .ld(ld),.init(init));
  81. cntr #(.w(4)) u1(.clk(clk),.rst_b(rst_b),.c_up(ld),.clr(init),.q(i));
  82. atan_const u2(.itr(i),.atan(atan));
  83. rgst #(.w(16)) u3(.clk(clk),.rst_b(rst_b),.ld(ld),.clr(1'd0),.d(x_new),.q(x_out));
  84. arsh u4(.a(y_out),.o(y_rsh));
  85. add_sub u5(.a(x_out), .b(y_rsh),.s(~z_out[15]),.o(x_new));
  86. rgst #(.w(16)) u6(.clk(clk),.rst_b(rst_b),.ld(ld),.clr(1'd0),.d(y_new),.q(y_out));
  87. arsh u7(.a(x_out),.o(x_rsh));
  88. add_sub u8(.a(y_out), .b(x_rsh),.s(z_out[15]),.o(y_new));
  89. rgst #(.w(16)) u9(.clk(clk),.rst_b(rst_b),.ld(ld),.clr(1'd0),.d(z_new),.q(z_out));
  90. add_sub u10(.a(z_out), .b(atan),.s(~z_out[15]),.o(z_new));
  91. assign cos+fin?x_out:16'bz;
  92. endmodule
  93.  
  94. module cordic_tb(output reg clk, rst_b, bgn, [15:0] theta,output fin, [15:0] cos);
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