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--
-- Create Date:    08:51:24 11/21/2019
-- Design Name:
-- Module Name:    uklad - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity uklad is
    Port ( x : in  STD_LOGIC_VECTOR (2 downto 0);
           y : out  STD_LOGIC_VECTOR (1 downto 0));
end uklad;

architecture Behavioral of uklad is

	-- y0(x2,x1,x0)=suma(1,2,4,6), y1(x2,x1,x0)=suma(3,5,6,7)
begin
	y(0) <= 	(not x(2) and not x(1) and x(0)) or -- 1
				(not x(2) and x(1) and not x(0)) or -- 2
				(x(2) and not x(1) and not x(0)) or -- 4
				(x(2) and x(1) and x(0)); -- 7

	y(1) <= 	(not x(2) and x(1) and x(0)) or -- 3
				(x(2) and not x(1) and x(0)) or -- 5
				(x(2) and x(1) and not x(0)) or -- 6
				(x(2) and x(1) and x(0)); -- 7

end Behavioral;