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  1. / {
  2. #address-cells = <0x00000002>;
  3. #size-cells = <0x00000002>;
  4. compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
  5. interrupt-parent = <0x00000001>;
  6. model = "TI AM5728 BeagleBoard-X15 rev C";
  7. chosen {
  8. stdout-path = "/ocp/interconnect@48000000/segment@0/target-module@20000/serial@0";
  9. };
  10. aliases {
  11. i2c0 = "/ocp/interconnect@48000000/segment@0/target-module@70000/i2c@0";
  12. i2c1 = "/ocp/interconnect@48000000/segment@0/target-module@72000/i2c@0";
  13. i2c2 = "/ocp/interconnect@48000000/segment@0/target-module@60000/i2c@0";
  14. i2c3 = "/ocp/interconnect@48000000/segment@0/target-module@7a000/i2c@0";
  15. i2c4 = "/ocp/interconnect@48000000/segment@0/target-module@7c000/i2c@0";
  16. serial0 = "/ocp/interconnect@48000000/segment@0/target-module@6a000/serial@0";
  17. serial1 = "/ocp/interconnect@48000000/segment@0/target-module@6c000/serial@0";
  18. serial2 = "/ocp/interconnect@48000000/segment@0/target-module@20000/serial@0";
  19. serial3 = "/ocp/interconnect@48000000/segment@0/target-module@6e000/serial@0";
  20. serial4 = "/ocp/interconnect@48000000/segment@0/target-module@66000/serial@0";
  21. serial5 = "/ocp/interconnect@48000000/segment@0/target-module@68000/serial@0";
  22. serial6 = "/ocp/interconnect@48400000/segment@0/target-module@20000/serial@0";
  23. serial7 = "/ocp/interconnect@48400000/segment@0/target-module@22000/serial@0";
  24. serial8 = "/ocp/interconnect@48400000/segment@0/target-module@24000/serial@0";
  25. serial9 = "/ocp/interconnect@4ae00000/segment@20000/target-module@b000/serial@0";
  26. ethernet0 = "/ocp/interconnect@48400000/segment@0/target-module@84000/ethernet@0/slave@200";
  27. ethernet1 = "/ocp/interconnect@48400000/segment@0/target-module@84000/ethernet@0/slave@300";
  28. d_can0 = "/ocp/interconnect@4ae00000/segment@30000/target-module@c000/can@0";
  29. d_can1 = "/ocp/interconnect@48400000/segment@0/target-module@80000/can@0";
  30. spi0 = "/ocp/spi@4b300000";
  31. rtc0 = "/ocp/interconnect@48000000/segment@0/target-module@60000/i2c@0/rtc@6f";
  32. rtc1 = "/ocp/interconnect@48000000/segment@0/target-module@70000/i2c@0/tps659038@58/tps659038_rtc";
  33. rtc2 = "/ocp/interconnect@48800000/segment@0/target-module@38000/rtc@0";
  34. display0 = "/connector";
  35. };
  36. timer {
  37. compatible = "arm,armv7-timer";
  38. interrupts = <0x00000001 0x0000000d 0x00000308 0x00000001 0x0000000e 0x00000308 0x00000001 0x0000000b 0x00000308 0x00000001 0x0000000a 0x00000308>;
  39. interrupt-parent = <0x00000002>;
  40. };
  41. interrupt-controller@48211000 {
  42. compatible = "arm,cortex-a15-gic";
  43. interrupt-controller;
  44. #interrupt-cells = <0x00000003>;
  45. reg = <0x00000000 0x48211000 0x00000000 0x00001000 0x00000000 0x48212000 0x00000000 0x00002000 0x00000000 0x48214000 0x00000000 0x00002000 0x00000000 0x48216000 0x00000000 0x00002000>;
  46. interrupts = <0x00000001 0x00000009 0x00000304>;
  47. interrupt-parent = <0x00000002>;
  48. phandle = <0x00000002>;
  49. };
  50. interrupt-controller@48281000 {
  51. compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
  52. interrupt-controller;
  53. #interrupt-cells = <0x00000003>;
  54. reg = <0x00000000 0x48281000 0x00000000 0x00001000>;
  55. interrupt-parent = <0x00000002>;
  56. phandle = <0x00000008>;
  57. };
  58. cpus {
  59. #address-cells = <0x00000001>;
  60. #size-cells = <0x00000000>;
  61. cpu@0 {
  62. device_type = "cpu";
  63. compatible = "arm,cortex-a15";
  64. reg = <0x00000000>;
  65. operating-points-v2 = <0x00000003>;
  66. clocks = <0x00000004>;
  67. clock-names = "cpu";
  68. clock-latency = <0x000493e0>;
  69. #cooling-cells = <0x00000002>;
  70. vbb-supply = <0x00000005>;
  71. vdd-supply = <0x00000006>;
  72. voltage-tolerance = <0x00000001>;
  73. phandle = <0x000000ce>;
  74. };
  75. cpu@1 {
  76. device_type = "cpu";
  77. compatible = "arm,cortex-a15";
  78. reg = <0x00000001>;
  79. operating-points-v2 = <0x00000003>;
  80. clocks = <0x00000004>;
  81. clock-names = "cpu";
  82. clock-latency = <0x000493e0>;
  83. #cooling-cells = <0x00000002>;
  84. vbb-supply = <0x00000005>;
  85. };
  86. };
  87. opp-table {
  88. compatible = "operating-points-v2-ti-cpu";
  89. syscon = <0x00000007>;
  90. opp-shared;
  91. phandle = <0x00000003>;
  92. opp_nom-1000000000 {
  93. opp-hz = <0x00000000 0x3b9aca00>;
  94. opp-microvolt = <0x00102ca0 0x000cf850 0x00118c30 0x00102ca0 0x000cf850 0x00118c30>;
  95. opp-supported-hw = <0x000000ff 0x00000001>;
  96. opp-suspend;
  97. };
  98. opp_od-1176000000 {
  99. opp-hz = <0x00000000 0x46185600>;
  100. opp-microvolt = <0x0011b340 0x000d8108 0x0011b340 0x0011b340 0x000d8108 0x0011b340>;
  101. opp-supported-hw = <0x000000ff 0x00000002>;
  102. };
  103. opp_high@1500000000 {
  104. opp-hz = <0x00000000 0x59682f00>;
  105. opp-microvolt = <0x00127690 0x000e7ef0 0x001312d0 0x00127690 0x000e7ef0 0x001312d0>;
  106. opp-supported-hw = <0x000000ff 0x00000004>;
  107. };
  108. };
  109. soc {
  110. compatible = "ti,omap-infra";
  111. mpu {
  112. compatible = "ti,omap5-mpu";
  113. ti,hwmods = "mpu";
  114. };
  115. };
  116. ocp {
  117. compatible = "ti,dra7-l3-noc", "simple-bus";
  118. #address-cells = <0x00000001>;
  119. #size-cells = <0x00000001>;
  120. ranges = <0x00000000 0x00000000 0x00000000 0xc0000000>;
  121. ti,hwmods = "l3_main_1", "l3_main_2";
  122. reg = <0x00000000 0x44000000 0x00000000 0x01000000 0x00000000 0x45000000 0x00000000 0x00001000>;
  123. interrupts-extended = <0x00000001 0x00000000 0x00000004 0x00000004 0x00000008 0x00000000 0x0000000a 0x00000004>;
  124. interconnect@4a000000 {
  125. compatible = "ti,dra7-l4-cfg", "simple-bus";
  126. reg = <0x4a000000 0x00000800 0x4a000800 0x00000800 0x4a001000 0x00001000>;
  127. reg-names = "ap", "la", "ia0";
  128. #address-cells = <0x00000001>;
  129. #size-cells = <0x00000001>;
  130. ranges = <0x00000000 0x4a000000 0x00100000 0x00100000 0x4a100000 0x00100000 0x00200000 0x4a200000 0x00100000>;
  131. segment@0 {
  132. compatible = "simple-bus";
  133. #address-cells = <0x00000001>;
  134. #size-cells = <0x00000001>;
  135. ranges = * 0x83001068 [0x0000015c];
  136. target-module@2000 {
  137. compatible = "ti,sysc-omap4", "ti,sysc";
  138. reg = <0x00002000 0x00000004>;
  139. reg-names = "rev";
  140. #address-cells = <0x00000001>;
  141. #size-cells = <0x00000001>;
  142. ranges = <0x00000000 0x00002000 0x00002000>;
  143. scm@0 {
  144. compatible = "ti,dra7-scm-core", "simple-bus";
  145. reg = <0x00000000 0x00002000>;
  146. #address-cells = <0x00000001>;
  147. #size-cells = <0x00000001>;
  148. ranges = <0x00000000 0x00000000 0x00002000>;
  149. scm_conf@0 {
  150. compatible = "syscon", "simple-bus";
  151. reg = <0x00000000 0x00001400>;
  152. #address-cells = <0x00000001>;
  153. #size-cells = <0x00000001>;
  154. ranges = <0x00000000 0x00000000 0x00001400>;
  155. phandle = <0x00000009>;
  156. pbias_regulator@e00 {
  157. compatible = "ti,pbias-dra7", "ti,pbias-omap";
  158. reg = <0x00000e00 0x00000004>;
  159. syscon = <0x00000009>;
  160. pbias_mmc_omap5 {
  161. regulator-name = "pbias_mmc_omap5";
  162. regulator-min-microvolt = <0x001b7740>;
  163. regulator-max-microvolt = <0x00325aa0>;
  164. phandle = <0x0000009b>;
  165. };
  166. };
  167. phy-gmii-sel {
  168. compatible = "ti,dra7xx-phy-gmii-sel";
  169. reg = <0x00000554 0x00000004>;
  170. #phy-cells = <0x00000001>;
  171. phandle = <0x000000b4>;
  172. };
  173. clocks {
  174. #address-cells = <0x00000001>;
  175. #size-cells = <0x00000000>;
  176. dss_deshdcp_clk@558 {
  177. #clock-cells = <0x00000000>;
  178. compatible = "ti,gate-clock";
  179. clocks = <0x0000000a>;
  180. ti,bit-shift = <0x00000000>;
  181. reg = <0x00000558>;
  182. };
  183. ehrpwm0_tbclk@558 {
  184. #clock-cells = <0x00000000>;
  185. compatible = "ti,gate-clock";
  186. clocks = <0x0000000b>;
  187. ti,bit-shift = <0x00000014>;
  188. reg = <0x00000558>;
  189. phandle = <0x000000ae>;
  190. };
  191. ehrpwm1_tbclk@558 {
  192. #clock-cells = <0x00000000>;
  193. compatible = "ti,gate-clock";
  194. clocks = <0x0000000b>;
  195. ti,bit-shift = <0x00000015>;
  196. reg = <0x00000558>;
  197. phandle = <0x000000af>;
  198. };
  199. ehrpwm2_tbclk@558 {
  200. #clock-cells = <0x00000000>;
  201. compatible = "ti,gate-clock";
  202. clocks = <0x0000000b>;
  203. ti,bit-shift = <0x00000016>;
  204. reg = <0x00000558>;
  205. phandle = <0x000000b0>;
  206. };
  207. sys_32k_ck {
  208. #clock-cells = <0x00000000>;
  209. compatible = "ti,mux-clock";
  210. clocks = <0x0000000c 0x0000000d 0x0000000d 0x0000000d>;
  211. ti,bit-shift = <0x00000008>;
  212. reg = <0x000006c4>;
  213. phandle = <0x00000050>;
  214. };
  215. };
  216. };
  217. pinmux@1400 {
  218. compatible = "ti,dra7-padconf", "pinctrl-single";
  219. reg = <0x00001400 0x00000468>;
  220. #address-cells = <0x00000001>;
  221. #size-cells = <0x00000000>;
  222. #pinctrl-cells = <0x00000001>;
  223. #interrupt-cells = <0x00000001>;
  224. interrupt-controller;
  225. pinctrl-single,register-width = <0x00000020>;
  226. pinctrl-single,function-mask = <0x3fffffff>;
  227. phandle = <0x00000092>;
  228. mmc1_pins_default {
  229. pinctrl-single,pins = <0x00000354 0x00060000 0x00000358 0x00060000 0x0000035c 0x00060000 0x00000360 0x00060000 0x00000364 0x00060000 0x00000368 0x00060000>;
  230. phandle = <0x0000009c>;
  231. };
  232. mmc1_pins_sdr12 {
  233. pinctrl-single,pins = <0x00000354 0x00060000 0x00000358 0x00060000 0x0000035c 0x00060000 0x00000360 0x00060000 0x00000364 0x00060000 0x00000368 0x00060000>;
  234. phandle = <0x0000009f>;
  235. };
  236. mmc1_pins_hs {
  237. pinctrl-single,pins = <0x00000354 0x000601b0 0x00000358 0x000601b0 0x0000035c 0x000601b0 0x00000360 0x000601b0 0x00000364 0x000601b0 0x00000368 0x000601b0>;
  238. phandle = <0x0000009e>;
  239. };
  240. mmc1_pins_sdr25 {
  241. pinctrl-single,pins = <0x00000354 0x000601b0 0x00000358 0x000601b0 0x0000035c 0x000601b0 0x00000360 0x000601b0 0x00000364 0x000601b0 0x00000368 0x000601b0>;
  242. phandle = <0x000000a0>;
  243. };
  244. mmc1_pins_sdr50 {
  245. pinctrl-single,pins = <0x00000354 0x000601a0 0x00000358 0x000601a0 0x0000035c 0x000601a0 0x00000360 0x000601a0 0x00000364 0x000601a0 0x00000368 0x000601a0>;
  246. phandle = <0x000000a1>;
  247. };
  248. mmc1_pins_ddr50 {
  249. pinctrl-single,pins = <0x00000354 0x00060100 0x00000358 0x00060100 0x0000035c 0x00060100 0x00000360 0x00060100 0x00000364 0x00060100 0x00000368 0x00060100>;
  250. phandle = <0x000000a2>;
  251. };
  252. mmc1_pins_sdr104 {
  253. pinctrl-single,pins = <0x00000354 0x00060100 0x00000358 0x00060100 0x0000035c 0x00060100 0x00000360 0x00060100 0x00000364 0x00060100 0x00000368 0x00060100>;
  254. phandle = <0x000000a4>;
  255. };
  256. mmc2_pins_default {
  257. pinctrl-single,pins = * 0x83001b28 [0x00000050];
  258. phandle = <0x000000a7>;
  259. };
  260. mmc2_pins_hs {
  261. pinctrl-single,pins = * 0x83001bac [0x00000050];
  262. phandle = <0x000000a8>;
  263. };
  264. mmc2_pins_ddr_3_3v_rev11 {
  265. pinctrl-single,pins = * 0x83001c3c [0x00000050];
  266. };
  267. mmc2_pins_ddr_1_8v_rev11 {
  268. pinctrl-single,pins = * 0x83001cbc [0x00000050];
  269. };
  270. mmc2_pins_ddr_rev20 {
  271. pinctrl-single,pins = * 0x83001d34 [0x00000050];
  272. phandle = <0x000000a9>;
  273. };
  274. mmc2_pins_hs200 {
  275. pinctrl-single,pins = * 0x83001db8 [0x00000050];
  276. };
  277. mmc4_pins_default {
  278. pinctrl-single,pins = <0x000003e8 0x00060103 0x000003ec 0x00060103 0x000003f0 0x00060103 0x000003f4 0x00060103 0x000003f8 0x00060103 0x000003fc 0x00060103>;
  279. };
  280. mmc4_pins_hs {
  281. pinctrl-single,pins = <0x000003e8 0x00060103 0x000003ec 0x00060103 0x000003f0 0x00060103 0x000003f4 0x00060103 0x000003f8 0x00060103 0x000003fc 0x00060103>;
  282. };
  283. mmc3_pins_default {
  284. pinctrl-single,pins = <0x0000037c 0x00060000 0x00000380 0x00060000 0x00000384 0x00060000 0x00000388 0x00060000 0x0000038c 0x00060000 0x00000390 0x00060000>;
  285. };
  286. mmc3_pins_hs {
  287. pinctrl-single,pins = <0x0000037c 0x00060000 0x00000380 0x00060000 0x00000384 0x00060000 0x00000388 0x00060000 0x0000038c 0x00060000 0x00000390 0x00060000>;
  288. };
  289. mmc3_pins_sdr12 {
  290. pinctrl-single,pins = <0x0000037c 0x00060000 0x00000380 0x00060000 0x00000384 0x00060000 0x00000388 0x00060000 0x0000038c 0x00060000 0x00000390 0x00060000>;
  291. };
  292. mmc3_pins_sdr25 {
  293. pinctrl-single,pins = <0x0000037c 0x00060000 0x00000380 0x00060000 0x00000384 0x00060000 0x00000388 0x00060000 0x0000038c 0x00060000 0x00000390 0x00060000>;
  294. };
  295. mmc3_pins_sdr50 {
  296. pinctrl-single,pins = <0x0000037c 0x00060100 0x00000380 0x00060100 0x00000384 0x00060100 0x00000388 0x00060100 0x0000038c 0x00060100 0x00000390 0x00060100>;
  297. };
  298. mmc4_pins_sdr12 {
  299. pinctrl-single,pins = <0x000003e8 0x00060103 0x000003ec 0x00060103 0x000003f0 0x00060103 0x000003f4 0x00060103 0x000003f8 0x00060103 0x000003fc 0x00060103>;
  300. };
  301. mmc4_pins_sdr25 {
  302. pinctrl-single,pins = <0x000003e8 0x00060103 0x000003ec 0x00060103 0x000003f0 0x00060103 0x000003f4 0x00060103 0x000003f8 0x00060103 0x000003fc 0x00060103>;
  303. };
  304. };
  305. scm_conf@1c04 {
  306. compatible = "syscon";
  307. reg = <0x00001c04 0x00000020>;
  308. #syscon-cells = <0x00000002>;
  309. phandle = <0x000000bf>;
  310. };
  311. scm_conf@1c24 {
  312. compatible = "syscon";
  313. reg = <0x00001c24 0x00000024>;
  314. phandle = <0x0000005f>;
  315. };
  316. dma-router@b78 {
  317. compatible = "ti,dra7-dma-crossbar";
  318. reg = <0x00000b78 0x000000fc>;
  319. #dma-cells = <0x00000001>;
  320. dma-requests = <0x000000cd>;
  321. ti,dma-safe-map = <0x00000000>;
  322. dma-masters = <0x0000000e>;
  323. phandle = <0x00000091>;
  324. };
  325. dma-router@c78 {
  326. compatible = "ti,dra7-dma-crossbar";
  327. reg = <0x00000c78 0x0000007c>;
  328. #dma-cells = <0x00000002>;
  329. dma-requests = <0x000000cc>;
  330. ti,dma-safe-map = <0x00000000>;
  331. dma-masters = <0x0000000f>;
  332. phandle = <0x000000b1>;
  333. };
  334. };
  335. };
  336. target-module@5000 {
  337. compatible = "ti,sysc-omap4", "ti,sysc";
  338. reg = <0x00005000 0x00000004>;
  339. reg-names = "rev";
  340. #address-cells = <0x00000001>;
  341. #size-cells = <0x00000001>;
  342. ranges = <0x00000000 0x00005000 0x00001000>;
  343. cm_core_aon@0 {
  344. compatible = "ti,dra7-cm-core-aon", "simple-bus";
  345. #address-cells = <0x00000001>;
  346. #size-cells = <0x00000001>;
  347. reg = <0x00000000 0x00002000>;
  348. ranges = <0x00000000 0x00000000 0x00002000>;
  349. clocks {
  350. #address-cells = <0x00000001>;
  351. #size-cells = <0x00000000>;
  352. atl_clkin0_ck {
  353. #clock-cells = <0x00000000>;
  354. compatible = "ti,dra7-atl-clock";
  355. clocks = <0x00000010 0x00000000 0x0000001a>;
  356. phandle = <0x000000aa>;
  357. };
  358. atl_clkin1_ck {
  359. #clock-cells = <0x00000000>;
  360. compatible = "ti,dra7-atl-clock";
  361. clocks = <0x00000010 0x00000000 0x0000001a>;
  362. phandle = <0x000000ab>;
  363. };
  364. atl_clkin2_ck {
  365. #clock-cells = <0x00000000>;
  366. compatible = "ti,dra7-atl-clock";
  367. clocks = <0x00000010 0x00000000 0x0000001a>;
  368. phandle = <0x000000ac>;
  369. };
  370. atl_clkin3_ck {
  371. #clock-cells = <0x00000000>;
  372. compatible = "ti,dra7-atl-clock";
  373. clocks = <0x00000010 0x00000000 0x0000001a>;
  374. phandle = <0x000000ad>;
  375. };
  376. hdmi_clkin_ck {
  377. #clock-cells = <0x00000000>;
  378. compatible = "fixed-clock";
  379. clock-frequency = <0x00000000>;
  380. phandle = <0x00000030>;
  381. };
  382. mlb_clkin_ck {
  383. #clock-cells = <0x00000000>;
  384. compatible = "fixed-clock";
  385. clock-frequency = <0x00000000>;
  386. phandle = <0x0000008d>;
  387. };
  388. mlbp_clkin_ck {
  389. #clock-cells = <0x00000000>;
  390. compatible = "fixed-clock";
  391. clock-frequency = <0x00000000>;
  392. phandle = <0x0000008e>;
  393. };
  394. pciesref_acs_clk_ck {
  395. #clock-cells = <0x00000000>;
  396. compatible = "fixed-clock";
  397. clock-frequency = <0x05f5e100>;
  398. phandle = <0x00000040>;
  399. };
  400. ref_clkin0_ck {
  401. #clock-cells = <0x00000000>;
  402. compatible = "fixed-clock";
  403. clock-frequency = <0x00000000>;
  404. };
  405. ref_clkin1_ck {
  406. #clock-cells = <0x00000000>;
  407. compatible = "fixed-clock";
  408. clock-frequency = <0x00000000>;
  409. };
  410. ref_clkin2_ck {
  411. #clock-cells = <0x00000000>;
  412. compatible = "fixed-clock";
  413. clock-frequency = <0x00000000>;
  414. };
  415. ref_clkin3_ck {
  416. #clock-cells = <0x00000000>;
  417. compatible = "fixed-clock";
  418. clock-frequency = <0x00000000>;
  419. };
  420. rmii_clk_ck {
  421. #clock-cells = <0x00000000>;
  422. compatible = "fixed-clock";
  423. clock-frequency = <0x00000000>;
  424. };
  425. sdvenc_clkin_ck {
  426. #clock-cells = <0x00000000>;
  427. compatible = "fixed-clock";
  428. clock-frequency = <0x00000000>;
  429. };
  430. secure_32k_clk_src_ck {
  431. #clock-cells = <0x00000000>;
  432. compatible = "fixed-clock";
  433. clock-frequency = <0x00008000>;
  434. phandle = <0x00000077>;
  435. };
  436. sys_clk32_crystal_ck {
  437. #clock-cells = <0x00000000>;
  438. compatible = "fixed-clock";
  439. clock-frequency = <0x00008000>;
  440. phandle = <0x0000000c>;
  441. };
  442. sys_clk32_pseudo_ck {
  443. #clock-cells = <0x00000000>;
  444. compatible = "fixed-factor-clock";
  445. clocks = <0x00000011>;
  446. clock-mult = <0x00000001>;
  447. clock-div = <0x00000262>;
  448. phandle = <0x0000000d>;
  449. };
  450. virt_12000000_ck {
  451. #clock-cells = <0x00000000>;
  452. compatible = "fixed-clock";
  453. clock-frequency = <0x00b71b00>;
  454. phandle = <0x00000065>;
  455. };
  456. virt_13000000_ck {
  457. #clock-cells = <0x00000000>;
  458. compatible = "fixed-clock";
  459. clock-frequency = <0x00c65d40>;
  460. };
  461. virt_16800000_ck {
  462. #clock-cells = <0x00000000>;
  463. compatible = "fixed-clock";
  464. clock-frequency = <0x01005900>;
  465. phandle = <0x00000067>;
  466. };
  467. virt_19200000_ck {
  468. #clock-cells = <0x00000000>;
  469. compatible = "fixed-clock";
  470. clock-frequency = <0x0124f800>;
  471. phandle = <0x00000068>;
  472. };
  473. virt_20000000_ck {
  474. #clock-cells = <0x00000000>;
  475. compatible = "fixed-clock";
  476. clock-frequency = <0x01312d00>;
  477. phandle = <0x00000066>;
  478. };
  479. virt_26000000_ck {
  480. #clock-cells = <0x00000000>;
  481. compatible = "fixed-clock";
  482. clock-frequency = <0x018cba80>;
  483. phandle = <0x00000069>;
  484. };
  485. virt_27000000_ck {
  486. #clock-cells = <0x00000000>;
  487. compatible = "fixed-clock";
  488. clock-frequency = <0x019bfcc0>;
  489. phandle = <0x0000006a>;
  490. };
  491. virt_38400000_ck {
  492. #clock-cells = <0x00000000>;
  493. compatible = "fixed-clock";
  494. clock-frequency = <0x0249f000>;
  495. phandle = <0x0000006b>;
  496. };
  497. sys_clkin2 {
  498. #clock-cells = <0x00000000>;
  499. compatible = "fixed-clock";
  500. clock-frequency = <0x01588800>;
  501. phandle = <0x0000006c>;
  502. };
  503. usb_otg_clkin_ck {
  504. #clock-cells = <0x00000000>;
  505. compatible = "fixed-clock";
  506. clock-frequency = <0x00000000>;
  507. phandle = <0x00000074>;
  508. };
  509. video1_clkin_ck {
  510. #clock-cells = <0x00000000>;
  511. compatible = "fixed-clock";
  512. clock-frequency = <0x00000000>;
  513. phandle = <0x0000003a>;
  514. };
  515. video1_m2_clkin_ck {
  516. #clock-cells = <0x00000000>;
  517. compatible = "fixed-clock";
  518. clock-frequency = <0x00000000>;
  519. phandle = <0x0000002f>;
  520. };
  521. video2_clkin_ck {
  522. #clock-cells = <0x00000000>;
  523. compatible = "fixed-clock";
  524. clock-frequency = <0x00000000>;
  525. phandle = <0x0000003b>;
  526. };
  527. video2_m2_clkin_ck {
  528. #clock-cells = <0x00000000>;
  529. compatible = "fixed-clock";
  530. clock-frequency = <0x00000000>;
  531. phandle = <0x0000002e>;
  532. };
  533. dpll_abe_ck@1e0 {
  534. #clock-cells = <0x00000000>;
  535. compatible = "ti,omap4-dpll-m4xen-clock";
  536. clocks = <0x00000012 0x00000013>;
  537. reg = <0x000001e0 0x000001e4 0x000001ec 0x000001e8>;
  538. phandle = <0x00000014>;
  539. };
  540. dpll_abe_x2_ck {
  541. #clock-cells = <0x00000000>;
  542. compatible = "ti,omap4-dpll-x2-clock";
  543. clocks = <0x00000014>;
  544. phandle = <0x00000015>;
  545. };
  546. dpll_abe_m2x2_ck@1f0 {
  547. #clock-cells = <0x00000000>;
  548. compatible = "ti,divider-clock";
  549. clocks = <0x00000015>;
  550. ti,max-div = <0x0000001f>;
  551. ti,autoidle-shift = <0x00000008>;
  552. reg = <0x000001f0>;
  553. ti,index-starts-at-one;
  554. ti,invert-autoidle-bit;
  555. phandle = <0x00000016>;
  556. };
  557. abe_clk@108 {
  558. #clock-cells = <0x00000000>;
  559. compatible = "ti,divider-clock";
  560. clocks = <0x00000016>;
  561. ti,max-div = <0x00000004>;
  562. reg = <0x00000108>;
  563. ti,index-power-of-two;
  564. phandle = <0x0000006e>;
  565. };
  566. dpll_abe_m2_ck@1f0 {
  567. #clock-cells = <0x00000000>;
  568. compatible = "ti,divider-clock";
  569. clocks = <0x00000014>;
  570. ti,max-div = <0x0000001f>;
  571. ti,autoidle-shift = <0x00000008>;
  572. reg = <0x000001f0>;
  573. ti,index-starts-at-one;
  574. ti,invert-autoidle-bit;
  575. phandle = <0x00000070>;
  576. };
  577. dpll_abe_m3x2_ck@1f4 {
  578. #clock-cells = <0x00000000>;
  579. compatible = "ti,divider-clock";
  580. clocks = <0x00000015>;
  581. ti,max-div = <0x0000001f>;
  582. ti,autoidle-shift = <0x00000008>;
  583. reg = <0x000001f4>;
  584. ti,index-starts-at-one;
  585. ti,invert-autoidle-bit;
  586. phandle = <0x00000017>;
  587. };
  588. dpll_core_byp_mux@12c {
  589. #clock-cells = <0x00000000>;
  590. compatible = "ti,mux-clock";
  591. clocks = <0x00000011 0x00000017>;
  592. ti,bit-shift = <0x00000017>;
  593. reg = <0x0000012c>;
  594. phandle = <0x00000018>;
  595. };
  596. dpll_core_ck@120 {
  597. #clock-cells = <0x00000000>;
  598. compatible = "ti,omap4-dpll-core-clock";
  599. clocks = <0x00000011 0x00000018>;
  600. reg = <0x00000120 0x00000124 0x0000012c 0x00000128>;
  601. phandle = <0x00000019>;
  602. };
  603. dpll_core_x2_ck {
  604. #clock-cells = <0x00000000>;
  605. compatible = "ti,omap4-dpll-x2-clock";
  606. clocks = <0x00000019>;
  607. phandle = <0x0000001a>;
  608. };
  609. dpll_core_h12x2_ck@13c {
  610. #clock-cells = <0x00000000>;
  611. compatible = "ti,divider-clock";
  612. clocks = <0x0000001a>;
  613. ti,max-div = <0x0000003f>;
  614. ti,autoidle-shift = <0x00000008>;
  615. reg = <0x0000013c>;
  616. ti,index-starts-at-one;
  617. ti,invert-autoidle-bit;
  618. phandle = <0x0000001b>;
  619. };
  620. mpu_dpll_hs_clk_div {
  621. #clock-cells = <0x00000000>;
  622. compatible = "fixed-factor-clock";
  623. clocks = <0x0000001b>;
  624. clock-mult = <0x00000001>;
  625. clock-div = <0x00000001>;
  626. phandle = <0x0000001c>;
  627. };
  628. dpll_mpu_ck@160 {
  629. #clock-cells = <0x00000000>;
  630. compatible = "ti,omap5-mpu-dpll-clock";
  631. clocks = <0x00000011 0x0000001c>;
  632. reg = <0x00000160 0x00000164 0x0000016c 0x00000168>;
  633. phandle = <0x00000004>;
  634. };
  635. dpll_mpu_m2_ck@170 {
  636. #clock-cells = <0x00000000>;
  637. compatible = "ti,divider-clock";
  638. clocks = <0x00000004>;
  639. ti,max-div = <0x0000001f>;
  640. ti,autoidle-shift = <0x00000008>;
  641. reg = <0x00000170>;
  642. ti,index-starts-at-one;
  643. ti,invert-autoidle-bit;
  644. phandle = <0x0000001d>;
  645. };
  646. mpu_dclk_div {
  647. #clock-cells = <0x00000000>;
  648. compatible = "fixed-factor-clock";
  649. clocks = <0x0000001d>;
  650. clock-mult = <0x00000001>;
  651. clock-div = <0x00000001>;
  652. phandle = <0x0000007b>;
  653. };
  654. dsp_dpll_hs_clk_div {
  655. #clock-cells = <0x00000000>;
  656. compatible = "fixed-factor-clock";
  657. clocks = <0x0000001b>;
  658. clock-mult = <0x00000001>;
  659. clock-div = <0x00000001>;
  660. phandle = <0x0000001e>;
  661. };
  662. dpll_dsp_byp_mux@240 {
  663. #clock-cells = <0x00000000>;
  664. compatible = "ti,mux-clock";
  665. clocks = <0x00000011 0x0000001e>;
  666. ti,bit-shift = <0x00000017>;
  667. reg = <0x00000240>;
  668. phandle = <0x0000001f>;
  669. };
  670. dpll_dsp_ck@234 {
  671. #clock-cells = <0x00000000>;
  672. compatible = "ti,omap4-dpll-clock";
  673. clocks = <0x00000011 0x0000001f>;
  674. reg = <0x00000234 0x00000238 0x00000240 0x0000023c>;
  675. assigned-clocks = <0x00000020>;
  676. assigned-clock-rates = "#ÃF";
  677. phandle = <0x00000020>;
  678. };
  679. dpll_dsp_m2_ck@244 {
  680. #clock-cells = <0x00000000>;
  681. compatible = "ti,divider-clock";
  682. clocks = <0x00000020>;
  683. ti,max-div = <0x0000001f>;
  684. ti,autoidle-shift = <0x00000008>;
  685. reg = <0x00000244>;
  686. ti,index-starts-at-one;
  687. ti,invert-autoidle-bit;
  688. assigned-clocks = <0x00000021>;
  689. assigned-clock-rates = "#ÃF";
  690. phandle = <0x00000021>;
  691. };
  692. iva_dpll_hs_clk_div {
  693. #clock-cells = <0x00000000>;
  694. compatible = "fixed-factor-clock";
  695. clocks = <0x0000001b>;
  696. clock-mult = <0x00000001>;
  697. clock-div = <0x00000001>;
  698. phandle = <0x00000022>;
  699. };
  700. dpll_iva_byp_mux@1ac {
  701. #clock-cells = <0x00000000>;
  702. compatible = "ti,mux-clock";
  703. clocks = <0x00000011 0x00000022>;
  704. ti,bit-shift = <0x00000017>;
  705. reg = <0x000001ac>;
  706. phandle = <0x00000023>;
  707. };
  708. dpll_iva_ck@1a0 {
  709. #clock-cells = <0x00000000>;
  710. compatible = "ti,omap4-dpll-clock";
  711. clocks = <0x00000011 0x00000023>;
  712. reg = <0x000001a0 0x000001a4 0x000001ac 0x000001a8>;
  713. assigned-clocks = <0x00000024>;
  714. assigned-clock-rates = <0x45707d40>;
  715. phandle = <0x00000024>;
  716. };
  717. dpll_iva_m2_ck@1b0 {
  718. #clock-cells = <0x00000000>;
  719. compatible = "ti,divider-clock";
  720. clocks = <0x00000024>;
  721. ti,max-div = <0x0000001f>;
  722. ti,autoidle-shift = <0x00000008>;
  723. reg = <0x000001b0>;
  724. ti,index-starts-at-one;
  725. ti,invert-autoidle-bit;
  726. assigned-clocks = <0x00000025>;
  727. assigned-clock-rates = <0x17257f16>;
  728. phandle = <0x00000025>;
  729. };
  730. iva_dclk {
  731. #clock-cells = <0x00000000>;
  732. compatible = "fixed-factor-clock";
  733. clocks = <0x00000025>;
  734. clock-mult = <0x00000001>;
  735. clock-div = <0x00000001>;
  736. phandle = <0x0000007d>;
  737. };
  738. dpll_gpu_byp_mux@2e4 {
  739. #clock-cells = <0x00000000>;
  740. compatible = "ti,mux-clock";
  741. clocks = <0x00000011 0x00000017>;
  742. ti,bit-shift = <0x00000017>;
  743. reg = <0x000002e4>;
  744. phandle = <0x00000026>;
  745. };
  746. dpll_gpu_ck@2d8 {
  747. #clock-cells = <0x00000000>;
  748. compatible = "ti,omap4-dpll-clock";
  749. clocks = <0x00000011 0x00000026>;
  750. reg = <0x000002d8 0x000002dc 0x000002e4 0x000002e0>;
  751. assigned-clocks = <0x00000027>;
  752. assigned-clock-rates = <0x4c1d7940>;
  753. phandle = <0x00000027>;
  754. };
  755. dpll_gpu_m2_ck@2e8 {
  756. #clock-cells = <0x00000000>;
  757. compatible = "ti,divider-clock";
  758. clocks = <0x00000027>;
  759. ti,max-div = <0x0000001f>;
  760. ti,autoidle-shift = <0x00000008>;
  761. reg = <0x000002e8>;
  762. ti,index-starts-at-one;
  763. ti,invert-autoidle-bit;
  764. assigned-clocks = <0x00000028>;
  765. assigned-clock-rates = <0x195f286b>;
  766. phandle = <0x00000028>;
  767. };
  768. dpll_core_m2_ck@130 {
  769. #clock-cells = <0x00000000>;
  770. compatible = "ti,divider-clock";
  771. clocks = <0x00000019>;
  772. ti,max-div = <0x0000001f>;
  773. ti,autoidle-shift = <0x00000008>;
  774. reg = <0x00000130>;
  775. ti,index-starts-at-one;
  776. ti,invert-autoidle-bit;
  777. phandle = <0x00000029>;
  778. };
  779. core_dpll_out_dclk_div {
  780. #clock-cells = <0x00000000>;
  781. compatible = "fixed-factor-clock";
  782. clocks = <0x00000029>;
  783. clock-mult = <0x00000001>;
  784. clock-div = <0x00000001>;
  785. phandle = <0x0000007f>;
  786. };
  787. dpll_ddr_byp_mux@21c {
  788. #clock-cells = <0x00000000>;
  789. compatible = "ti,mux-clock";
  790. clocks = <0x00000011 0x00000017>;
  791. ti,bit-shift = <0x00000017>;
  792. reg = <0x0000021c>;
  793. phandle = <0x0000002a>;
  794. };
  795. dpll_ddr_ck@210 {
  796. #clock-cells = <0x00000000>;
  797. compatible = "ti,omap4-dpll-clock";
  798. clocks = <0x00000011 0x0000002a>;
  799. reg = <0x00000210 0x00000214 0x0000021c 0x00000218>;
  800. phandle = <0x0000002b>;
  801. };
  802. dpll_ddr_m2_ck@220 {
  803. #clock-cells = <0x00000000>;
  804. compatible = "ti,divider-clock";
  805. clocks = <0x0000002b>;
  806. ti,max-div = <0x0000001f>;
  807. ti,autoidle-shift = <0x00000008>;
  808. reg = <0x00000220>;
  809. ti,index-starts-at-one;
  810. ti,invert-autoidle-bit;
  811. phandle = <0x00000071>;
  812. };
  813. dpll_gmac_byp_mux@2b4 {
  814. #clock-cells = <0x00000000>;
  815. compatible = "ti,mux-clock";
  816. clocks = <0x00000011 0x00000017>;
  817. ti,bit-shift = <0x00000017>;
  818. reg = <0x000002b4>;
  819. phandle = <0x0000002c>;
  820. };
  821. dpll_gmac_ck@2a8 {
  822. #clock-cells = <0x00000000>;
  823. compatible = "ti,omap4-dpll-clock";
  824. clocks = <0x00000011 0x0000002c>;
  825. reg = <0x000002a8 0x000002ac 0x000002b4 0x000002b0>;
  826. phandle = <0x0000002d>;
  827. };
  828. dpll_gmac_m2_ck@2b8 {
  829. #clock-cells = <0x00000000>;
  830. compatible = "ti,divider-clock";
  831. clocks = <0x0000002d>;
  832. ti,max-div = <0x0000001f>;
  833. ti,autoidle-shift = <0x00000008>;
  834. reg = <0x000002b8>;
  835. ti,index-starts-at-one;
  836. ti,invert-autoidle-bit;
  837. phandle = <0x00000072>;
  838. };
  839. video2_dclk_div {
  840. #clock-cells = <0x00000000>;
  841. compatible = "fixed-factor-clock";
  842. clocks = <0x0000002e>;
  843. clock-mult = <0x00000001>;
  844. clock-div = <0x00000001>;
  845. phandle = <0x00000081>;
  846. };
  847. video1_dclk_div {
  848. #clock-cells = <0x00000000>;
  849. compatible = "fixed-factor-clock";
  850. clocks = <0x0000002f>;
  851. clock-mult = <0x00000001>;
  852. clock-div = <0x00000001>;
  853. phandle = <0x00000082>;
  854. };
  855. hdmi_dclk_div {
  856. #clock-cells = <0x00000000>;
  857. compatible = "fixed-factor-clock";
  858. clocks = <0x00000030>;
  859. clock-mult = <0x00000001>;
  860. clock-div = <0x00000001>;
  861. phandle = <0x00000083>;
  862. };
  863. per_dpll_hs_clk_div {
  864. #clock-cells = <0x00000000>;
  865. compatible = "fixed-factor-clock";
  866. clocks = <0x00000017>;
  867. clock-mult = <0x00000001>;
  868. clock-div = <0x00000002>;
  869. phandle = <0x00000043>;
  870. };
  871. usb_dpll_hs_clk_div {
  872. #clock-cells = <0x00000000>;
  873. compatible = "fixed-factor-clock";
  874. clocks = <0x00000017>;
  875. clock-mult = <0x00000001>;
  876. clock-div = <0x00000003>;
  877. phandle = <0x00000047>;
  878. };
  879. eve_dpll_hs_clk_div {
  880. #clock-cells = <0x00000000>;
  881. compatible = "fixed-factor-clock";
  882. clocks = <0x0000001b>;
  883. clock-mult = <0x00000001>;
  884. clock-div = <0x00000001>;
  885. phandle = <0x00000031>;
  886. };
  887. dpll_eve_byp_mux@290 {
  888. #clock-cells = <0x00000000>;
  889. compatible = "ti,mux-clock";
  890. clocks = <0x00000011 0x00000031>;
  891. ti,bit-shift = <0x00000017>;
  892. reg = <0x00000290>;
  893. phandle = <0x00000032>;
  894. };
  895. dpll_eve_ck@284 {
  896. #clock-cells = <0x00000000>;
  897. compatible = "ti,omap4-dpll-clock";
  898. clocks = <0x00000011 0x00000032>;
  899. reg = <0x00000284 0x00000288 0x00000290 0x0000028c>;
  900. phandle = <0x00000033>;
  901. };
  902. dpll_eve_m2_ck@294 {
  903. #clock-cells = <0x00000000>;
  904. compatible = "ti,divider-clock";
  905. clocks = <0x00000033>;
  906. ti,max-div = <0x0000001f>;
  907. ti,autoidle-shift = <0x00000008>;
  908. reg = <0x00000294>;
  909. ti,index-starts-at-one;
  910. ti,invert-autoidle-bit;
  911. phandle = <0x00000034>;
  912. };
  913. eve_dclk_div {
  914. #clock-cells = <0x00000000>;
  915. compatible = "fixed-factor-clock";
  916. clocks = <0x00000034>;
  917. clock-mult = <0x00000001>;
  918. clock-div = <0x00000001>;
  919. phandle = <0x0000008c>;
  920. };
  921. dpll_core_h13x2_ck@140 {
  922. #clock-cells = <0x00000000>;
  923. compatible = "ti,divider-clock";
  924. clocks = <0x0000001a>;
  925. ti,max-div = <0x0000003f>;
  926. ti,autoidle-shift = <0x00000008>;
  927. reg = <0x00000140>;
  928. ti,index-starts-at-one;
  929. ti,invert-autoidle-bit;
  930. };
  931. dpll_core_h14x2_ck@144 {
  932. #clock-cells = <0x00000000>;
  933. compatible = "ti,divider-clock";
  934. clocks = <0x0000001a>;
  935. ti,max-div = <0x0000003f>;
  936. ti,autoidle-shift = <0x00000008>;
  937. reg = <0x00000144>;
  938. ti,index-starts-at-one;
  939. ti,invert-autoidle-bit;
  940. phandle = <0x00000051>;
  941. };
  942. dpll_core_h22x2_ck@154 {
  943. #clock-cells = <0x00000000>;
  944. compatible = "ti,divider-clock";
  945. clocks = <0x0000001a>;
  946. ti,max-div = <0x0000003f>;
  947. ti,autoidle-shift = <0x00000008>;
  948. reg = <0x00000154>;
  949. ti,index-starts-at-one;
  950. ti,invert-autoidle-bit;
  951. phandle = <0x0000003c>;
  952. };
  953. dpll_core_h23x2_ck@158 {
  954. #clock-cells = <0x00000000>;
  955. compatible = "ti,divider-clock";
  956. clocks = <0x0000001a>;
  957. ti,max-div = <0x0000003f>;
  958. ti,autoidle-shift = <0x00000008>;
  959. reg = <0x00000158>;
  960. ti,index-starts-at-one;
  961. ti,invert-autoidle-bit;
  962. phandle = <0x00000056>;
  963. };
  964. dpll_core_h24x2_ck@15c {
  965. #clock-cells = <0x00000000>;
  966. compatible = "ti,divider-clock";
  967. clocks = <0x0000001a>;
  968. ti,max-div = <0x0000003f>;
  969. ti,autoidle-shift = <0x00000008>;
  970. reg = <0x0000015c>;
  971. ti,index-starts-at-one;
  972. ti,invert-autoidle-bit;
  973. };
  974. dpll_ddr_x2_ck {
  975. #clock-cells = <0x00000000>;
  976. compatible = "ti,omap4-dpll-x2-clock";
  977. clocks = <0x0000002b>;
  978. phandle = <0x00000035>;
  979. };
  980. dpll_ddr_h11x2_ck@228 {
  981. #clock-cells = <0x00000000>;
  982. compatible = "ti,divider-clock";
  983. clocks = <0x00000035>;
  984. ti,max-div = <0x0000003f>;
  985. ti,autoidle-shift = <0x00000008>;
  986. reg = <0x00000228>;
  987. ti,index-starts-at-one;
  988. ti,invert-autoidle-bit;
  989. };
  990. dpll_dsp_x2_ck {
  991. #clock-cells = <0x00000000>;
  992. compatible = "ti,omap4-dpll-x2-clock";
  993. clocks = <0x00000020>;
  994. phandle = <0x00000036>;
  995. };
  996. dpll_dsp_m3x2_ck@248 {
  997. #clock-cells = <0x00000000>;
  998. compatible = "ti,divider-clock";
  999. clocks = <0x00000036>;
  1000. ti,max-div = <0x0000001f>;
  1001. ti,autoidle-shift = <0x00000008>;
  1002. reg = <0x00000248>;
  1003. ti,index-starts-at-one;
  1004. ti,invert-autoidle-bit;
  1005. assigned-clocks = <0x00000037>;
  1006. assigned-clock-rates = <0x17d78400>;
  1007. phandle = <0x00000037>;
  1008. };
  1009. dpll_gmac_x2_ck {
  1010. #clock-cells = <0x00000000>;
  1011. compatible = "ti,omap4-dpll-x2-clock";
  1012. clocks = <0x0000002d>;
  1013. phandle = <0x00000038>;
  1014. };
  1015. dpll_gmac_h11x2_ck@2c0 {
  1016. #clock-cells = <0x00000000>;
  1017. compatible = "ti,divider-clock";
  1018. clocks = <0x00000038>;
  1019. ti,max-div = <0x0000003f>;
  1020. ti,autoidle-shift = <0x00000008>;
  1021. reg = <0x000002c0>;
  1022. ti,index-starts-at-one;
  1023. ti,invert-autoidle-bit;
  1024. phandle = <0x00000039>;
  1025. };
  1026. dpll_gmac_h12x2_ck@2c4 {
  1027. #clock-cells = <0x00000000>;
  1028. compatible = "ti,divider-clock";
  1029. clocks = <0x00000038>;
  1030. ti,max-div = <0x0000003f>;
  1031. ti,autoidle-shift = <0x00000008>;
  1032. reg = <0x000002c4>;
  1033. ti,index-starts-at-one;
  1034. ti,invert-autoidle-bit;
  1035. };
  1036. dpll_gmac_h13x2_ck@2c8 {
  1037. #clock-cells = <0x00000000>;
  1038. compatible = "ti,divider-clock";
  1039. clocks = <0x00000038>;
  1040. ti,max-div = <0x0000003f>;
  1041. ti,autoidle-shift = <0x00000008>;
  1042. reg = <0x000002c8>;
  1043. ti,index-starts-at-one;
  1044. ti,invert-autoidle-bit;
  1045. };
  1046. dpll_gmac_m3x2_ck@2bc {
  1047. #clock-cells = <0x00000000>;
  1048. compatible = "ti,divider-clock";
  1049. clocks = <0x00000038>;
  1050. ti,max-div = <0x0000001f>;
  1051. ti,autoidle-shift = <0x00000008>;
  1052. reg = <0x000002bc>;
  1053. ti,index-starts-at-one;
  1054. ti,invert-autoidle-bit;
  1055. };
  1056. gmii_m_clk_div {
  1057. #clock-cells = <0x00000000>;
  1058. compatible = "fixed-factor-clock";
  1059. clocks = <0x00000039>;
  1060. clock-mult = <0x00000001>;
  1061. clock-div = <0x00000002>;
  1062. };
  1063. hdmi_clk2_div {
  1064. #clock-cells = <0x00000000>;
  1065. compatible = "fixed-factor-clock";
  1066. clocks = <0x00000030>;
  1067. clock-mult = <0x00000001>;
  1068. clock-div = <0x00000001>;
  1069. };
  1070. hdmi_div_clk {
  1071. #clock-cells = <0x00000000>;
  1072. compatible = "fixed-factor-clock";
  1073. clocks = <0x00000030>;
  1074. clock-mult = <0x00000001>;
  1075. clock-div = <0x00000001>;
  1076. };
  1077. l3_iclk_div@100 {
  1078. #clock-cells = <0x00000000>;
  1079. compatible = "ti,divider-clock";
  1080. ti,max-div = <0x00000002>;
  1081. ti,bit-shift = <0x00000004>;
  1082. reg = <0x00000100>;
  1083. clocks = <0x0000001b>;
  1084. ti,index-power-of-two;
  1085. phandle = <0x0000000a>;
  1086. };
  1087. l4_root_clk_div {
  1088. #clock-cells = <0x00000000>;
  1089. compatible = "fixed-factor-clock";
  1090. clocks = <0x0000000a>;
  1091. clock-mult = <0x00000001>;
  1092. clock-div = <0x00000002>;
  1093. phandle = <0x0000000b>;
  1094. };
  1095. video1_clk2_div {
  1096. #clock-cells = <0x00000000>;
  1097. compatible = "fixed-factor-clock";
  1098. clocks = <0x0000003a>;
  1099. clock-mult = <0x00000001>;
  1100. clock-div = <0x00000001>;
  1101. };
  1102. video1_div_clk {
  1103. #clock-cells = <0x00000000>;
  1104. compatible = "fixed-factor-clock";
  1105. clocks = <0x0000003a>;
  1106. clock-mult = <0x00000001>;
  1107. clock-div = <0x00000001>;
  1108. };
  1109. video2_clk2_div {
  1110. #clock-cells = <0x00000000>;
  1111. compatible = "fixed-factor-clock";
  1112. clocks = <0x0000003b>;
  1113. clock-mult = <0x00000001>;
  1114. clock-div = <0x00000001>;
  1115. };
  1116. video2_div_clk {
  1117. #clock-cells = <0x00000000>;
  1118. compatible = "fixed-factor-clock";
  1119. clocks = <0x0000003b>;
  1120. clock-mult = <0x00000001>;
  1121. clock-div = <0x00000001>;
  1122. };
  1123. ipu1_gfclk_mux@520 {
  1124. #clock-cells = <0x00000000>;
  1125. compatible = "ti,mux-clock";
  1126. clocks = <0x00000016 0x0000003c>;
  1127. ti,bit-shift = <0x00000018>;
  1128. reg = <0x00000520>;
  1129. assigned-clocks = <0x0000003d>;
  1130. assigned-clock-parents = <0x0000003c>;
  1131. phandle = <0x0000003d>;
  1132. };
  1133. dummy_ck {
  1134. #clock-cells = <0x00000000>;
  1135. compatible = "fixed-clock";
  1136. clock-frequency = <0x00000000>;
  1137. };
  1138. };
  1139. clockdomains {
  1140. };
  1141. mpu-cm@300 {
  1142. compatible = "ti,omap4-cm";
  1143. reg = <0x00000300 0x00000100>;
  1144. #address-cells = <0x00000001>;
  1145. #size-cells = <0x00000001>;
  1146. ranges = <0x00000000 0x00000300 0x00000100>;
  1147. mpu-clkctrl@20 {
  1148. compatible = "ti,clkctrl";
  1149. reg = <0x00000020 0x00000004>;
  1150. #clock-cells = <0x00000002>;
  1151. };
  1152. };
  1153. dsp1-cm@400 {
  1154. compatible = "ti,omap4-cm";
  1155. reg = <0x00000400 0x00000100>;
  1156. #address-cells = <0x00000001>;
  1157. #size-cells = <0x00000001>;
  1158. ranges = <0x00000000 0x00000400 0x00000100>;
  1159. dsp1-clkctrl@20 {
  1160. compatible = "ti,clkctrl";
  1161. reg = <0x00000020 0x00000004>;
  1162. #clock-cells = <0x00000002>;
  1163. };
  1164. };
  1165. ipu-cm@500 {
  1166. compatible = "ti,omap4-cm";
  1167. reg = <0x00000500 0x00000100>;
  1168. #address-cells = <0x00000001>;
  1169. #size-cells = <0x00000001>;
  1170. ranges = <0x00000000 0x00000500 0x00000100>;
  1171. ipu1-clkctrl@20 {
  1172. compatible = "ti,clkctrl";
  1173. reg = <0x00000020 0x00000004>;
  1174. #clock-cells = <0x00000002>;
  1175. };
  1176. ipu-clkctrl@50 {
  1177. compatible = "ti,clkctrl";
  1178. reg = <0x00000050 0x00000034>;
  1179. #clock-cells = <0x00000002>;
  1180. phandle = <0x00000094>;
  1181. };
  1182. };
  1183. dsp2-cm@600 {
  1184. compatible = "ti,omap4-cm";
  1185. reg = <0x00000600 0x00000100>;
  1186. #address-cells = <0x00000001>;
  1187. #size-cells = <0x00000001>;
  1188. ranges = <0x00000000 0x00000600 0x00000100>;
  1189. dsp2-clkctrl@20 {
  1190. compatible = "ti,clkctrl";
  1191. reg = <0x00000020 0x00000004>;
  1192. #clock-cells = <0x00000002>;
  1193. };
  1194. };
  1195. rtc-cm@700 {
  1196. compatible = "ti,omap4-cm";
  1197. reg = <0x00000700 0x00000100>;
  1198. #address-cells = <0x00000001>;
  1199. #size-cells = <0x00000001>;
  1200. ranges = <0x00000000 0x00000700 0x00000100>;
  1201. rtc-clkctrl@20 {
  1202. compatible = "ti,clkctrl";
  1203. reg = <0x00000020 0x00000028>;
  1204. #clock-cells = <0x00000002>;
  1205. phandle = <0x000000b8>;
  1206. };
  1207. };
  1208. };
  1209. };
  1210. target-module@8000 {
  1211. compatible = "ti,sysc-omap4", "ti,sysc";
  1212. reg = <0x00008000 0x00000004>;
  1213. reg-names = "rev";
  1214. #address-cells = <0x00000001>;
  1215. #size-cells = <0x00000001>;
  1216. ranges = <0x00000000 0x00008000 0x00002000>;
  1217. cm_core@0 {
  1218. compatible = "ti,dra7-cm-core", "simple-bus";
  1219. #address-cells = <0x00000001>;
  1220. #size-cells = <0x00000001>;
  1221. reg = <0x00000000 0x00003000>;
  1222. ranges = <0x00000000 0x00000000 0x00003000>;
  1223. clocks {
  1224. #address-cells = <0x00000001>;
  1225. #size-cells = <0x00000000>;
  1226. dpll_pcie_ref_ck@200 {
  1227. #clock-cells = <0x00000000>;
  1228. compatible = "ti,omap4-dpll-clock";
  1229. clocks = <0x00000011 0x00000011>;
  1230. reg = <0x00000200 0x00000204 0x0000020c 0x00000208>;
  1231. phandle = <0x0000003e>;
  1232. };
  1233. dpll_pcie_ref_m2ldo_ck@210 {
  1234. #clock-cells = <0x00000000>;
  1235. compatible = "ti,divider-clock";
  1236. clocks = <0x0000003e>;
  1237. ti,max-div = <0x0000001f>;
  1238. ti,autoidle-shift = <0x00000008>;
  1239. reg = <0x00000210>;
  1240. ti,index-starts-at-one;
  1241. ti,invert-autoidle-bit;
  1242. phandle = <0x0000003f>;
  1243. };
  1244. apll_pcie_in_clk_mux@4ae06118 {
  1245. compatible = "ti,mux-clock";
  1246. clocks = <0x0000003f 0x00000040>;
  1247. #clock-cells = <0x00000000>;
  1248. reg = <0x0000021c 0x00000004>;
  1249. ti,bit-shift = <0x00000007>;
  1250. phandle = <0x00000041>;
  1251. };
  1252. apll_pcie_ck@21c {
  1253. #clock-cells = <0x00000000>;
  1254. compatible = "ti,dra7-apll-clock";
  1255. clocks = <0x00000041 0x0000003e>;
  1256. reg = <0x0000021c 0x00000220>;
  1257. phandle = <0x00000042>;
  1258. };
  1259. optfclk_pciephy_div@4a00821c {
  1260. compatible = "ti,divider-clock";
  1261. clocks = <0x00000042>;
  1262. #clock-cells = <0x00000000>;
  1263. reg = <0x0000021c>;
  1264. ti,dividers = <0x00000002 0x00000001>;
  1265. ti,bit-shift = <0x00000008>;
  1266. ti,max-div = <0x00000002>;
  1267. phandle = <0x00000061>;
  1268. };
  1269. apll_pcie_clkvcoldo {
  1270. #clock-cells = <0x00000000>;
  1271. compatible = "fixed-factor-clock";
  1272. clocks = <0x00000042>;
  1273. clock-mult = <0x00000001>;
  1274. clock-div = <0x00000001>;
  1275. };
  1276. apll_pcie_clkvcoldo_div {
  1277. #clock-cells = <0x00000000>;
  1278. compatible = "fixed-factor-clock";
  1279. clocks = <0x00000042>;
  1280. clock-mult = <0x00000001>;
  1281. clock-div = <0x00000001>;
  1282. };
  1283. apll_pcie_m2_ck {
  1284. #clock-cells = <0x00000000>;
  1285. compatible = "fixed-factor-clock";
  1286. clocks = <0x00000042>;
  1287. clock-mult = <0x00000001>;
  1288. clock-div = <0x00000001>;
  1289. phandle = <0x00000076>;
  1290. };
  1291. dpll_per_byp_mux@14c {
  1292. #clock-cells = <0x00000000>;
  1293. compatible = "ti,mux-clock";
  1294. clocks = <0x00000011 0x00000043>;
  1295. ti,bit-shift = <0x00000017>;
  1296. reg = <0x0000014c>;
  1297. phandle = <0x00000044>;
  1298. };
  1299. dpll_per_ck@140 {
  1300. #clock-cells = <0x00000000>;
  1301. compatible = "ti,omap4-dpll-clock";
  1302. clocks = <0x00000011 0x00000044>;
  1303. reg = <0x00000140 0x00000144 0x0000014c 0x00000148>;
  1304. phandle = <0x00000045>;
  1305. };
  1306. dpll_per_m2_ck@150 {
  1307. #clock-cells = <0x00000000>;
  1308. compatible = "ti,divider-clock";
  1309. clocks = <0x00000045>;
  1310. ti,max-div = <0x0000001f>;
  1311. ti,autoidle-shift = <0x00000008>;
  1312. reg = <0x00000150>;
  1313. ti,index-starts-at-one;
  1314. ti,invert-autoidle-bit;
  1315. phandle = <0x00000046>;
  1316. };
  1317. func_96m_aon_dclk_div {
  1318. #clock-cells = <0x00000000>;
  1319. compatible = "fixed-factor-clock";
  1320. clocks = <0x00000046>;
  1321. clock-mult = <0x00000001>;
  1322. clock-div = <0x00000001>;
  1323. phandle = <0x00000084>;
  1324. };
  1325. dpll_usb_byp_mux@18c {
  1326. #clock-cells = <0x00000000>;
  1327. compatible = "ti,mux-clock";
  1328. clocks = <0x00000011 0x00000047>;
  1329. ti,bit-shift = <0x00000017>;
  1330. reg = <0x0000018c>;
  1331. phandle = <0x00000048>;
  1332. };
  1333. dpll_usb_ck@180 {
  1334. #clock-cells = <0x00000000>;
  1335. compatible = "ti,omap4-dpll-j-type-clock";
  1336. clocks = <0x00000011 0x00000048>;
  1337. reg = <0x00000180 0x00000184 0x0000018c 0x00000188>;
  1338. phandle = <0x00000049>;
  1339. };
  1340. dpll_usb_m2_ck@190 {
  1341. #clock-cells = <0x00000000>;
  1342. compatible = "ti,divider-clock";
  1343. clocks = <0x00000049>;
  1344. ti,max-div = <0x0000007f>;
  1345. ti,autoidle-shift = <0x00000008>;
  1346. reg = <0x00000190>;
  1347. ti,index-starts-at-one;
  1348. ti,invert-autoidle-bit;
  1349. phandle = <0x0000004d>;
  1350. };
  1351. dpll_pcie_ref_m2_ck@210 {
  1352. #clock-cells = <0x00000000>;
  1353. compatible = "ti,divider-clock";
  1354. clocks = <0x0000003e>;
  1355. ti,max-div = <0x0000007f>;
  1356. ti,autoidle-shift = <0x00000008>;
  1357. reg = <0x00000210>;
  1358. ti,index-starts-at-one;
  1359. ti,invert-autoidle-bit;
  1360. phandle = <0x00000075>;
  1361. };
  1362. dpll_per_x2_ck {
  1363. #clock-cells = <0x00000000>;
  1364. compatible = "ti,omap4-dpll-x2-clock";
  1365. clocks = <0x00000045>;
  1366. phandle = <0x0000004a>;
  1367. };
  1368. dpll_per_h11x2_ck@158 {
  1369. #clock-cells = <0x00000000>;
  1370. compatible = "ti,divider-clock";
  1371. clocks = <0x0000004a>;
  1372. ti,max-div = <0x0000003f>;
  1373. ti,autoidle-shift = <0x00000008>;
  1374. reg = <0x00000158>;
  1375. ti,index-starts-at-one;
  1376. ti,invert-autoidle-bit;
  1377. phandle = <0x0000004b>;
  1378. };
  1379. dpll_per_h12x2_ck@15c {
  1380. #clock-cells = <0x00000000>;
  1381. compatible = "ti,divider-clock";
  1382. clocks = <0x0000004a>;
  1383. ti,max-div = <0x0000003f>;
  1384. ti,autoidle-shift = <0x00000008>;
  1385. reg = <0x0000015c>;
  1386. ti,index-starts-at-one;
  1387. ti,invert-autoidle-bit;
  1388. };
  1389. dpll_per_h13x2_ck@160 {
  1390. #clock-cells = <0x00000000>;
  1391. compatible = "ti,divider-clock";
  1392. clocks = <0x0000004a>;
  1393. ti,max-div = <0x0000003f>;
  1394. ti,autoidle-shift = <0x00000008>;
  1395. reg = <0x00000160>;
  1396. ti,index-starts-at-one;
  1397. ti,invert-autoidle-bit;
  1398. };
  1399. dpll_per_h14x2_ck@164 {
  1400. #clock-cells = <0x00000000>;
  1401. compatible = "ti,divider-clock";
  1402. clocks = <0x0000004a>;
  1403. ti,max-div = <0x0000003f>;
  1404. ti,autoidle-shift = <0x00000008>;
  1405. reg = <0x00000164>;
  1406. ti,index-starts-at-one;
  1407. ti,invert-autoidle-bit;
  1408. phandle = <0x00000052>;
  1409. };
  1410. dpll_per_m2x2_ck@150 {
  1411. #clock-cells = <0x00000000>;
  1412. compatible = "ti,divider-clock";
  1413. clocks = <0x0000004a>;
  1414. ti,max-div = <0x0000001f>;
  1415. ti,autoidle-shift = <0x00000008>;
  1416. reg = <0x00000150>;
  1417. ti,index-starts-at-one;
  1418. ti,invert-autoidle-bit;
  1419. phandle = <0x0000004c>;
  1420. };
  1421. dpll_usb_clkdcoldo {
  1422. #clock-cells = <0x00000000>;
  1423. compatible = "fixed-factor-clock";
  1424. clocks = <0x00000049>;
  1425. clock-mult = <0x00000001>;
  1426. clock-div = <0x00000001>;
  1427. phandle = <0x0000004f>;
  1428. };
  1429. func_128m_clk {
  1430. #clock-cells = <0x00000000>;
  1431. compatible = "fixed-factor-clock";
  1432. clocks = <0x0000004b>;
  1433. clock-mult = <0x00000001>;
  1434. clock-div = <0x00000002>;
  1435. };
  1436. func_12m_fclk {
  1437. #clock-cells = <0x00000000>;
  1438. compatible = "fixed-factor-clock";
  1439. clocks = <0x0000004c>;
  1440. clock-mult = <0x00000001>;
  1441. clock-div = <0x00000010>;
  1442. };
  1443. func_24m_clk {
  1444. #clock-cells = <0x00000000>;
  1445. compatible = "fixed-factor-clock";
  1446. clocks = <0x00000046>;
  1447. clock-mult = <0x00000001>;
  1448. clock-div = <0x00000004>;
  1449. };
  1450. func_48m_fclk {
  1451. #clock-cells = <0x00000000>;
  1452. compatible = "fixed-factor-clock";
  1453. clocks = <0x0000004c>;
  1454. clock-mult = <0x00000001>;
  1455. clock-div = <0x00000004>;
  1456. };
  1457. func_96m_fclk {
  1458. #clock-cells = <0x00000000>;
  1459. compatible = "fixed-factor-clock";
  1460. clocks = <0x0000004c>;
  1461. clock-mult = <0x00000001>;
  1462. clock-div = <0x00000002>;
  1463. };
  1464. l3init_60m_fclk@104 {
  1465. #clock-cells = <0x00000000>;
  1466. compatible = "ti,divider-clock";
  1467. clocks = <0x0000004d>;
  1468. reg = <0x00000104>;
  1469. ti,dividers = <0x00000001 0x00000008>;
  1470. };
  1471. clkout2_clk@6b0 {
  1472. #clock-cells = <0x00000000>;
  1473. compatible = "ti,gate-clock";
  1474. clocks = <0x0000004e>;
  1475. ti,bit-shift = <0x00000008>;
  1476. reg = <0x000006b0>;
  1477. phandle = <0x000000dc>;
  1478. };
  1479. l3init_960m_gfclk@6c0 {
  1480. #clock-cells = <0x00000000>;
  1481. compatible = "ti,gate-clock";
  1482. clocks = <0x0000004f>;
  1483. ti,bit-shift = <0x00000008>;
  1484. reg = <0x000006c0>;
  1485. };
  1486. usb_phy1_always_on_clk32k@640 {
  1487. #clock-cells = <0x00000000>;
  1488. compatible = "ti,gate-clock";
  1489. clocks = <0x00000050>;
  1490. ti,bit-shift = <0x00000008>;
  1491. reg = <0x00000640>;
  1492. phandle = <0x0000005b>;
  1493. };
  1494. usb_phy2_always_on_clk32k@688 {
  1495. #clock-cells = <0x00000000>;
  1496. compatible = "ti,gate-clock";
  1497. clocks = <0x00000050>;
  1498. ti,bit-shift = <0x00000008>;
  1499. reg = <0x00000688>;
  1500. phandle = <0x0000005d>;
  1501. };
  1502. usb_phy3_always_on_clk32k@698 {
  1503. #clock-cells = <0x00000000>;
  1504. compatible = "ti,gate-clock";
  1505. clocks = <0x00000050>;
  1506. ti,bit-shift = <0x00000008>;
  1507. reg = <0x00000698>;
  1508. phandle = <0x0000005e>;
  1509. };
  1510. gpu_core_gclk_mux@1220 {
  1511. #clock-cells = <0x00000000>;
  1512. compatible = "ti,mux-clock";
  1513. clocks = <0x00000051 0x00000052 0x00000028>;
  1514. ti,bit-shift = <0x00000018>;
  1515. reg = <0x00001220>;
  1516. assigned-clocks = <0x00000053>;
  1517. assigned-clock-parents = <0x00000028>;
  1518. phandle = <0x00000053>;
  1519. };
  1520. gpu_hyd_gclk_mux@1220 {
  1521. #clock-cells = <0x00000000>;
  1522. compatible = "ti,mux-clock";
  1523. clocks = <0x00000051 0x00000052 0x00000028>;
  1524. ti,bit-shift = <0x0000001a>;
  1525. reg = <0x00001220>;
  1526. assigned-clocks = <0x00000054>;
  1527. assigned-clock-parents = <0x00000028>;
  1528. phandle = <0x00000054>;
  1529. };
  1530. l3instr_ts_gclk_div@e50 {
  1531. #clock-cells = <0x00000000>;
  1532. compatible = "ti,divider-clock";
  1533. clocks = <0x00000055>;
  1534. ti,bit-shift = <0x00000018>;
  1535. reg = <0x00000e50>;
  1536. ti,dividers = <0x00000008 0x00000010 0x00000020>;
  1537. };
  1538. vip1_gclk_mux@1020 {
  1539. #clock-cells = <0x00000000>;
  1540. compatible = "ti,mux-clock";
  1541. clocks = <0x0000000a 0x00000056>;
  1542. ti,bit-shift = <0x00000018>;
  1543. reg = <0x00001020>;
  1544. };
  1545. vip2_gclk_mux@1028 {
  1546. #clock-cells = <0x00000000>;
  1547. compatible = "ti,mux-clock";
  1548. clocks = <0x0000000a 0x00000056>;
  1549. ti,bit-shift = <0x00000018>;
  1550. reg = <0x00001028>;
  1551. };
  1552. vip3_gclk_mux@1030 {
  1553. #clock-cells = <0x00000000>;
  1554. compatible = "ti,mux-clock";
  1555. clocks = <0x0000000a 0x00000056>;
  1556. ti,bit-shift = <0x00000018>;
  1557. reg = <0x00001030>;
  1558. };
  1559. };
  1560. clockdomains {
  1561. coreaon_clkdm {
  1562. compatible = "ti,clockdomain";
  1563. clocks = <0x00000049>;
  1564. };
  1565. };
  1566. coreaon-cm@600 {
  1567. compatible = "ti,omap4-cm";
  1568. reg = <0x00000600 0x00000100>;
  1569. #address-cells = <0x00000001>;
  1570. #size-cells = <0x00000001>;
  1571. ranges = <0x00000000 0x00000600 0x00000100>;
  1572. coreaon-clkctrl@20 {
  1573. compatible = "ti,clkctrl";
  1574. reg = <0x00000020 0x0000001c>;
  1575. #clock-cells = <0x00000002>;
  1576. phandle = <0x00000062>;
  1577. };
  1578. };
  1579. l3main1-cm@700 {
  1580. compatible = "ti,omap4-cm";
  1581. reg = <0x00000700 0x00000100>;
  1582. #address-cells = <0x00000001>;
  1583. #size-cells = <0x00000001>;
  1584. ranges = <0x00000000 0x00000700 0x00000100>;
  1585. l3main1-clkctrl@20 {
  1586. compatible = "ti,clkctrl";
  1587. reg = <0x00000020 0x00000074>;
  1588. #clock-cells = <0x00000002>;
  1589. };
  1590. };
  1591. ipu2-cm@900 {
  1592. compatible = "ti,omap4-cm";
  1593. reg = <0x00000900 0x00000100>;
  1594. #address-cells = <0x00000001>;
  1595. #size-cells = <0x00000001>;
  1596. ranges = <0x00000000 0x00000900 0x00000100>;
  1597. ipu2-clkctrl@20 {
  1598. compatible = "ti,clkctrl";
  1599. reg = <0x00000020 0x00000004>;
  1600. #clock-cells = <0x00000002>;
  1601. };
  1602. };
  1603. dma-cm@a00 {
  1604. compatible = "ti,omap4-cm";
  1605. reg = <0x00000a00 0x00000100>;
  1606. #address-cells = <0x00000001>;
  1607. #size-cells = <0x00000001>;
  1608. ranges = <0x00000000 0x00000a00 0x00000100>;
  1609. dma-clkctrl@20 {
  1610. compatible = "ti,clkctrl";
  1611. reg = <0x00000020 0x00000004>;
  1612. #clock-cells = <0x00000002>;
  1613. phandle = <0x00000059>;
  1614. };
  1615. };
  1616. emif-cm@b00 {
  1617. compatible = "ti,omap4-cm";
  1618. reg = <0x00000b00 0x00000100>;
  1619. #address-cells = <0x00000001>;
  1620. #size-cells = <0x00000001>;
  1621. ranges = <0x00000000 0x00000b00 0x00000100>;
  1622. emif-clkctrl@20 {
  1623. compatible = "ti,clkctrl";
  1624. reg = <0x00000020 0x00000004>;
  1625. #clock-cells = <0x00000002>;
  1626. };
  1627. };
  1628. atl-cm@c00 {
  1629. compatible = "ti,omap4-cm";
  1630. reg = <0x00000c00 0x00000100>;
  1631. #address-cells = <0x00000001>;
  1632. #size-cells = <0x00000001>;
  1633. ranges = <0x00000000 0x00000c00 0x00000100>;
  1634. atl-clkctrl@0 {
  1635. compatible = "ti,clkctrl";
  1636. reg = <0x00000000 0x00000004>;
  1637. #clock-cells = <0x00000002>;
  1638. phandle = <0x00000010>;
  1639. };
  1640. };
  1641. l4cfg-cm@d00 {
  1642. compatible = "ti,omap4-cm";
  1643. reg = <0x00000d00 0x00000100>;
  1644. #address-cells = <0x00000001>;
  1645. #size-cells = <0x00000001>;
  1646. ranges = <0x00000000 0x00000d00 0x00000100>;
  1647. l4cfg-clkctrl@20 {
  1648. compatible = "ti,clkctrl";
  1649. reg = <0x00000020 0x00000084>;
  1650. #clock-cells = <0x00000002>;
  1651. phandle = <0x00000063>;
  1652. };
  1653. };
  1654. l3instr-cm@e00 {
  1655. compatible = "ti,omap4-cm";
  1656. reg = <0x00000e00 0x00000100>;
  1657. #address-cells = <0x00000001>;
  1658. #size-cells = <0x00000001>;
  1659. ranges = <0x00000000 0x00000e00 0x00000100>;
  1660. l3instr-clkctrl@20 {
  1661. compatible = "ti,clkctrl";
  1662. reg = <0x00000020 0x0000000c>;
  1663. #clock-cells = <0x00000002>;
  1664. };
  1665. };
  1666. dss-cm@1100 {
  1667. compatible = "ti,omap4-cm";
  1668. reg = <0x00001100 0x00000100>;
  1669. #address-cells = <0x00000001>;
  1670. #size-cells = <0x00000001>;
  1671. ranges = <0x00000000 0x00001100 0x00000100>;
  1672. dss-clkctrl@20 {
  1673. compatible = "ti,clkctrl";
  1674. reg = <0x00000020 0x00000014>;
  1675. #clock-cells = <0x00000002>;
  1676. phandle = <0x000000c7>;
  1677. };
  1678. };
  1679. l3init-cm@1300 {
  1680. compatible = "ti,omap4-cm";
  1681. reg = <0x00001300 0x00000100>;
  1682. #address-cells = <0x00000001>;
  1683. #size-cells = <0x00000001>;
  1684. ranges = <0x00000000 0x00001300 0x00000100>;
  1685. l3init-clkctrl@20 {
  1686. compatible = "ti,clkctrl";
  1687. reg = <0x00000020 0x0000006c 0x000000e0 0x00000014>;
  1688. #clock-cells = <0x00000002>;
  1689. phandle = <0x0000005a>;
  1690. };
  1691. pcie-clkctrl@b0 {
  1692. compatible = "ti,clkctrl";
  1693. reg = <0x000000b0 0x0000000c>;
  1694. #clock-cells = <0x00000002>;
  1695. phandle = <0x00000060>;
  1696. };
  1697. gmac-clkctrl@d0 {
  1698. compatible = "ti,clkctrl";
  1699. reg = <0x000000d0 0x00000004>;
  1700. #clock-cells = <0x00000002>;
  1701. phandle = <0x000000b2>;
  1702. };
  1703. };
  1704. l4per-cm@1700 {
  1705. compatible = "ti,omap4-cm";
  1706. reg = <0x00001700 0x00000300>;
  1707. #address-cells = <0x00000001>;
  1708. #size-cells = <0x00000001>;
  1709. ranges = <0x00000000 0x00001700 0x00000300>;
  1710. l4per-clkctrl@28 {
  1711. compatible = "ti,clkctrl";
  1712. reg = <0x00000028 0x00000064 0x000000a0 0x00000024 0x000000f0 0x0000003c 0x00000140 0x0000001c 0x00000170 0x00000004>;
  1713. #clock-cells = <0x00000002>;
  1714. assigned-clocks = <0x00000057 0x0000015c 0x00000018>;
  1715. assigned-clock-parents = <0x00000058>;
  1716. phandle = <0x00000090>;
  1717. };
  1718. l4sec-clkctrl@1a0 {
  1719. compatible = "ti,clkctrl";
  1720. reg = <0x000001a0 0x0000002c>;
  1721. #clock-cells = <0x00000002>;
  1722. phandle = <0x0000009a>;
  1723. };
  1724. l4per2-clkctrl@c {
  1725. compatible = "ti,clkctrl";
  1726. reg = <0x0000000c 0x00000004 0x00000018 0x0000000c 0x00000090 0x0000000c 0x000000c4 0x00000004 0x00000138 0x00000004 0x00000160 0x0000000c 0x00000178 0x00000024 0x000001d0 0x0000003c>;
  1727. #clock-cells = <0x00000002>;
  1728. phandle = <0x00000057>;
  1729. };
  1730. l4per3-clkctrl@14 {
  1731. compatible = "ti,clkctrl";
  1732. reg = <0x00000014 0x00000004 0x000000c8 0x00000014 0x00000130 0x00000004>;
  1733. #clock-cells = <0x00000002>;
  1734. phandle = <0x000000b7>;
  1735. };
  1736. };
  1737. };
  1738. };
  1739. target-module@56000 {
  1740. compatible = "ti,sysc-omap2", "ti,sysc";
  1741. ti,hwmods = "dma_system";
  1742. reg = <0x00056000 0x00000004 0x0005602c 0x00000004 0x00056028 0x00000004>;
  1743. reg-names = "rev", "sysc", "syss";
  1744. ti,sysc-mask = <0x00000323>;
  1745. ti,sysc-midle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  1746. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  1747. ti,syss-mask = <0x00000001>;
  1748. clocks = <0x00000059 0x00000000 0x00000000>;
  1749. clock-names = "fck";
  1750. #address-cells = <0x00000001>;
  1751. #size-cells = <0x00000001>;
  1752. ranges = <0x00000000 0x00056000 0x00001000>;
  1753. dma-controller@0 {
  1754. compatible = "ti,omap4430-sdma";
  1755. reg = <0x00000000 0x00001000>;
  1756. interrupts = <0x00000000 0x00000007 0x00000004 0x00000000 0x00000008 0x00000004 0x00000000 0x00000009 0x00000004 0x00000000 0x0000000a 0x00000004>;
  1757. #dma-cells = <0x00000001>;
  1758. dma-channels = <0x00000020>;
  1759. dma-requests = <0x0000007f>;
  1760. phandle = <0x0000000e>;
  1761. };
  1762. };
  1763. target-module@5e000 {
  1764. compatible = "ti,sysc";
  1765. status = "disabled";
  1766. #address-cells = <0x00000001>;
  1767. #size-cells = <0x00000001>;
  1768. ranges = <0x00000000 0x0005e000 0x00002000>;
  1769. };
  1770. target-module@80000 {
  1771. compatible = "ti,sysc-omap2", "ti,sysc";
  1772. ti,hwmods = "ocp2scp1";
  1773. reg = <0x00080000 0x00000004 0x00080010 0x00000004 0x00080014 0x00000004>;
  1774. reg-names = "rev", "sysc", "syss";
  1775. ti,sysc-mask = <0x00000003>;
  1776. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002>;
  1777. ti,syss-mask = <0x00000001>;
  1778. clocks = <0x0000005a 0x000000c0 0x00000000>;
  1779. clock-names = "fck";
  1780. #address-cells = <0x00000001>;
  1781. #size-cells = <0x00000001>;
  1782. ranges = <0x00000000 0x00080000 0x00008000>;
  1783. ocp2scp@0 {
  1784. compatible = "ti,omap-ocp2scp";
  1785. #address-cells = <0x00000001>;
  1786. #size-cells = <0x00000001>;
  1787. ranges = <0x00000000 0x00000000 0x00008000>;
  1788. reg = <0x00000000 0x00000020>;
  1789. phy@4000 {
  1790. compatible = "ti,dra7x-usb2", "ti,omap-usb2";
  1791. reg = <0x00004000 0x00000400>;
  1792. syscon-phy-power = <0x00000009 0x00000300>;
  1793. clocks = <0x0000005b 0x0000005a 0x000000d0 0x00000008>;
  1794. clock-names = "wkupclk", "refclk";
  1795. #phy-cells = <0x00000000>;
  1796. phy-supply = <0x0000005c>;
  1797. phandle = <0x000000b9>;
  1798. };
  1799. phy@5000 {
  1800. compatible = "ti,dra7x-usb2-phy2", "ti,omap-usb2";
  1801. reg = <0x00005000 0x00000400>;
  1802. syscon-phy-power = <0x00000009 0x00000e74>;
  1803. clocks = <0x0000005d 0x0000005a 0x00000020 0x00000008>;
  1804. clock-names = "wkupclk", "refclk";
  1805. #phy-cells = <0x00000000>;
  1806. phy-supply = <0x0000005c>;
  1807. phandle = <0x000000bc>;
  1808. };
  1809. phy@4400 {
  1810. compatible = "ti,omap-usb3";
  1811. reg = <0x00004400 0x00000080 0x00004800 0x00000064 0x00004c00 0x00000040>;
  1812. reg-names = "phy_rx", "phy_tx", "pll_ctrl";
  1813. syscon-phy-power = <0x00000009 0x00000370>;
  1814. clocks = <0x0000005e 0x00000011 0x0000005a 0x000000d0 0x00000008>;
  1815. clock-names = "wkupclk", "sysclk", "refclk";
  1816. #phy-cells = <0x00000000>;
  1817. phandle = <0x000000ba>;
  1818. };
  1819. };
  1820. };
  1821. target-module@90000 {
  1822. compatible = "ti,sysc-omap2", "ti,sysc";
  1823. ti,hwmods = "ocp2scp3";
  1824. reg = <0x00090000 0x00000004 0x00090010 0x00000004 0x00090014 0x00000004>;
  1825. reg-names = "rev", "sysc", "syss";
  1826. ti,sysc-mask = <0x00000003>;
  1827. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002>;
  1828. ti,syss-mask = <0x00000001>;
  1829. clocks = <0x0000005a 0x000000c8 0x00000000>;
  1830. clock-names = "fck";
  1831. #address-cells = <0x00000001>;
  1832. #size-cells = <0x00000001>;
  1833. ranges = <0x00000000 0x00090000 0x00008000>;
  1834. ocp2scp@0 {
  1835. compatible = "ti,omap-ocp2scp";
  1836. #address-cells = <0x00000001>;
  1837. #size-cells = <0x00000001>;
  1838. ranges = <0x00000000 0x00000000 0x00008000>;
  1839. reg = <0x00000000 0x00000020>;
  1840. pciephy@4000 {
  1841. compatible = "ti,phy-pipe3-pcie";
  1842. reg = <0x00004000 0x00000080 0x00004400 0x00000064>;
  1843. reg-names = "phy_rx", "phy_tx";
  1844. syscon-phy-power = <0x0000005f 0x0000001c>;
  1845. syscon-pcs = <0x0000005f 0x00000010>;
  1846. clocks = <0x0000003e 0x0000003f 0x00000060 0x00000000 0x00000008 0x00000060 0x00000000 0x00000009 0x00000060 0x00000000 0x0000000a 0x00000061 0x00000011>;
  1847. clock-names = "dpll_ref", "dpll_ref_m2", "wkupclk", "refclk", "div-clk", "phy-div", "sysclk";
  1848. #phy-cells = <0x00000000>;
  1849. phandle = <0x000000bd>;
  1850. };
  1851. pciephy@5000 {
  1852. compatible = "ti,phy-pipe3-pcie";
  1853. reg = <0x00005000 0x00000080 0x00005400 0x00000064>;
  1854. reg-names = "phy_rx", "phy_tx";
  1855. syscon-phy-power = <0x0000005f 0x00000020>;
  1856. syscon-pcs = <0x0000005f 0x00000010>;
  1857. clocks = <0x0000003e 0x0000003f 0x00000060 0x00000008 0x00000008 0x00000060 0x00000008 0x00000009 0x00000060 0x00000008 0x0000000a 0x00000061 0x00000011>;
  1858. clock-names = "dpll_ref", "dpll_ref_m2", "wkupclk", "refclk", "div-clk", "phy-div", "sysclk";
  1859. #phy-cells = <0x00000000>;
  1860. status = "disabled";
  1861. phandle = <0x000000c1>;
  1862. };
  1863. phy@6000 {
  1864. compatible = "ti,phy-pipe3-sata";
  1865. reg = <0x00006000 0x00000080 0x00006400 0x00000064 0x00006800 0x00000040>;
  1866. reg-names = "phy_rx", "phy_tx", "pll_ctrl";
  1867. syscon-phy-power = <0x00000009 0x00000374>;
  1868. clocks = <0x00000011 0x0000005a 0x00000068 0x00000008>;
  1869. clock-names = "sysclk", "refclk";
  1870. syscon-pllreset = <0x00000009 0x000003fc>;
  1871. #phy-cells = <0x00000000>;
  1872. phandle = <0x000000c6>;
  1873. };
  1874. };
  1875. };
  1876. target-module@a0000 {
  1877. compatible = "ti,sysc";
  1878. status = "disabled";
  1879. #address-cells = <0x00000001>;
  1880. #size-cells = <0x00000001>;
  1881. ranges = <0x00000000 0x000a0000 0x00008000>;
  1882. };
  1883. target-module@d9000 {
  1884. compatible = "ti,sysc-omap4-sr", "ti,sysc";
  1885. ti,hwmods = "smartreflex_mpu";
  1886. reg = <0x000d9038 0x00000004>;
  1887. reg-names = "sysc";
  1888. ti,sysc-mask = <0x04000000>;
  1889. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  1890. clocks = <0x00000062 0x00000008 0x00000000>;
  1891. clock-names = "fck";
  1892. #address-cells = <0x00000001>;
  1893. #size-cells = <0x00000001>;
  1894. ranges = <0x00000000 0x000d9000 0x00001000>;
  1895. };
  1896. target-module@dd000 {
  1897. compatible = "ti,sysc-omap4-sr", "ti,sysc";
  1898. ti,hwmods = "smartreflex_core";
  1899. reg = <0x000dd038 0x00000004>;
  1900. reg-names = "sysc";
  1901. ti,sysc-mask = <0x04000000>;
  1902. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  1903. clocks = <0x00000062 0x00000018 0x00000000>;
  1904. clock-names = "fck";
  1905. #address-cells = <0x00000001>;
  1906. #size-cells = <0x00000001>;
  1907. ranges = <0x00000000 0x000dd000 0x00001000>;
  1908. };
  1909. target-module@e0000 {
  1910. compatible = "ti,sysc";
  1911. status = "disabled";
  1912. #address-cells = <0x00000001>;
  1913. #size-cells = <0x00000001>;
  1914. ranges = <0x00000000 0x000e0000 0x00001000>;
  1915. };
  1916. target-module@f4000 {
  1917. compatible = "ti,sysc-omap4", "ti,sysc";
  1918. ti,hwmods = "mailbox1";
  1919. reg = <0x000f4000 0x00000004 0x000f4010 0x00000004>;
  1920. reg-names = "rev", "sysc";
  1921. ti,sysc-mask = <0x00000001>;
  1922. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002>;
  1923. clocks = <0x00000063 0x00000010 0x00000000>;
  1924. clock-names = "fck";
  1925. #address-cells = <0x00000001>;
  1926. #size-cells = <0x00000001>;
  1927. ranges = <0x00000000 0x000f4000 0x00001000>;
  1928. mailbox@0 {
  1929. compatible = "ti,omap4-mailbox";
  1930. reg = <0x00000000 0x00000200>;
  1931. interrupts = <0x00000000 0x00000015 0x00000004 0x00000000 0x00000087 0x00000004 0x00000000 0x00000086 0x00000004>;
  1932. #mbox-cells = <0x00000001>;
  1933. ti,mbox-num-users = <0x00000003>;
  1934. ti,mbox-num-fifos = <0x00000008>;
  1935. status = "disabled";
  1936. };
  1937. };
  1938. target-module@f6000 {
  1939. compatible = "ti,sysc-omap2", "ti,sysc";
  1940. ti,hwmods = "spinlock";
  1941. reg = <0x000f6000 0x00000004 0x000f6010 0x00000004 0x000f6014 0x00000004>;
  1942. reg-names = "rev", "sysc", "syss";
  1943. ti,sysc-mask = <0x00000007>;
  1944. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002>;
  1945. ti,syss-mask = <0x00000001>;
  1946. clocks = <0x00000063 0x00000008 0x00000000>;
  1947. clock-names = "fck";
  1948. #address-cells = <0x00000001>;
  1949. #size-cells = <0x00000001>;
  1950. ranges = <0x00000000 0x000f6000 0x00001000>;
  1951. spinlock@0 {
  1952. compatible = "ti,omap4-hwspinlock";
  1953. reg = <0x00000000 0x00001000>;
  1954. #hwlock-cells = <0x00000001>;
  1955. };
  1956. };
  1957. };
  1958. segment@100000 {
  1959. compatible = "simple-bus";
  1960. #address-cells = <0x00000001>;
  1961. #size-cells = <0x00000001>;
  1962. ranges = * 0x83009540 [0x000002b8];
  1963. target-module@2000 {
  1964. compatible = "ti,sysc";
  1965. status = "disabled";
  1966. #address-cells = <0x00000001>;
  1967. #size-cells = <0x00000001>;
  1968. ranges = <0x00000000 0x00002000 0x00001000>;
  1969. };
  1970. target-module@8000 {
  1971. compatible = "ti,sysc";
  1972. status = "disabled";
  1973. #address-cells = <0x00000001>;
  1974. #size-cells = <0x00000001>;
  1975. ranges = <0x00000000 0x00008000 0x00001000>;
  1976. };
  1977. target-module@40000 {
  1978. compatible = "ti,sysc";
  1979. status = "disabled";
  1980. #address-cells = <0x00000001>;
  1981. #size-cells = <0x00000001>;
  1982. ranges = <0x00000000 0x00040000 0x00010000>;
  1983. };
  1984. target-module@51000 {
  1985. compatible = "ti,sysc";
  1986. status = "disabled";
  1987. #address-cells = <0x00000001>;
  1988. #size-cells = <0x00000001>;
  1989. ranges = <0x00000000 0x00051000 0x00001000>;
  1990. };
  1991. target-module@53000 {
  1992. compatible = "ti,sysc";
  1993. status = "disabled";
  1994. #address-cells = <0x00000001>;
  1995. #size-cells = <0x00000001>;
  1996. ranges = <0x00000000 0x00053000 0x00001000>;
  1997. };
  1998. target-module@55000 {
  1999. compatible = "ti,sysc";
  2000. status = "disabled";
  2001. #address-cells = <0x00000001>;
  2002. #size-cells = <0x00000001>;
  2003. ranges = <0x00000000 0x00055000 0x00001000>;
  2004. };
  2005. target-module@57000 {
  2006. compatible = "ti,sysc";
  2007. status = "disabled";
  2008. #address-cells = <0x00000001>;
  2009. #size-cells = <0x00000001>;
  2010. ranges = <0x00000000 0x00057000 0x00001000>;
  2011. };
  2012. target-module@59000 {
  2013. compatible = "ti,sysc";
  2014. status = "disabled";
  2015. #address-cells = <0x00000001>;
  2016. #size-cells = <0x00000001>;
  2017. ranges = <0x00000000 0x00059000 0x00001000>;
  2018. };
  2019. target-module@5b000 {
  2020. compatible = "ti,sysc";
  2021. status = "disabled";
  2022. #address-cells = <0x00000001>;
  2023. #size-cells = <0x00000001>;
  2024. ranges = <0x00000000 0x0005b000 0x00001000>;
  2025. };
  2026. target-module@5d000 {
  2027. compatible = "ti,sysc";
  2028. status = "disabled";
  2029. #address-cells = <0x00000001>;
  2030. #size-cells = <0x00000001>;
  2031. ranges = <0x00000000 0x0005d000 0x00001000>;
  2032. };
  2033. target-module@5f000 {
  2034. compatible = "ti,sysc";
  2035. status = "disabled";
  2036. #address-cells = <0x00000001>;
  2037. #size-cells = <0x00000001>;
  2038. ranges = <0x00000000 0x0005f000 0x00001000>;
  2039. };
  2040. target-module@61000 {
  2041. compatible = "ti,sysc";
  2042. status = "disabled";
  2043. #address-cells = <0x00000001>;
  2044. #size-cells = <0x00000001>;
  2045. ranges = <0x00000000 0x00061000 0x00001000>;
  2046. };
  2047. target-module@63000 {
  2048. compatible = "ti,sysc";
  2049. status = "disabled";
  2050. #address-cells = <0x00000001>;
  2051. #size-cells = <0x00000001>;
  2052. ranges = <0x00000000 0x00063000 0x00001000>;
  2053. };
  2054. target-module@65000 {
  2055. compatible = "ti,sysc";
  2056. status = "disabled";
  2057. #address-cells = <0x00000001>;
  2058. #size-cells = <0x00000001>;
  2059. ranges = <0x00000000 0x00065000 0x00001000>;
  2060. };
  2061. target-module@67000 {
  2062. compatible = "ti,sysc";
  2063. status = "disabled";
  2064. #address-cells = <0x00000001>;
  2065. #size-cells = <0x00000001>;
  2066. ranges = <0x00000000 0x00067000 0x00001000>;
  2067. };
  2068. target-module@69000 {
  2069. compatible = "ti,sysc";
  2070. status = "disabled";
  2071. #address-cells = <0x00000001>;
  2072. #size-cells = <0x00000001>;
  2073. ranges = <0x00000000 0x00069000 0x00001000>;
  2074. };
  2075. target-module@6b000 {
  2076. compatible = "ti,sysc";
  2077. status = "disabled";
  2078. #address-cells = <0x00000001>;
  2079. #size-cells = <0x00000001>;
  2080. ranges = <0x00000000 0x0006b000 0x00001000>;
  2081. };
  2082. target-module@6d000 {
  2083. compatible = "ti,sysc";
  2084. status = "disabled";
  2085. #address-cells = <0x00000001>;
  2086. #size-cells = <0x00000001>;
  2087. ranges = <0x00000000 0x0006d000 0x00001000>;
  2088. };
  2089. target-module@71000 {
  2090. compatible = "ti,sysc";
  2091. status = "disabled";
  2092. #address-cells = <0x00000001>;
  2093. #size-cells = <0x00000001>;
  2094. ranges = <0x00000000 0x00071000 0x00001000>;
  2095. };
  2096. target-module@73000 {
  2097. compatible = "ti,sysc";
  2098. status = "disabled";
  2099. #address-cells = <0x00000001>;
  2100. #size-cells = <0x00000001>;
  2101. ranges = <0x00000000 0x00073000 0x00001000>;
  2102. };
  2103. target-module@75000 {
  2104. compatible = "ti,sysc";
  2105. status = "disabled";
  2106. #address-cells = <0x00000001>;
  2107. #size-cells = <0x00000001>;
  2108. ranges = <0x00000000 0x00075000 0x00001000>;
  2109. };
  2110. target-module@77000 {
  2111. compatible = "ti,sysc";
  2112. status = "disabled";
  2113. #address-cells = <0x00000001>;
  2114. #size-cells = <0x00000001>;
  2115. ranges = <0x00000000 0x00077000 0x00001000>;
  2116. };
  2117. target-module@79000 {
  2118. compatible = "ti,sysc";
  2119. status = "disabled";
  2120. #address-cells = <0x00000001>;
  2121. #size-cells = <0x00000001>;
  2122. ranges = <0x00000000 0x00079000 0x00001000>;
  2123. };
  2124. target-module@7b000 {
  2125. compatible = "ti,sysc";
  2126. status = "disabled";
  2127. #address-cells = <0x00000001>;
  2128. #size-cells = <0x00000001>;
  2129. ranges = <0x00000000 0x0007b000 0x00001000>;
  2130. };
  2131. target-module@7d000 {
  2132. compatible = "ti,sysc";
  2133. status = "disabled";
  2134. #address-cells = <0x00000001>;
  2135. #size-cells = <0x00000001>;
  2136. ranges = <0x00000000 0x0007d000 0x00001000>;
  2137. };
  2138. target-module@81000 {
  2139. compatible = "ti,sysc";
  2140. status = "disabled";
  2141. #address-cells = <0x00000001>;
  2142. #size-cells = <0x00000001>;
  2143. ranges = <0x00000000 0x00081000 0x00001000>;
  2144. };
  2145. target-module@83000 {
  2146. compatible = "ti,sysc";
  2147. status = "disabled";
  2148. #address-cells = <0x00000001>;
  2149. #size-cells = <0x00000001>;
  2150. ranges = <0x00000000 0x00083000 0x00001000>;
  2151. };
  2152. target-module@85000 {
  2153. compatible = "ti,sysc";
  2154. status = "disabled";
  2155. #address-cells = <0x00000001>;
  2156. #size-cells = <0x00000001>;
  2157. ranges = <0x00000000 0x00085000 0x00001000>;
  2158. };
  2159. target-module@87000 {
  2160. compatible = "ti,sysc";
  2161. status = "disabled";
  2162. #address-cells = <0x00000001>;
  2163. #size-cells = <0x00000001>;
  2164. ranges = <0x00000000 0x00087000 0x00001000>;
  2165. };
  2166. };
  2167. segment@200000 {
  2168. compatible = "simple-bus";
  2169. #address-cells = <0x00000001>;
  2170. #size-cells = <0x00000001>;
  2171. ranges = * 0x8300a6d4 [0x000001f8];
  2172. target-module@0 {
  2173. compatible = "ti,sysc";
  2174. status = "disabled";
  2175. #address-cells = <0x00000001>;
  2176. #size-cells = <0x00000001>;
  2177. ranges = <0x00000000 0x00000000 0x00001000>;
  2178. };
  2179. target-module@a000 {
  2180. compatible = "ti,sysc";
  2181. status = "disabled";
  2182. #address-cells = <0x00000001>;
  2183. #size-cells = <0x00000001>;
  2184. ranges = <0x00000000 0x0000a000 0x00001000>;
  2185. };
  2186. target-module@c000 {
  2187. compatible = "ti,sysc";
  2188. status = "disabled";
  2189. #address-cells = <0x00000001>;
  2190. #size-cells = <0x00000001>;
  2191. ranges = <0x00000000 0x0000c000 0x00001000>;
  2192. };
  2193. target-module@e000 {
  2194. compatible = "ti,sysc";
  2195. status = "disabled";
  2196. #address-cells = <0x00000001>;
  2197. #size-cells = <0x00000001>;
  2198. ranges = <0x00000000 0x0000e000 0x00001000>;
  2199. };
  2200. target-module@10000 {
  2201. compatible = "ti,sysc";
  2202. status = "disabled";
  2203. #address-cells = <0x00000001>;
  2204. #size-cells = <0x00000001>;
  2205. ranges = <0x00000000 0x00010000 0x00001000>;
  2206. };
  2207. target-module@12000 {
  2208. compatible = "ti,sysc";
  2209. status = "disabled";
  2210. #address-cells = <0x00000001>;
  2211. #size-cells = <0x00000001>;
  2212. ranges = <0x00000000 0x00012000 0x00001000>;
  2213. };
  2214. target-module@14000 {
  2215. compatible = "ti,sysc";
  2216. status = "disabled";
  2217. #address-cells = <0x00000001>;
  2218. #size-cells = <0x00000001>;
  2219. ranges = <0x00000000 0x00014000 0x00001000>;
  2220. };
  2221. target-module@18000 {
  2222. compatible = "ti,sysc";
  2223. status = "disabled";
  2224. #address-cells = <0x00000001>;
  2225. #size-cells = <0x00000001>;
  2226. ranges = <0x00000000 0x00018000 0x00001000>;
  2227. };
  2228. target-module@1a000 {
  2229. compatible = "ti,sysc";
  2230. status = "disabled";
  2231. #address-cells = <0x00000001>;
  2232. #size-cells = <0x00000001>;
  2233. ranges = <0x00000000 0x0001a000 0x00001000>;
  2234. };
  2235. target-module@1c000 {
  2236. compatible = "ti,sysc";
  2237. status = "disabled";
  2238. #address-cells = <0x00000001>;
  2239. #size-cells = <0x00000001>;
  2240. ranges = <0x00000000 0x0001c000 0x00001000>;
  2241. };
  2242. target-module@1e000 {
  2243. compatible = "ti,sysc";
  2244. status = "disabled";
  2245. #address-cells = <0x00000001>;
  2246. #size-cells = <0x00000001>;
  2247. ranges = <0x00000000 0x0001e000 0x00001000>;
  2248. };
  2249. target-module@20000 {
  2250. compatible = "ti,sysc";
  2251. status = "disabled";
  2252. #address-cells = <0x00000001>;
  2253. #size-cells = <0x00000001>;
  2254. ranges = <0x00000000 0x00020000 0x00001000>;
  2255. };
  2256. target-module@24000 {
  2257. compatible = "ti,sysc";
  2258. status = "disabled";
  2259. #address-cells = <0x00000001>;
  2260. #size-cells = <0x00000001>;
  2261. ranges = <0x00000000 0x00024000 0x00001000>;
  2262. };
  2263. target-module@26000 {
  2264. compatible = "ti,sysc";
  2265. status = "disabled";
  2266. #address-cells = <0x00000001>;
  2267. #size-cells = <0x00000001>;
  2268. ranges = <0x00000000 0x00026000 0x00001000>;
  2269. };
  2270. target-module@2a000 {
  2271. compatible = "ti,sysc";
  2272. status = "disabled";
  2273. #address-cells = <0x00000001>;
  2274. #size-cells = <0x00000001>;
  2275. ranges = <0x00000000 0x0002a000 0x00001000>;
  2276. };
  2277. target-module@2c000 {
  2278. compatible = "ti,sysc";
  2279. status = "disabled";
  2280. #address-cells = <0x00000001>;
  2281. #size-cells = <0x00000001>;
  2282. ranges = <0x00000000 0x0002c000 0x00001000>;
  2283. };
  2284. target-module@2e000 {
  2285. compatible = "ti,sysc";
  2286. status = "disabled";
  2287. #address-cells = <0x00000001>;
  2288. #size-cells = <0x00000001>;
  2289. ranges = <0x00000000 0x0002e000 0x00001000>;
  2290. };
  2291. target-module@30000 {
  2292. compatible = "ti,sysc";
  2293. status = "disabled";
  2294. #address-cells = <0x00000001>;
  2295. #size-cells = <0x00000001>;
  2296. ranges = <0x00000000 0x00030000 0x00001000>;
  2297. };
  2298. target-module@32000 {
  2299. compatible = "ti,sysc";
  2300. status = "disabled";
  2301. #address-cells = <0x00000001>;
  2302. #size-cells = <0x00000001>;
  2303. ranges = <0x00000000 0x00032000 0x00001000>;
  2304. };
  2305. target-module@34000 {
  2306. compatible = "ti,sysc";
  2307. status = "disabled";
  2308. #address-cells = <0x00000001>;
  2309. #size-cells = <0x00000001>;
  2310. ranges = <0x00000000 0x00034000 0x00001000>;
  2311. };
  2312. target-module@36000 {
  2313. compatible = "ti,sysc";
  2314. status = "disabled";
  2315. #address-cells = <0x00000001>;
  2316. #size-cells = <0x00000001>;
  2317. ranges = <0x00000000 0x00036000 0x00001000>;
  2318. };
  2319. };
  2320. };
  2321. interconnect@4ae00000 {
  2322. compatible = "ti,dra7-l4-wkup", "simple-bus";
  2323. reg = <0x4ae00000 0x00000800 0x4ae00800 0x00000800 0x4ae01000 0x00001000>;
  2324. reg-names = "ap", "la", "ia0";
  2325. #address-cells = <0x00000001>;
  2326. #size-cells = <0x00000001>;
  2327. ranges = <0x00000000 0x4ae00000 0x00010000 0x00010000 0x4ae10000 0x00010000 0x00020000 0x4ae20000 0x00010000 0x00030000 0x4ae30000 0x00010000>;
  2328. segment@0 {
  2329. compatible = "simple-bus";
  2330. #address-cells = <0x00000001>;
  2331. #size-cells = <0x00000001>;
  2332. ranges = * 0x8300b480 [0x0000006c];
  2333. target-module@4000 {
  2334. compatible = "ti,sysc-omap2", "ti,sysc";
  2335. ti,hwmods = "counter_32k";
  2336. reg = <0x00004000 0x00000004 0x00004010 0x00000004>;
  2337. reg-names = "rev", "sysc";
  2338. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  2339. clocks = <0x00000064 0x00000030 0x00000000>;
  2340. clock-names = "fck";
  2341. #address-cells = <0x00000001>;
  2342. #size-cells = <0x00000001>;
  2343. ranges = <0x00000000 0x00004000 0x00001000>;
  2344. counter@0 {
  2345. compatible = "ti,omap-counter32k";
  2346. reg = <0x00000000 0x00000040>;
  2347. };
  2348. };
  2349. target-module@6000 {
  2350. compatible = "ti,sysc-omap4", "ti,sysc";
  2351. reg = <0x00006000 0x00000004>;
  2352. reg-names = "rev";
  2353. #address-cells = <0x00000001>;
  2354. #size-cells = <0x00000001>;
  2355. ranges = <0x00000000 0x00006000 0x00002000>;
  2356. prm@0 {
  2357. compatible = "ti,dra7-prm", "simple-bus";
  2358. reg = <0x00000000 0x00003000>;
  2359. interrupts = <0x00000000 0x00000006 0x00000004>;
  2360. #address-cells = <0x00000001>;
  2361. #size-cells = <0x00000001>;
  2362. ranges = <0x00000000 0x00000000 0x00003000>;
  2363. clocks {
  2364. #address-cells = <0x00000001>;
  2365. #size-cells = <0x00000000>;
  2366. sys_clkin1@110 {
  2367. #clock-cells = <0x00000000>;
  2368. compatible = "ti,mux-clock";
  2369. clocks = <0x00000065 0x00000066 0x00000067 0x00000068 0x00000069 0x0000006a 0x0000006b>;
  2370. reg = <0x00000110>;
  2371. ti,index-starts-at-one;
  2372. phandle = <0x00000011>;
  2373. };
  2374. abe_dpll_sys_clk_mux@118 {
  2375. #clock-cells = <0x00000000>;
  2376. compatible = "ti,mux-clock";
  2377. clocks = <0x00000011 0x0000006c>;
  2378. reg = <0x00000118>;
  2379. phandle = <0x0000006d>;
  2380. };
  2381. abe_dpll_bypass_clk_mux@114 {
  2382. #clock-cells = <0x00000000>;
  2383. compatible = "ti,mux-clock";
  2384. clocks = <0x0000006d 0x00000050>;
  2385. reg = <0x00000114>;
  2386. phandle = <0x00000013>;
  2387. };
  2388. abe_dpll_clk_mux@10c {
  2389. #clock-cells = <0x00000000>;
  2390. compatible = "ti,mux-clock";
  2391. clocks = <0x0000006d 0x00000050>;
  2392. reg = <0x0000010c>;
  2393. phandle = <0x00000012>;
  2394. };
  2395. abe_24m_fclk@11c {
  2396. #clock-cells = <0x00000000>;
  2397. compatible = "ti,divider-clock";
  2398. clocks = <0x00000016>;
  2399. reg = <0x0000011c>;
  2400. ti,dividers = <0x00000008 0x00000010>;
  2401. phandle = <0x00000058>;
  2402. };
  2403. aess_fclk@178 {
  2404. #clock-cells = <0x00000000>;
  2405. compatible = "ti,divider-clock";
  2406. clocks = <0x0000006e>;
  2407. reg = <0x00000178>;
  2408. ti,max-div = <0x00000002>;
  2409. phandle = <0x0000006f>;
  2410. };
  2411. abe_giclk_div@174 {
  2412. #clock-cells = <0x00000000>;
  2413. compatible = "ti,divider-clock";
  2414. clocks = <0x0000006f>;
  2415. reg = <0x00000174>;
  2416. ti,max-div = <0x00000002>;
  2417. };
  2418. abe_lp_clk_div@1d8 {
  2419. #clock-cells = <0x00000000>;
  2420. compatible = "ti,divider-clock";
  2421. clocks = <0x00000016>;
  2422. reg = <0x000001d8>;
  2423. ti,dividers = <0x00000010 0x00000020>;
  2424. phandle = <0x0000008f>;
  2425. };
  2426. abe_sys_clk_div@120 {
  2427. #clock-cells = <0x00000000>;
  2428. compatible = "ti,divider-clock";
  2429. clocks = <0x00000011>;
  2430. reg = <0x00000120>;
  2431. ti,max-div = <0x00000002>;
  2432. };
  2433. adc_gfclk_mux@1dc {
  2434. #clock-cells = <0x00000000>;
  2435. compatible = "ti,mux-clock";
  2436. clocks = <0x00000011 0x0000006c 0x00000050>;
  2437. reg = <0x000001dc>;
  2438. };
  2439. sys_clk1_dclk_div@1c8 {
  2440. #clock-cells = <0x00000000>;
  2441. compatible = "ti,divider-clock";
  2442. clocks = <0x00000011>;
  2443. ti,max-div = <0x00000040>;
  2444. reg = <0x000001c8>;
  2445. ti,index-power-of-two;
  2446. phandle = <0x00000078>;
  2447. };
  2448. sys_clk2_dclk_div@1cc {
  2449. #clock-cells = <0x00000000>;
  2450. compatible = "ti,divider-clock";
  2451. clocks = <0x0000006c>;
  2452. ti,max-div = <0x00000040>;
  2453. reg = <0x000001cc>;
  2454. ti,index-power-of-two;
  2455. phandle = <0x00000079>;
  2456. };
  2457. per_abe_x1_dclk_div@1bc {
  2458. #clock-cells = <0x00000000>;
  2459. compatible = "ti,divider-clock";
  2460. clocks = <0x00000070>;
  2461. ti,max-div = <0x00000040>;
  2462. reg = <0x000001bc>;
  2463. ti,index-power-of-two;
  2464. phandle = <0x0000007a>;
  2465. };
  2466. dsp_gclk_div@18c {
  2467. #clock-cells = <0x00000000>;
  2468. compatible = "ti,divider-clock";
  2469. clocks = <0x00000021>;
  2470. ti,max-div = <0x00000040>;
  2471. reg = <0x0000018c>;
  2472. ti,index-power-of-two;
  2473. phandle = <0x0000007c>;
  2474. };
  2475. gpu_dclk@1a0 {
  2476. #clock-cells = <0x00000000>;
  2477. compatible = "ti,divider-clock";
  2478. clocks = <0x00000028>;
  2479. ti,max-div = <0x00000040>;
  2480. reg = <0x000001a0>;
  2481. ti,index-power-of-two;
  2482. phandle = <0x0000007e>;
  2483. };
  2484. emif_phy_dclk_div@190 {
  2485. #clock-cells = <0x00000000>;
  2486. compatible = "ti,divider-clock";
  2487. clocks = <0x00000071>;
  2488. ti,max-div = <0x00000040>;
  2489. reg = <0x00000190>;
  2490. ti,index-power-of-two;
  2491. phandle = <0x00000080>;
  2492. };
  2493. gmac_250m_dclk_div@19c {
  2494. #clock-cells = <0x00000000>;
  2495. compatible = "ti,divider-clock";
  2496. clocks = <0x00000072>;
  2497. ti,max-div = <0x00000040>;
  2498. reg = <0x0000019c>;
  2499. ti,index-power-of-two;
  2500. phandle = <0x00000073>;
  2501. };
  2502. gmac_main_clk {
  2503. #clock-cells = <0x00000000>;
  2504. compatible = "fixed-factor-clock";
  2505. clocks = <0x00000073>;
  2506. clock-mult = <0x00000001>;
  2507. clock-div = <0x00000002>;
  2508. phandle = <0x000000b3>;
  2509. };
  2510. l3init_480m_dclk_div@1ac {
  2511. #clock-cells = <0x00000000>;
  2512. compatible = "ti,divider-clock";
  2513. clocks = <0x0000004d>;
  2514. ti,max-div = <0x00000040>;
  2515. reg = <0x000001ac>;
  2516. ti,index-power-of-two;
  2517. phandle = <0x00000085>;
  2518. };
  2519. usb_otg_dclk_div@184 {
  2520. #clock-cells = <0x00000000>;
  2521. compatible = "ti,divider-clock";
  2522. clocks = <0x00000074>;
  2523. ti,max-div = <0x00000040>;
  2524. reg = <0x00000184>;
  2525. ti,index-power-of-two;
  2526. phandle = <0x00000086>;
  2527. };
  2528. sata_dclk_div@1c0 {
  2529. #clock-cells = <0x00000000>;
  2530. compatible = "ti,divider-clock";
  2531. clocks = <0x00000011>;
  2532. ti,max-div = <0x00000040>;
  2533. reg = <0x000001c0>;
  2534. ti,index-power-of-two;
  2535. phandle = <0x00000087>;
  2536. };
  2537. pcie2_dclk_div@1b8 {
  2538. #clock-cells = <0x00000000>;
  2539. compatible = "ti,divider-clock";
  2540. clocks = <0x00000075>;
  2541. ti,max-div = <0x00000040>;
  2542. reg = <0x000001b8>;
  2543. ti,index-power-of-two;
  2544. phandle = <0x00000088>;
  2545. };
  2546. pcie_dclk_div@1b4 {
  2547. #clock-cells = <0x00000000>;
  2548. compatible = "ti,divider-clock";
  2549. clocks = <0x00000076>;
  2550. ti,max-div = <0x00000040>;
  2551. reg = <0x000001b4>;
  2552. ti,index-power-of-two;
  2553. phandle = <0x00000089>;
  2554. };
  2555. emu_dclk_div@194 {
  2556. #clock-cells = <0x00000000>;
  2557. compatible = "ti,divider-clock";
  2558. clocks = <0x00000011>;
  2559. ti,max-div = <0x00000040>;
  2560. reg = <0x00000194>;
  2561. ti,index-power-of-two;
  2562. phandle = <0x0000008a>;
  2563. };
  2564. secure_32k_dclk_div@1c4 {
  2565. #clock-cells = <0x00000000>;
  2566. compatible = "ti,divider-clock";
  2567. clocks = <0x00000077>;
  2568. ti,max-div = <0x00000040>;
  2569. reg = <0x000001c4>;
  2570. ti,index-power-of-two;
  2571. phandle = <0x0000008b>;
  2572. };
  2573. clkoutmux0_clk_mux@158 {
  2574. #clock-cells = <0x00000000>;
  2575. compatible = "ti,mux-clock";
  2576. clocks = * 0x8300c610 [0x00000058];
  2577. reg = <0x00000158>;
  2578. };
  2579. clkoutmux1_clk_mux@15c {
  2580. #clock-cells = <0x00000000>;
  2581. compatible = "ti,mux-clock";
  2582. clocks = * 0x8300c6d0 [0x00000058];
  2583. reg = <0x0000015c>;
  2584. };
  2585. clkoutmux2_clk_mux@160 {
  2586. #clock-cells = <0x00000000>;
  2587. compatible = "ti,mux-clock";
  2588. clocks = * 0x8300c790 [0x00000058];
  2589. reg = <0x00000160>;
  2590. phandle = <0x0000004e>;
  2591. };
  2592. custefuse_sys_gfclk_div {
  2593. #clock-cells = <0x00000000>;
  2594. compatible = "fixed-factor-clock";
  2595. clocks = <0x00000011>;
  2596. clock-mult = <0x00000001>;
  2597. clock-div = <0x00000002>;
  2598. };
  2599. eve_clk@180 {
  2600. #clock-cells = <0x00000000>;
  2601. compatible = "ti,mux-clock";
  2602. clocks = <0x00000034 0x00000037>;
  2603. reg = <0x00000180>;
  2604. };
  2605. hdmi_dpll_clk_mux@164 {
  2606. #clock-cells = <0x00000000>;
  2607. compatible = "ti,mux-clock";
  2608. clocks = <0x00000011 0x0000006c>;
  2609. reg = <0x00000164>;
  2610. };
  2611. mlb_clk@134 {
  2612. #clock-cells = <0x00000000>;
  2613. compatible = "ti,divider-clock";
  2614. clocks = <0x0000008d>;
  2615. ti,max-div = <0x00000040>;
  2616. reg = <0x00000134>;
  2617. ti,index-power-of-two;
  2618. };
  2619. mlbp_clk@130 {
  2620. #clock-cells = <0x00000000>;
  2621. compatible = "ti,divider-clock";
  2622. clocks = <0x0000008e>;
  2623. ti,max-div = <0x00000040>;
  2624. reg = <0x00000130>;
  2625. ti,index-power-of-two;
  2626. };
  2627. per_abe_x1_gfclk2_div@138 {
  2628. #clock-cells = <0x00000000>;
  2629. compatible = "ti,divider-clock";
  2630. clocks = <0x00000070>;
  2631. ti,max-div = <0x00000040>;
  2632. reg = <0x00000138>;
  2633. ti,index-power-of-two;
  2634. };
  2635. timer_sys_clk_div@144 {
  2636. #clock-cells = <0x00000000>;
  2637. compatible = "ti,divider-clock";
  2638. clocks = <0x00000011>;
  2639. reg = <0x00000144>;
  2640. ti,max-div = <0x00000002>;
  2641. };
  2642. video1_dpll_clk_mux@168 {
  2643. #clock-cells = <0x00000000>;
  2644. compatible = "ti,mux-clock";
  2645. clocks = <0x00000011 0x0000006c>;
  2646. reg = <0x00000168>;
  2647. };
  2648. video2_dpll_clk_mux@16c {
  2649. #clock-cells = <0x00000000>;
  2650. compatible = "ti,mux-clock";
  2651. clocks = <0x00000011 0x0000006c>;
  2652. reg = <0x0000016c>;
  2653. };
  2654. wkupaon_iclk_mux@108 {
  2655. #clock-cells = <0x00000000>;
  2656. compatible = "ti,mux-clock";
  2657. clocks = <0x00000011 0x0000008f>;
  2658. reg = <0x00000108>;
  2659. phandle = <0x00000055>;
  2660. };
  2661. };
  2662. clockdomains {
  2663. };
  2664. wkupaon-cm@1800 {
  2665. compatible = "ti,omap4-cm";
  2666. reg = <0x00001800 0x00000100>;
  2667. #address-cells = <0x00000001>;
  2668. #size-cells = <0x00000001>;
  2669. ranges = <0x00000000 0x00001800 0x00000100>;
  2670. wkupaon-clkctrl@20 {
  2671. compatible = "ti,clkctrl";
  2672. reg = <0x00000020 0x0000006c>;
  2673. #clock-cells = <0x00000002>;
  2674. phandle = <0x00000064>;
  2675. };
  2676. };
  2677. };
  2678. };
  2679. target-module@c000 {
  2680. compatible = "ti,sysc-omap4", "ti,sysc";
  2681. reg = <0x0000c000 0x00000004>;
  2682. reg-names = "rev";
  2683. #address-cells = <0x00000001>;
  2684. #size-cells = <0x00000001>;
  2685. ranges = <0x00000000 0x0000c000 0x00001000>;
  2686. scm_conf@0 {
  2687. compatible = "syscon";
  2688. reg = <0x00000000 0x00001000>;
  2689. phandle = <0x00000007>;
  2690. };
  2691. };
  2692. };
  2693. segment@10000 {
  2694. compatible = "simple-bus";
  2695. #address-cells = <0x00000001>;
  2696. #size-cells = <0x00000001>;
  2697. ranges = * 0x8300cf20 [0x00000060];
  2698. target-module@0 {
  2699. compatible = "ti,sysc-omap2", "ti,sysc";
  2700. ti,hwmods = "gpio1";
  2701. reg = <0x00000000 0x00000004 0x00000010 0x00000004 0x00000114 0x00000004>;
  2702. reg-names = "rev", "sysc", "syss";
  2703. ti,sysc-mask = <0x00000007>;
  2704. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  2705. ti,syss-mask = <0x00000001>;
  2706. clocks = <0x00000064 0x00000018 0x00000000 0x00000064 0x00000018 0x00000008>;
  2707. clock-names = "fck", "dbclk";
  2708. #address-cells = <0x00000001>;
  2709. #size-cells = <0x00000001>;
  2710. ranges = <0x00000000 0x00000000 0x00001000>;
  2711. gpio@0 {
  2712. compatible = "ti,omap4-gpio";
  2713. reg = <0x00000000 0x00000200>;
  2714. interrupts = <0x00000000 0x00000018 0x00000004>;
  2715. gpio-controller;
  2716. #gpio-cells = <0x00000002>;
  2717. interrupt-controller;
  2718. #interrupt-cells = <0x00000002>;
  2719. phandle = <0x00000095>;
  2720. };
  2721. };
  2722. target-module@4000 {
  2723. compatible = "ti,sysc-omap2", "ti,sysc";
  2724. ti,hwmods = "wd_timer2";
  2725. reg = <0x00004000 0x00000004 0x00004010 0x00000004 0x00004014 0x00000004>;
  2726. reg-names = "rev", "sysc", "syss";
  2727. ti,sysc-mask = <0x00000022>;
  2728. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  2729. ti,syss-mask = <0x00000001>;
  2730. clocks = <0x00000064 0x00000010 0x00000000>;
  2731. clock-names = "fck";
  2732. #address-cells = <0x00000001>;
  2733. #size-cells = <0x00000001>;
  2734. ranges = <0x00000000 0x00004000 0x00001000>;
  2735. wdt@0 {
  2736. compatible = "ti,omap3-wdt";
  2737. reg = <0x00000000 0x00000080>;
  2738. interrupts = <0x00000000 0x0000004b 0x00000004>;
  2739. };
  2740. };
  2741. target-module@8000 {
  2742. compatible = "ti,sysc-omap4-timer", "ti,sysc";
  2743. ti,hwmods = "timer1";
  2744. reg = <0x00008000 0x00000004 0x00008010 0x00000004>;
  2745. reg-names = "rev", "sysc";
  2746. ti,sysc-mask = <0x00000003>;
  2747. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  2748. clocks = <0x00000064 0x00000020 0x00000000>;
  2749. clock-names = "fck";
  2750. #address-cells = <0x00000001>;
  2751. #size-cells = <0x00000001>;
  2752. ranges = <0x00000000 0x00008000 0x00001000>;
  2753. timer@0 {
  2754. compatible = "ti,omap5430-timer";
  2755. reg = <0x00000000 0x00000080>;
  2756. clocks = <0x00000064 0x00000020 0x00000018>;
  2757. clock-names = "fck";
  2758. interrupts = <0x00000000 0x00000020 0x00000004>;
  2759. ti,timer-alwon;
  2760. };
  2761. };
  2762. target-module@c000 {
  2763. compatible = "ti,sysc";
  2764. status = "disabled";
  2765. #address-cells = <0x00000001>;
  2766. #size-cells = <0x00000001>;
  2767. ranges = <0x00000000 0x0000c000 0x00001000>;
  2768. };
  2769. };
  2770. segment@20000 {
  2771. compatible = "simple-bus";
  2772. #address-cells = <0x00000001>;
  2773. #size-cells = <0x00000001>;
  2774. ranges = * 0x8300d570 [0x000000a8];
  2775. target-module@0 {
  2776. compatible = "ti,sysc-omap4-timer", "ti,sysc";
  2777. ti,hwmods = "timer12";
  2778. reg = <0x00000000 0x00000004 0x00000010 0x00000004>;
  2779. reg-names = "rev", "sysc";
  2780. ti,sysc-mask = <0x00000003>;
  2781. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  2782. clocks = <0x00000064 0x00000028 0x00000000>;
  2783. clock-names = "fck";
  2784. #address-cells = <0x00000001>;
  2785. #size-cells = <0x00000001>;
  2786. ranges = <0x00000000 0x00000000 0x00001000>;
  2787. timer@0 {
  2788. compatible = "ti,omap5430-timer";
  2789. reg = <0x00000000 0x00000080>;
  2790. clocks = <0x00000064 0x00000028 0x00000018>;
  2791. clock-names = "fck";
  2792. interrupts = <0x00000000 0x0000005a 0x00000004>;
  2793. ti,timer-alwon;
  2794. ti,timer-secure;
  2795. };
  2796. };
  2797. target-module@2000 {
  2798. compatible = "ti,sysc";
  2799. status = "disabled";
  2800. #address-cells = <0x00000001>;
  2801. #size-cells = <0x00000001>;
  2802. ranges = <0x00000000 0x00002000 0x00001000>;
  2803. };
  2804. target-module@6000 {
  2805. compatible = "ti,sysc";
  2806. status = "disabled";
  2807. #address-cells = <0x00000001>;
  2808. #size-cells = <0x00000001>;
  2809. ranges = * 0x8300d8b8 [0x00000048];
  2810. };
  2811. target-module@b000 {
  2812. compatible = "ti,sysc-omap2", "ti,sysc";
  2813. ti,hwmods = "uart10";
  2814. reg = <0x0000b050 0x00000004 0x0000b054 0x00000004 0x0000b058 0x00000004>;
  2815. reg-names = "rev", "sysc", "syss";
  2816. ti,sysc-mask = <0x00000007>;
  2817. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  2818. ti,syss-mask = <0x00000001>;
  2819. clocks = <0x00000064 0x00000060 0x00000000>;
  2820. clock-names = "fck";
  2821. #address-cells = <0x00000001>;
  2822. #size-cells = <0x00000001>;
  2823. ranges = <0x00000000 0x0000b000 0x00001000>;
  2824. serial@0 {
  2825. compatible = "ti,dra742-uart", "ti,omap4-uart";
  2826. reg = <0x00000000 0x00000100>;
  2827. interrupts = <0x00000000 0x000000dd 0x00000004>;
  2828. clock-frequency = <0x02dc6c00>;
  2829. status = "disabled";
  2830. };
  2831. };
  2832. target-module@f000 {
  2833. compatible = "ti,sysc";
  2834. status = "disabled";
  2835. #address-cells = <0x00000001>;
  2836. #size-cells = <0x00000001>;
  2837. ranges = <0x00000000 0x0000f000 0x00001000>;
  2838. };
  2839. };
  2840. segment@30000 {
  2841. compatible = "simple-bus";
  2842. #address-cells = <0x00000001>;
  2843. #size-cells = <0x00000001>;
  2844. ranges = * 0x8300dba4 [0x0000009c];
  2845. target-module@1000 {
  2846. compatible = "ti,sysc";
  2847. status = "disabled";
  2848. #address-cells = <0x00000001>;
  2849. #size-cells = <0x00000001>;
  2850. ranges = <0x00000000 0x00001000 0x00001000>;
  2851. };
  2852. target-module@3000 {
  2853. compatible = "ti,sysc";
  2854. status = "disabled";
  2855. #address-cells = <0x00000001>;
  2856. #size-cells = <0x00000001>;
  2857. ranges = <0x00000000 0x00003000 0x00001000>;
  2858. };
  2859. target-module@5000 {
  2860. compatible = "ti,sysc";
  2861. status = "disabled";
  2862. #address-cells = <0x00000001>;
  2863. #size-cells = <0x00000001>;
  2864. ranges = <0x00000000 0x00005000 0x00001000>;
  2865. };
  2866. target-module@7000 {
  2867. compatible = "ti,sysc";
  2868. status = "disabled";
  2869. #address-cells = <0x00000001>;
  2870. #size-cells = <0x00000001>;
  2871. ranges = <0x00000000 0x00007000 0x00001000>;
  2872. };
  2873. target-module@9000 {
  2874. compatible = "ti,sysc";
  2875. status = "disabled";
  2876. #address-cells = <0x00000001>;
  2877. #size-cells = <0x00000001>;
  2878. ranges = <0x00000000 0x00009000 0x00001000>;
  2879. };
  2880. target-module@c000 {
  2881. compatible = "ti,sysc-omap4", "ti,sysc";
  2882. reg = <0x0000c000 0x00000004>;
  2883. reg-names = "rev";
  2884. clocks = <0x00000064 0x00000068 0x00000000>;
  2885. clock-names = "fck";
  2886. #address-cells = <0x00000001>;
  2887. #size-cells = <0x00000001>;
  2888. ranges = <0x00000000 0x0000c000 0x00002000>;
  2889. can@0 {
  2890. compatible = "ti,dra7-d_can";
  2891. reg = <0x00000000 0x00002000>;
  2892. syscon-raminit = <0x00000009 0x00000558 0x00000000>;
  2893. interrupts = <0x00000000 0x000000de 0x00000004>;
  2894. clocks = <0x00000064 0x00000068 0x00000018>;
  2895. status = "disabled";
  2896. };
  2897. };
  2898. };
  2899. };
  2900. interconnect@48000000 {
  2901. compatible = "ti,dra7-l4-per1", "simple-bus";
  2902. reg = <0x48000000 0x00000800 0x48000800 0x00000800 0x48001000 0x00000400 0x48001400 0x00000400 0x48001800 0x00000400 0x48001c00 0x00000400>;
  2903. reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
  2904. #address-cells = <0x00000001>;
  2905. #size-cells = <0x00000001>;
  2906. ranges = <0x00000000 0x48000000 0x00200000 0x00200000 0x48200000 0x00200000>;
  2907. segment@0 {
  2908. compatible = "simple-bus";
  2909. #address-cells = <0x00000001>;
  2910. #size-cells = <0x00000001>;
  2911. ranges = * 0x8300e168 [0x000003fc];
  2912. target-module@20000 {
  2913. compatible = "ti,sysc-omap2", "ti,sysc";
  2914. ti,hwmods = "uart3";
  2915. reg = <0x00020050 0x00000004 0x00020054 0x00000004 0x00020058 0x00000004>;
  2916. reg-names = "rev", "sysc", "syss";
  2917. ti,sysc-mask = <0x00000007>;
  2918. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  2919. ti,syss-mask = <0x00000001>;
  2920. clocks = <0x00000090 0x00000128 0x00000000>;
  2921. clock-names = "fck";
  2922. #address-cells = <0x00000001>;
  2923. #size-cells = <0x00000001>;
  2924. ranges = <0x00000000 0x00020000 0x00001000>;
  2925. serial@0 {
  2926. compatible = "ti,dra742-uart", "ti,omap4-uart";
  2927. reg = <0x00000000 0x00000100>;
  2928. interrupts = <0x00000000 0x00000045 0x00000004>;
  2929. clock-frequency = <0x02dc6c00>;
  2930. status = "okay";
  2931. dmas = <0x00000091 0x00000035 0x00000091 0x00000036>;
  2932. dma-names = "tx", "rx";
  2933. interrupts-extended = <0x00000001 0x00000000 0x00000045 0x00000004 0x00000092 0x000003f8>;
  2934. };
  2935. };
  2936. target-module@32000 {
  2937. compatible = "ti,sysc-omap4-timer", "ti,sysc";
  2938. ti,hwmods = "timer2";
  2939. reg = <0x00032000 0x00000004 0x00032010 0x00000004>;
  2940. reg-names = "rev", "sysc";
  2941. ti,sysc-mask = <0x00000003>;
  2942. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  2943. clocks = <0x00000090 0x00000010 0x00000000>;
  2944. clock-names = "fck";
  2945. #address-cells = <0x00000001>;
  2946. #size-cells = <0x00000001>;
  2947. ranges = <0x00000000 0x00032000 0x00001000>;
  2948. timer@0 {
  2949. compatible = "ti,omap5430-timer";
  2950. reg = <0x00000000 0x00000080>;
  2951. clocks = <0x00000090 0x00000010 0x00000018>;
  2952. clock-names = "fck";
  2953. interrupts = <0x00000000 0x00000021 0x00000004>;
  2954. };
  2955. };
  2956. target-module@34000 {
  2957. compatible = "ti,sysc-omap4-timer", "ti,sysc";
  2958. ti,hwmods = "timer3";
  2959. reg = <0x00034000 0x00000004 0x00034010 0x00000004>;
  2960. reg-names = "rev", "sysc";
  2961. ti,sysc-mask = <0x00000003>;
  2962. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  2963. clocks = <0x00000090 0x00000018 0x00000000>;
  2964. clock-names = "fck";
  2965. #address-cells = <0x00000001>;
  2966. #size-cells = <0x00000001>;
  2967. ranges = <0x00000000 0x00034000 0x00001000>;
  2968. timer@0 {
  2969. compatible = "ti,omap5430-timer";
  2970. reg = <0x00000000 0x00000080>;
  2971. clocks = <0x00000090 0x00000018 0x00000018>;
  2972. clock-names = "fck";
  2973. interrupts = <0x00000000 0x00000022 0x00000004>;
  2974. };
  2975. };
  2976. target-module@36000 {
  2977. compatible = "ti,sysc-omap4-timer", "ti,sysc";
  2978. ti,hwmods = "timer4";
  2979. reg = <0x00036000 0x00000004 0x00036010 0x00000004>;
  2980. reg-names = "rev", "sysc";
  2981. ti,sysc-mask = <0x00000003>;
  2982. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  2983. clocks = <0x00000090 0x00000020 0x00000000>;
  2984. clock-names = "fck";
  2985. #address-cells = <0x00000001>;
  2986. #size-cells = <0x00000001>;
  2987. ranges = <0x00000000 0x00036000 0x00001000>;
  2988. timer@0 {
  2989. compatible = "ti,omap5430-timer";
  2990. reg = <0x00000000 0x00000080>;
  2991. clocks = <0x00000090 0x00000020 0x00000018>;
  2992. clock-names = "fck";
  2993. interrupts = <0x00000000 0x00000023 0x00000004>;
  2994. };
  2995. };
  2996. target-module@3e000 {
  2997. compatible = "ti,sysc-omap4-timer", "ti,sysc";
  2998. ti,hwmods = "timer9";
  2999. reg = <0x0003e000 0x00000004 0x0003e010 0x00000004>;
  3000. reg-names = "rev", "sysc";
  3001. ti,sysc-mask = <0x00000003>;
  3002. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3003. clocks = <0x00000090 0x00000028 0x00000000>;
  3004. clock-names = "fck";
  3005. #address-cells = <0x00000001>;
  3006. #size-cells = <0x00000001>;
  3007. ranges = <0x00000000 0x0003e000 0x00001000>;
  3008. timer@0 {
  3009. compatible = "ti,omap5430-timer";
  3010. reg = <0x00000000 0x00000080>;
  3011. clocks = <0x00000090 0x00000028 0x00000018>;
  3012. clock-names = "fck";
  3013. interrupts = <0x00000000 0x00000028 0x00000004>;
  3014. };
  3015. };
  3016. target-module@51000 {
  3017. compatible = "ti,sysc-omap2", "ti,sysc";
  3018. ti,hwmods = "gpio7";
  3019. reg = <0x00051000 0x00000004 0x00051010 0x00000004 0x00051114 0x00000004>;
  3020. reg-names = "rev", "sysc", "syss";
  3021. ti,sysc-mask = <0x00000007>;
  3022. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3023. ti,syss-mask = <0x00000001>;
  3024. clocks = <0x00000090 0x000000e8 0x00000000 0x00000090 0x000000e8 0x00000008>;
  3025. clock-names = "fck", "dbclk";
  3026. #address-cells = <0x00000001>;
  3027. #size-cells = <0x00000001>;
  3028. ranges = <0x00000000 0x00051000 0x00001000>;
  3029. gpio@0 {
  3030. compatible = "ti,omap4-gpio";
  3031. reg = <0x00000000 0x00000200>;
  3032. interrupts = <0x00000000 0x0000001e 0x00000004>;
  3033. gpio-controller;
  3034. #gpio-cells = <0x00000002>;
  3035. interrupt-controller;
  3036. #interrupt-cells = <0x00000002>;
  3037. ti,no-reset-on-init;
  3038. ti,no-idle-on-init;
  3039. phandle = <0x00000098>;
  3040. };
  3041. };
  3042. target-module@53000 {
  3043. compatible = "ti,sysc-omap2", "ti,sysc";
  3044. ti,hwmods = "gpio8";
  3045. reg = <0x00053000 0x00000004 0x00053010 0x00000004 0x00053114 0x00000004>;
  3046. reg-names = "rev", "sysc", "syss";
  3047. ti,sysc-mask = <0x00000007>;
  3048. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3049. ti,syss-mask = <0x00000001>;
  3050. clocks = <0x00000090 0x000000f0 0x00000000 0x00000090 0x000000f0 0x00000008>;
  3051. clock-names = "fck", "dbclk";
  3052. #address-cells = <0x00000001>;
  3053. #size-cells = <0x00000001>;
  3054. ranges = <0x00000000 0x00053000 0x00001000>;
  3055. gpio@0 {
  3056. compatible = "ti,omap4-gpio";
  3057. reg = <0x00000000 0x00000200>;
  3058. interrupts = <0x00000000 0x00000074 0x00000004>;
  3059. gpio-controller;
  3060. #gpio-cells = <0x00000002>;
  3061. interrupt-controller;
  3062. #interrupt-cells = <0x00000002>;
  3063. };
  3064. };
  3065. target-module@55000 {
  3066. compatible = "ti,sysc-omap2", "ti,sysc";
  3067. ti,hwmods = "gpio2";
  3068. reg = <0x00055000 0x00000004 0x00055010 0x00000004 0x00055114 0x00000004>;
  3069. reg-names = "rev", "sysc", "syss";
  3070. ti,sysc-mask = <0x00000007>;
  3071. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3072. ti,syss-mask = <0x00000001>;
  3073. clocks = <0x00000090 0x00000038 0x00000000 0x00000090 0x00000038 0x00000008>;
  3074. clock-names = "fck", "dbclk";
  3075. #address-cells = <0x00000001>;
  3076. #size-cells = <0x00000001>;
  3077. ranges = <0x00000000 0x00055000 0x00001000>;
  3078. gpio@0 {
  3079. compatible = "ti,omap4-gpio";
  3080. reg = <0x00000000 0x00000200>;
  3081. interrupts = <0x00000000 0x00000019 0x00000004>;
  3082. gpio-controller;
  3083. #gpio-cells = <0x00000002>;
  3084. interrupt-controller;
  3085. #interrupt-cells = <0x00000002>;
  3086. phandle = <0x000000c0>;
  3087. };
  3088. };
  3089. target-module@57000 {
  3090. compatible = "ti,sysc-omap2", "ti,sysc";
  3091. ti,hwmods = "gpio3";
  3092. reg = <0x00057000 0x00000004 0x00057010 0x00000004 0x00057114 0x00000004>;
  3093. reg-names = "rev", "sysc", "syss";
  3094. ti,sysc-mask = <0x00000007>;
  3095. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3096. ti,syss-mask = <0x00000001>;
  3097. clocks = <0x00000090 0x00000040 0x00000000 0x00000090 0x00000040 0x00000008>;
  3098. clock-names = "fck", "dbclk";
  3099. #address-cells = <0x00000001>;
  3100. #size-cells = <0x00000001>;
  3101. ranges = <0x00000000 0x00057000 0x00001000>;
  3102. gpio@0 {
  3103. compatible = "ti,omap4-gpio";
  3104. reg = <0x00000000 0x00000200>;
  3105. interrupts = <0x00000000 0x0000001a 0x00000004>;
  3106. gpio-controller;
  3107. #gpio-cells = <0x00000002>;
  3108. interrupt-controller;
  3109. #interrupt-cells = <0x00000002>;
  3110. };
  3111. };
  3112. target-module@59000 {
  3113. compatible = "ti,sysc-omap2", "ti,sysc";
  3114. ti,hwmods = "gpio4";
  3115. reg = <0x00059000 0x00000004 0x00059010 0x00000004 0x00059114 0x00000004>;
  3116. reg-names = "rev", "sysc", "syss";
  3117. ti,sysc-mask = <0x00000007>;
  3118. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3119. ti,syss-mask = <0x00000001>;
  3120. clocks = <0x00000090 0x00000048 0x00000000 0x00000090 0x00000048 0x00000008>;
  3121. clock-names = "fck", "dbclk";
  3122. #address-cells = <0x00000001>;
  3123. #size-cells = <0x00000001>;
  3124. ranges = <0x00000000 0x00059000 0x00001000>;
  3125. gpio@0 {
  3126. compatible = "ti,omap4-gpio";
  3127. reg = <0x00000000 0x00000200>;
  3128. interrupts = <0x00000000 0x0000001b 0x00000004>;
  3129. gpio-controller;
  3130. #gpio-cells = <0x00000002>;
  3131. interrupt-controller;
  3132. #interrupt-cells = <0x00000002>;
  3133. phandle = <0x00000097>;
  3134. };
  3135. };
  3136. target-module@5b000 {
  3137. compatible = "ti,sysc-omap2", "ti,sysc";
  3138. ti,hwmods = "gpio5";
  3139. reg = <0x0005b000 0x00000004 0x0005b010 0x00000004 0x0005b114 0x00000004>;
  3140. reg-names = "rev", "sysc", "syss";
  3141. ti,sysc-mask = <0x00000007>;
  3142. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3143. ti,syss-mask = <0x00000001>;
  3144. clocks = <0x00000090 0x00000050 0x00000000 0x00000090 0x00000050 0x00000008>;
  3145. clock-names = "fck", "dbclk";
  3146. #address-cells = <0x00000001>;
  3147. #size-cells = <0x00000001>;
  3148. ranges = <0x00000000 0x0005b000 0x00001000>;
  3149. gpio@0 {
  3150. compatible = "ti,omap4-gpio";
  3151. reg = <0x00000000 0x00000200>;
  3152. interrupts = <0x00000000 0x0000001c 0x00000004>;
  3153. gpio-controller;
  3154. #gpio-cells = <0x00000002>;
  3155. interrupt-controller;
  3156. #interrupt-cells = <0x00000002>;
  3157. };
  3158. };
  3159. target-module@5d000 {
  3160. compatible = "ti,sysc-omap2", "ti,sysc";
  3161. ti,hwmods = "gpio6";
  3162. reg = <0x0005d000 0x00000004 0x0005d010 0x00000004 0x0005d114 0x00000004>;
  3163. reg-names = "rev", "sysc", "syss";
  3164. ti,sysc-mask = <0x00000007>;
  3165. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3166. ti,syss-mask = <0x00000001>;
  3167. clocks = <0x00000090 0x00000058 0x00000000 0x00000090 0x00000058 0x00000008>;
  3168. clock-names = "fck", "dbclk";
  3169. #address-cells = <0x00000001>;
  3170. #size-cells = <0x00000001>;
  3171. ranges = <0x00000000 0x0005d000 0x00001000>;
  3172. gpio@0 {
  3173. compatible = "ti,omap4-gpio";
  3174. reg = <0x00000000 0x00000200>;
  3175. interrupts = <0x00000000 0x0000001d 0x00000004>;
  3176. gpio-controller;
  3177. #gpio-cells = <0x00000002>;
  3178. interrupt-controller;
  3179. #interrupt-cells = <0x00000002>;
  3180. phandle = <0x0000009d>;
  3181. };
  3182. };
  3183. target-module@60000 {
  3184. compatible = "ti,sysc-omap2", "ti,sysc";
  3185. ti,hwmods = "i2c3";
  3186. reg = <0x00060000 0x00000008 0x00060010 0x00000008 0x00060090 0x00000008>;
  3187. reg-names = "rev", "sysc", "syss";
  3188. ti,sysc-mask = <0x00000307>;
  3189. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3190. ti,syss-mask = <0x00000001>;
  3191. clocks = <0x00000090 0x00000088 0x00000000>;
  3192. clock-names = "fck";
  3193. #address-cells = <0x00000001>;
  3194. #size-cells = <0x00000001>;
  3195. ranges = <0x00000000 0x00060000 0x00001000>;
  3196. i2c@0 {
  3197. compatible = "ti,omap4-i2c";
  3198. reg = <0x00000000 0x00000100>;
  3199. interrupts = <0x00000000 0x00000038 0x00000004>;
  3200. #address-cells = <0x00000001>;
  3201. #size-cells = <0x00000000>;
  3202. status = "okay";
  3203. clock-frequency = <0x00061a80>;
  3204. rtc@6f {
  3205. compatible = "microchip,mcp7941x";
  3206. reg = <0x0000006f>;
  3207. interrupts-extended = <0x00000001 0x00000000 0x00000002 0x00000001 0x00000092 0x00000424>;
  3208. interrupt-names = "irq", "wakeup";
  3209. vcc-supply = <0x00000093>;
  3210. wakeup-source;
  3211. };
  3212. };
  3213. };
  3214. target-module@66000 {
  3215. compatible = "ti,sysc-omap2", "ti,sysc";
  3216. ti,hwmods = "uart5";
  3217. reg = <0x00066050 0x00000004 0x00066054 0x00000004 0x00066058 0x00000004>;
  3218. reg-names = "rev", "sysc", "syss";
  3219. ti,sysc-mask = <0x00000007>;
  3220. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3221. ti,syss-mask = <0x00000001>;
  3222. clocks = <0x00000090 0x00000148 0x00000000>;
  3223. clock-names = "fck";
  3224. #address-cells = <0x00000001>;
  3225. #size-cells = <0x00000001>;
  3226. ranges = <0x00000000 0x00066000 0x00001000>;
  3227. serial@0 {
  3228. compatible = "ti,dra742-uart", "ti,omap4-uart";
  3229. reg = <0x00000000 0x00000100>;
  3230. interrupts = <0x00000000 0x00000064 0x00000004>;
  3231. clock-frequency = <0x02dc6c00>;
  3232. status = "disabled";
  3233. dmas = <0x00000091 0x0000003f 0x00000091 0x00000040>;
  3234. dma-names = "tx", "rx";
  3235. };
  3236. };
  3237. target-module@68000 {
  3238. compatible = "ti,sysc-omap2", "ti,sysc";
  3239. ti,hwmods = "uart6";
  3240. reg = <0x00068050 0x00000004 0x00068054 0x00000004 0x00068058 0x00000004>;
  3241. reg-names = "rev", "sysc", "syss";
  3242. ti,sysc-mask = <0x00000007>;
  3243. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3244. ti,syss-mask = <0x00000001>;
  3245. clocks = <0x00000094 0x00000030 0x00000000>;
  3246. clock-names = "fck";
  3247. #address-cells = <0x00000001>;
  3248. #size-cells = <0x00000001>;
  3249. ranges = <0x00000000 0x00068000 0x00001000>;
  3250. serial@0 {
  3251. compatible = "ti,dra742-uart", "ti,omap4-uart";
  3252. reg = <0x00000000 0x00000100>;
  3253. interrupts = <0x00000000 0x00000065 0x00000004>;
  3254. clock-frequency = <0x02dc6c00>;
  3255. status = "disabled";
  3256. dmas = <0x00000091 0x0000004f 0x00000091 0x00000050>;
  3257. dma-names = "tx", "rx";
  3258. };
  3259. };
  3260. target-module@6a000 {
  3261. compatible = "ti,sysc-omap2", "ti,sysc";
  3262. ti,hwmods = "uart1";
  3263. reg = <0x0006a050 0x00000004 0x0006a054 0x00000004 0x0006a058 0x00000004>;
  3264. reg-names = "rev", "sysc", "syss";
  3265. ti,sysc-mask = <0x00000007>;
  3266. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3267. ti,syss-mask = <0x00000001>;
  3268. clocks = <0x00000090 0x00000118 0x00000000>;
  3269. clock-names = "fck";
  3270. #address-cells = <0x00000001>;
  3271. #size-cells = <0x00000001>;
  3272. ranges = <0x00000000 0x0006a000 0x00001000>;
  3273. serial@0 {
  3274. compatible = "ti,dra742-uart", "ti,omap4-uart";
  3275. reg = <0x00000000 0x00000100>;
  3276. interrupts-extended = <0x00000001 0x00000000 0x00000043 0x00000004>;
  3277. clock-frequency = <0x02dc6c00>;
  3278. status = "disabled";
  3279. dmas = <0x00000091 0x00000031 0x00000091 0x00000032>;
  3280. dma-names = "tx", "rx";
  3281. };
  3282. };
  3283. target-module@6c000 {
  3284. compatible = "ti,sysc-omap2", "ti,sysc";
  3285. ti,hwmods = "uart2";
  3286. reg = <0x0006c050 0x00000004 0x0006c054 0x00000004 0x0006c058 0x00000004>;
  3287. reg-names = "rev", "sysc", "syss";
  3288. ti,sysc-mask = <0x00000007>;
  3289. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3290. ti,syss-mask = <0x00000001>;
  3291. clocks = <0x00000090 0x00000120 0x00000000>;
  3292. clock-names = "fck";
  3293. #address-cells = <0x00000001>;
  3294. #size-cells = <0x00000001>;
  3295. ranges = <0x00000000 0x0006c000 0x00001000>;
  3296. serial@0 {
  3297. compatible = "ti,dra742-uart", "ti,omap4-uart";
  3298. reg = <0x00000000 0x00000100>;
  3299. interrupts = <0x00000000 0x00000044 0x00000004>;
  3300. clock-frequency = <0x02dc6c00>;
  3301. status = "disabled";
  3302. dmas = <0x00000091 0x00000033 0x00000091 0x00000034>;
  3303. dma-names = "tx", "rx";
  3304. };
  3305. };
  3306. target-module@6e000 {
  3307. compatible = "ti,sysc-omap2", "ti,sysc";
  3308. ti,hwmods = "uart4";
  3309. reg = <0x0006e050 0x00000004 0x0006e054 0x00000004 0x0006e058 0x00000004>;
  3310. reg-names = "rev", "sysc", "syss";
  3311. ti,sysc-mask = <0x00000007>;
  3312. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3313. ti,syss-mask = <0x00000001>;
  3314. clocks = <0x00000090 0x00000130 0x00000000>;
  3315. clock-names = "fck";
  3316. #address-cells = <0x00000001>;
  3317. #size-cells = <0x00000001>;
  3318. ranges = <0x00000000 0x0006e000 0x00001000>;
  3319. serial@0 {
  3320. compatible = "ti,dra742-uart", "ti,omap4-uart";
  3321. reg = <0x00000000 0x00000100>;
  3322. interrupts = <0x00000000 0x00000041 0x00000004>;
  3323. clock-frequency = <0x02dc6c00>;
  3324. status = "disabled";
  3325. dmas = <0x00000091 0x00000037 0x00000091 0x00000038>;
  3326. dma-names = "tx", "rx";
  3327. };
  3328. };
  3329. target-module@70000 {
  3330. compatible = "ti,sysc-omap2", "ti,sysc";
  3331. ti,hwmods = "i2c1";
  3332. reg = <0x00070000 0x00000008 0x00070010 0x00000008 0x00070090 0x00000008>;
  3333. reg-names = "rev", "sysc", "syss";
  3334. ti,sysc-mask = <0x00000307>;
  3335. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3336. ti,syss-mask = <0x00000001>;
  3337. clocks = <0x00000090 0x00000078 0x00000000>;
  3338. clock-names = "fck";
  3339. #address-cells = <0x00000001>;
  3340. #size-cells = <0x00000001>;
  3341. ranges = <0x00000000 0x00070000 0x00001000>;
  3342. i2c@0 {
  3343. compatible = "ti,omap4-i2c";
  3344. reg = <0x00000000 0x00000100>;
  3345. interrupts = <0x00000000 0x00000033 0x00000004>;
  3346. #address-cells = <0x00000001>;
  3347. #size-cells = <0x00000000>;
  3348. status = "okay";
  3349. clock-frequency = <0x00061a80>;
  3350. tps659038@58 {
  3351. compatible = "ti,tps659038";
  3352. reg = <0x00000058>;
  3353. interrupt-parent = <0x00000095>;
  3354. interrupts = <0x00000000 0x00000008>;
  3355. #interrupt-cells = <0x00000002>;
  3356. interrupt-controller;
  3357. ti,system-power-controller;
  3358. ti,palmas-override-powerhold;
  3359. phandle = <0x00000096>;
  3360. tps659038_pmic {
  3361. compatible = "ti,tps659038-pmic";
  3362. regulators {
  3363. smps12 {
  3364. regulator-name = "smps12";
  3365. regulator-min-microvolt = <0x000cf850>;
  3366. regulator-max-microvolt = <0x001312d0>;
  3367. regulator-always-on;
  3368. regulator-boot-on;
  3369. phandle = <0x00000006>;
  3370. };
  3371. smps3 {
  3372. regulator-name = "smps3";
  3373. regulator-min-microvolt = <0x00149970>;
  3374. regulator-max-microvolt = <0x00149970>;
  3375. regulator-always-on;
  3376. regulator-boot-on;
  3377. phandle = <0x000000d4>;
  3378. };
  3379. smps45 {
  3380. regulator-name = "smps45";
  3381. regulator-min-microvolt = <0x000cf850>;
  3382. regulator-max-microvolt = <0x001312d0>;
  3383. regulator-always-on;
  3384. regulator-boot-on;
  3385. };
  3386. smps6 {
  3387. regulator-name = "smps6";
  3388. regulator-min-microvolt = <0x000cf850>;
  3389. regulator-max-microvolt = <0x00118c30>;
  3390. regulator-always-on;
  3391. regulator-boot-on;
  3392. };
  3393. smps8 {
  3394. regulator-name = "smps8";
  3395. regulator-min-microvolt = <0x001b7740>;
  3396. regulator-max-microvolt = <0x001b7740>;
  3397. regulator-always-on;
  3398. regulator-boot-on;
  3399. };
  3400. ldo1 {
  3401. regulator-name = "ldo1";
  3402. regulator-min-microvolt = <0x001b7740>;
  3403. regulator-max-microvolt = <0x00325aa0>;
  3404. regulator-boot-on;
  3405. regulator-always-on;
  3406. phandle = <0x000000a6>;
  3407. };
  3408. ldo2 {
  3409. regulator-name = "ldo2";
  3410. regulator-min-microvolt = <0x00325aa0>;
  3411. regulator-max-microvolt = <0x00325aa0>;
  3412. regulator-always-on;
  3413. regulator-boot-on;
  3414. };
  3415. ldo3 {
  3416. regulator-name = "ldo3";
  3417. regulator-min-microvolt = <0x001b7740>;
  3418. regulator-max-microvolt = <0x001b7740>;
  3419. regulator-always-on;
  3420. regulator-boot-on;
  3421. };
  3422. ldo4 {
  3423. regulator-name = "ldo4";
  3424. regulator-min-microvolt = <0x001b7740>;
  3425. regulator-max-microvolt = <0x001b7740>;
  3426. regulator-always-on;
  3427. regulator-boot-on;
  3428. phandle = <0x000000c9>;
  3429. };
  3430. ldo9 {
  3431. regulator-name = "ldo9";
  3432. regulator-min-microvolt = <0x00100590>;
  3433. regulator-max-microvolt = <0x00100590>;
  3434. regulator-always-on;
  3435. regulator-boot-on;
  3436. };
  3437. ldoln {
  3438. regulator-name = "ldoln";
  3439. regulator-min-microvolt = <0x001b7740>;
  3440. regulator-max-microvolt = <0x001b7740>;
  3441. regulator-always-on;
  3442. regulator-boot-on;
  3443. phandle = <0x000000c8>;
  3444. };
  3445. ldousb {
  3446. regulator-name = "ldousb";
  3447. regulator-min-microvolt = <0x00325aa0>;
  3448. regulator-max-microvolt = <0x00325aa0>;
  3449. regulator-boot-on;
  3450. phandle = <0x0000005c>;
  3451. };
  3452. regen1 {
  3453. regulator-name = "regen1";
  3454. regulator-boot-on;
  3455. regulator-always-on;
  3456. phandle = <0x000000d3>;
  3457. };
  3458. };
  3459. };
  3460. tps659038_rtc {
  3461. compatible = "ti,palmas-rtc";
  3462. interrupt-parent = <0x00000096>;
  3463. interrupts = <0x00000008 0x00000002>;
  3464. wakeup-source;
  3465. };
  3466. tps659038_pwr_button {
  3467. compatible = "ti,palmas-pwrbutton";
  3468. interrupt-parent = <0x00000096>;
  3469. interrupts = <0x00000001 0x00000002>;
  3470. wakeup-source;
  3471. ti,palmas-long-press-seconds = <0x0000000c>;
  3472. };
  3473. tps659038_gpio {
  3474. compatible = "ti,palmas-gpio";
  3475. gpio-controller;
  3476. #gpio-cells = <0x00000002>;
  3477. phandle = <0x000000d5>;
  3478. };
  3479. tps659038_usb {
  3480. compatible = "ti,palmas-usb-vid";
  3481. ti,enable-vbus-detection;
  3482. vbus-gpio = <0x00000097 0x00000015 0x00000000>;
  3483. phandle = <0x000000bb>;
  3484. };
  3485. };
  3486. tmp102@48 {
  3487. compatible = "ti,tmp102";
  3488. reg = <0x00000048>;
  3489. interrupt-parent = <0x00000098>;
  3490. interrupts = <0x00000010 0x00000008>;
  3491. #thermal-sensor-cells = <0x00000001>;
  3492. phandle = <0x000000d1>;
  3493. };
  3494. tlv320aic3104@18 {
  3495. #sound-dai-cells = <0x00000000>;
  3496. compatible = "ti,tlv320aic3104";
  3497. reg = <0x00000018>;
  3498. assigned-clocks = <0x0000004e>;
  3499. assigned-clock-parents = <0x00000079>;
  3500. status = "okay";
  3501. adc-settle-ms = <0x00000028>;
  3502. AVDD-supply = <0x00000093>;
  3503. IOVDD-supply = <0x00000093>;
  3504. DRVDD-supply = <0x00000093>;
  3505. DVDD-supply = <0x00000099>;
  3506. phandle = <0x000000db>;
  3507. };
  3508. eeprom@50 {
  3509. compatible = "atmel,24c32";
  3510. reg = <0x00000050>;
  3511. };
  3512. };
  3513. };
  3514. target-module@72000 {
  3515. compatible = "ti,sysc-omap2", "ti,sysc";
  3516. ti,hwmods = "i2c2";
  3517. reg = <0x00072000 0x00000008 0x00072010 0x00000008 0x00072090 0x00000008>;
  3518. reg-names = "rev", "sysc", "syss";
  3519. ti,sysc-mask = <0x00000307>;
  3520. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3521. ti,syss-mask = <0x00000001>;
  3522. clocks = <0x00000090 0x00000080 0x00000000>;
  3523. clock-names = "fck";
  3524. #address-cells = <0x00000001>;
  3525. #size-cells = <0x00000001>;
  3526. ranges = <0x00000000 0x00072000 0x00001000>;
  3527. i2c@0 {
  3528. compatible = "ti,omap4-i2c";
  3529. reg = <0x00000000 0x00000100>;
  3530. interrupts = <0x00000000 0x00000034 0x00000004>;
  3531. #address-cells = <0x00000001>;
  3532. #size-cells = <0x00000000>;
  3533. status = "disabled";
  3534. };
  3535. };
  3536. target-module@78000 {
  3537. compatible = "ti,sysc-omap2", "ti,sysc";
  3538. ti,hwmods = "elm";
  3539. reg = <0x00078000 0x00000004 0x00078010 0x00000004 0x00078014 0x00000004>;
  3540. reg-names = "rev", "sysc", "syss";
  3541. ti,sysc-mask = <0x00000303>;
  3542. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3543. ti,syss-mask = <0x00000001>;
  3544. clocks = <0x00000090 0x00000030 0x00000000>;
  3545. clock-names = "fck";
  3546. #address-cells = <0x00000001>;
  3547. #size-cells = <0x00000001>;
  3548. ranges = <0x00000000 0x00078000 0x00001000>;
  3549. elm@0 {
  3550. compatible = "ti,am3352-elm";
  3551. reg = <0x00000000 0x00000fc0>;
  3552. interrupts = <0x00000000 0x00000001 0x00000004>;
  3553. status = "disabled";
  3554. };
  3555. };
  3556. target-module@7a000 {
  3557. compatible = "ti,sysc-omap2", "ti,sysc";
  3558. ti,hwmods = "i2c4";
  3559. reg = <0x0007a000 0x00000008 0x0007a010 0x00000008 0x0007a090 0x00000008>;
  3560. reg-names = "rev", "sysc", "syss";
  3561. ti,sysc-mask = <0x00000307>;
  3562. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3563. ti,syss-mask = <0x00000001>;
  3564. clocks = <0x00000090 0x00000090 0x00000000>;
  3565. clock-names = "fck";
  3566. #address-cells = <0x00000001>;
  3567. #size-cells = <0x00000001>;
  3568. ranges = <0x00000000 0x0007a000 0x00001000>;
  3569. i2c@0 {
  3570. compatible = "ti,omap4-i2c";
  3571. reg = <0x00000000 0x00000100>;
  3572. interrupts = <0x00000000 0x00000039 0x00000004>;
  3573. #address-cells = <0x00000001>;
  3574. #size-cells = <0x00000000>;
  3575. status = "disabled";
  3576. };
  3577. };
  3578. target-module@7c000 {
  3579. compatible = "ti,sysc-omap2", "ti,sysc";
  3580. ti,hwmods = "i2c5";
  3581. reg = <0x0007c000 0x00000008 0x0007c010 0x00000008 0x0007c090 0x00000008>;
  3582. reg-names = "rev", "sysc", "syss";
  3583. ti,sysc-mask = <0x00000307>;
  3584. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3585. ti,syss-mask = <0x00000001>;
  3586. clocks = <0x00000094 0x00000028 0x00000000>;
  3587. clock-names = "fck";
  3588. #address-cells = <0x00000001>;
  3589. #size-cells = <0x00000001>;
  3590. ranges = <0x00000000 0x0007c000 0x00001000>;
  3591. i2c@0 {
  3592. compatible = "ti,omap4-i2c";
  3593. reg = <0x00000000 0x00000100>;
  3594. interrupts = <0x00000000 0x00000037 0x00000004>;
  3595. #address-cells = <0x00000001>;
  3596. #size-cells = <0x00000000>;
  3597. status = "disabled";
  3598. };
  3599. };
  3600. target-module@86000 {
  3601. compatible = "ti,sysc-omap4-timer", "ti,sysc";
  3602. ti,hwmods = "timer10";
  3603. reg = <0x00086000 0x00000004 0x00086010 0x00000004>;
  3604. reg-names = "rev", "sysc";
  3605. ti,sysc-mask = <0x00000003>;
  3606. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3607. clocks = <0x00000090 0x00000000 0x00000000>;
  3608. clock-names = "fck";
  3609. #address-cells = <0x00000001>;
  3610. #size-cells = <0x00000001>;
  3611. ranges = <0x00000000 0x00086000 0x00001000>;
  3612. timer@0 {
  3613. compatible = "ti,omap5430-timer";
  3614. reg = <0x00000000 0x00000080>;
  3615. clocks = <0x00000090 0x00000000 0x00000018>;
  3616. clock-names = "fck";
  3617. interrupts = <0x00000000 0x00000029 0x00000004>;
  3618. };
  3619. };
  3620. target-module@88000 {
  3621. compatible = "ti,sysc-omap4-timer", "ti,sysc";
  3622. ti,hwmods = "timer11";
  3623. reg = <0x00088000 0x00000004 0x00088010 0x00000004>;
  3624. reg-names = "rev", "sysc";
  3625. ti,sysc-mask = <0x00000003>;
  3626. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3627. clocks = <0x00000090 0x00000008 0x00000000>;
  3628. clock-names = "fck";
  3629. #address-cells = <0x00000001>;
  3630. #size-cells = <0x00000001>;
  3631. ranges = <0x00000000 0x00088000 0x00001000>;
  3632. timer@0 {
  3633. compatible = "ti,omap5430-timer";
  3634. reg = <0x00000000 0x00000080>;
  3635. clocks = <0x00000090 0x00000008 0x00000018>;
  3636. clock-names = "fck";
  3637. interrupts = <0x00000000 0x0000002a 0x00000004>;
  3638. };
  3639. };
  3640. target-module@90000 {
  3641. compatible = "ti,sysc-omap2", "ti,sysc";
  3642. ti,hwmods = "rng";
  3643. reg = <0x00091fe0 0x00000004 0x00091fe4 0x00000004>;
  3644. reg-names = "rev", "sysc";
  3645. ti,sysc-mask = <0x00000001>;
  3646. ti,sysc-sidle = <0x00000000 0x00000001>;
  3647. clocks = <0x0000009a 0x00000020 0x00000000>;
  3648. clock-names = "fck";
  3649. #address-cells = <0x00000001>;
  3650. #size-cells = <0x00000001>;
  3651. ranges = <0x00000000 0x00090000 0x00002000>;
  3652. rng@0 {
  3653. compatible = "ti,omap4-rng";
  3654. reg = <0x00000000 0x00002000>;
  3655. interrupts = <0x00000000 0x0000002f 0x00000004>;
  3656. clocks = <0x0000000a>;
  3657. clock-names = "fck";
  3658. };
  3659. };
  3660. target-module@98000 {
  3661. compatible = "ti,sysc-omap4", "ti,sysc";
  3662. ti,hwmods = "mcspi1";
  3663. reg = <0x00098000 0x00000004 0x00098010 0x00000004>;
  3664. reg-names = "rev", "sysc";
  3665. ti,sysc-mask = <0x00000003>;
  3666. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3667. clocks = <0x00000090 0x000000c8 0x00000000>;
  3668. clock-names = "fck";
  3669. #address-cells = <0x00000001>;
  3670. #size-cells = <0x00000001>;
  3671. ranges = <0x00000000 0x00098000 0x00001000>;
  3672. spi@0 {
  3673. compatible = "ti,omap4-mcspi";
  3674. reg = <0x00000000 0x00000200>;
  3675. interrupts = <0x00000000 0x0000003c 0x00000004>;
  3676. #address-cells = <0x00000001>;
  3677. #size-cells = <0x00000000>;
  3678. ti,spi-num-cs = <0x00000004>;
  3679. dmas = <0x00000091 0x00000023 0x00000091 0x00000024 0x00000091 0x00000025 0x00000091 0x00000026 0x00000091 0x00000027 0x00000091 0x00000028 0x00000091 0x00000029 0x00000091 0x0000002a>;
  3680. dma-names = "tx0", "rx0", "tx1", "rx1", "tx2", "rx2", "tx3", "rx3";
  3681. status = "disabled";
  3682. };
  3683. };
  3684. target-module@9a000 {
  3685. compatible = "ti,sysc-omap4", "ti,sysc";
  3686. ti,hwmods = "mcspi2";
  3687. reg = <0x0009a000 0x00000004 0x0009a010 0x00000004>;
  3688. reg-names = "rev", "sysc";
  3689. ti,sysc-mask = <0x00000003>;
  3690. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3691. clocks = <0x00000090 0x000000d0 0x00000000>;
  3692. clock-names = "fck";
  3693. #address-cells = <0x00000001>;
  3694. #size-cells = <0x00000001>;
  3695. ranges = <0x00000000 0x0009a000 0x00001000>;
  3696. spi@0 {
  3697. compatible = "ti,omap4-mcspi";
  3698. reg = <0x00000000 0x00000200>;
  3699. interrupts = <0x00000000 0x0000003d 0x00000004>;
  3700. #address-cells = <0x00000001>;
  3701. #size-cells = <0x00000000>;
  3702. ti,spi-num-cs = <0x00000002>;
  3703. dmas = <0x00000091 0x0000002b 0x00000091 0x0000002c 0x00000091 0x0000002d 0x00000091 0x0000002e>;
  3704. dma-names = "tx0", "rx0", "tx1", "rx1";
  3705. status = "disabled";
  3706. };
  3707. };
  3708. target-module@9c000 {
  3709. compatible = "ti,sysc-omap4", "ti,sysc";
  3710. ti,hwmods = "mmc1";
  3711. reg = <0x0009c000 0x00000004 0x0009c010 0x00000004>;
  3712. reg-names = "rev", "sysc";
  3713. ti,sysc-mask = <0x00000003>;
  3714. ti,sysc-midle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3715. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3716. clocks = <0x0000005a 0x00000008 0x00000000>;
  3717. clock-names = "fck";
  3718. #address-cells = <0x00000001>;
  3719. #size-cells = <0x00000001>;
  3720. ranges = <0x00000000 0x0009c000 0x00001000>;
  3721. mmc@0 {
  3722. compatible = "ti,dra7-sdhci";
  3723. reg = <0x00000000 0x00000400>;
  3724. interrupts = <0x00000000 0x0000004e 0x00000004>;
  3725. status = "okay";
  3726. pbias-supply = <0x0000009b>;
  3727. max-frequency = "qḞ";
  3728. mmc-ddr-1_8v;
  3729. mmc-ddr-3_3v;
  3730. pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
  3731. pinctrl-0 = <0x0000009c>;
  3732. bus-width = <0x00000004>;
  3733. cd-gpios = <0x0000009d 0x0000001b 0x00000001>;
  3734. pinctrl-1 = <0x0000009e>;
  3735. pinctrl-2 = <0x0000009f>;
  3736. pinctrl-3 = <0x000000a0>;
  3737. pinctrl-4 = <0x000000a1>;
  3738. pinctrl-5 = <0x000000a2 0x000000a3>;
  3739. pinctrl-6 = <0x000000a4 0x000000a5>;
  3740. vmmc-supply = <0x00000093>;
  3741. vqmmc-supply = <0x000000a6>;
  3742. };
  3743. };
  3744. target-module@a2000 {
  3745. compatible = "ti,sysc";
  3746. status = "disabled";
  3747. #address-cells = <0x00000001>;
  3748. #size-cells = <0x00000001>;
  3749. ranges = <0x00000000 0x000a2000 0x00001000>;
  3750. };
  3751. target-module@a4000 {
  3752. compatible = "ti,sysc";
  3753. status = "disabled";
  3754. #address-cells = <0x00000001>;
  3755. #size-cells = <0x00000001>;
  3756. ranges = <0x00000000 0x000a4000 0x00001000 0x00001000 0x000a5000 0x00001000>;
  3757. };
  3758. target-module@a8000 {
  3759. compatible = "ti,sysc";
  3760. status = "disabled";
  3761. #address-cells = <0x00000001>;
  3762. #size-cells = <0x00000001>;
  3763. ranges = <0x00000000 0x000a8000 0x00004000>;
  3764. };
  3765. target-module@ad000 {
  3766. compatible = "ti,sysc-omap4", "ti,sysc";
  3767. ti,hwmods = "mmc3";
  3768. reg = <0x000ad000 0x00000004 0x000ad010 0x00000004>;
  3769. reg-names = "rev", "sysc";
  3770. ti,sysc-mask = <0x00000003>;
  3771. ti,sysc-midle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3772. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3773. clocks = <0x00000090 0x000000f8 0x00000000>;
  3774. clock-names = "fck";
  3775. #address-cells = <0x00000001>;
  3776. #size-cells = <0x00000001>;
  3777. ranges = <0x00000000 0x000ad000 0x00001000>;
  3778. mmc@0 {
  3779. compatible = "ti,dra7-sdhci";
  3780. reg = <0x00000000 0x00000400>;
  3781. interrupts = <0x00000000 0x00000059 0x00000004>;
  3782. status = "disabled";
  3783. max-frequency = <0x03d09000>;
  3784. sdhci-caps-mask = <0x00000000 0x00400000>;
  3785. };
  3786. };
  3787. target-module@b2000 {
  3788. compatible = "ti,sysc-omap2", "ti,sysc";
  3789. ti,hwmods = "hdq1w";
  3790. reg = <0x000b2000 0x00000004 0x000b2014 0x00000004 0x000b2018 0x00000004>;
  3791. reg-names = "rev", "sysc", "syss";
  3792. ti,sysc-mask = <0x00000003>;
  3793. ti,syss-mask = <0x00000001>;
  3794. ti,no-reset-on-init;
  3795. clocks = <0x00000090 0x00000060 0x00000000>;
  3796. clock-names = "fck";
  3797. #address-cells = <0x00000001>;
  3798. #size-cells = <0x00000001>;
  3799. ranges = <0x00000000 0x000b2000 0x00001000>;
  3800. 1w@0 {
  3801. compatible = "ti,omap3-1w";
  3802. reg = <0x00000000 0x00001000>;
  3803. interrupts = <0x00000000 0x00000035 0x00000004>;
  3804. };
  3805. };
  3806. target-module@b4000 {
  3807. compatible = "ti,sysc-omap4", "ti,sysc";
  3808. ti,hwmods = "mmc2";
  3809. reg = <0x000b4000 0x00000004 0x000b4010 0x00000004>;
  3810. reg-names = "rev", "sysc";
  3811. ti,sysc-mask = <0x00000003>;
  3812. ti,sysc-midle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3813. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3814. clocks = <0x0000005a 0x00000010 0x00000000>;
  3815. clock-names = "fck";
  3816. #address-cells = <0x00000001>;
  3817. #size-cells = <0x00000001>;
  3818. ranges = <0x00000000 0x000b4000 0x00001000>;
  3819. mmc@0 {
  3820. compatible = "ti,dra7-sdhci";
  3821. reg = <0x00000000 0x00000400>;
  3822. interrupts = <0x00000000 0x00000051 0x00000004>;
  3823. status = "okay";
  3824. max-frequency = "qḞ";
  3825. sdhci-caps-mask = <0x00000007 0x00000000>;
  3826. mmc-hs200-1_8v;
  3827. mmc-ddr-1_8v;
  3828. mmc-ddr-3_3v;
  3829. pinctrl-names = "default", "hs", "ddr_1_8v";
  3830. pinctrl-0 = <0x000000a7>;
  3831. vmmc-supply = <0x00000093>;
  3832. vqmmc-supply = <0x00000093>;
  3833. bus-width = <0x00000008>;
  3834. non-removable;
  3835. no-1-8-v;
  3836. pinctrl-1 = <0x000000a8>;
  3837. pinctrl-2 = <0x000000a9>;
  3838. };
  3839. };
  3840. target-module@b8000 {
  3841. compatible = "ti,sysc-omap4", "ti,sysc";
  3842. ti,hwmods = "mcspi3";
  3843. reg = <0x000b8000 0x00000004 0x000b8010 0x00000004>;
  3844. reg-names = "rev", "sysc";
  3845. ti,sysc-mask = <0x00000003>;
  3846. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3847. clocks = <0x00000090 0x000000d8 0x00000000>;
  3848. clock-names = "fck";
  3849. #address-cells = <0x00000001>;
  3850. #size-cells = <0x00000001>;
  3851. ranges = <0x00000000 0x000b8000 0x00001000>;
  3852. spi@0 {
  3853. compatible = "ti,omap4-mcspi";
  3854. reg = <0x00000000 0x00000200>;
  3855. interrupts = <0x00000000 0x00000056 0x00000004>;
  3856. #address-cells = <0x00000001>;
  3857. #size-cells = <0x00000000>;
  3858. ti,spi-num-cs = <0x00000002>;
  3859. dmas = <0x00000091 0x0000000f 0x00000091 0x00000010>;
  3860. dma-names = "tx0", "rx0";
  3861. status = "disabled";
  3862. };
  3863. };
  3864. target-module@ba000 {
  3865. compatible = "ti,sysc-omap4", "ti,sysc";
  3866. ti,hwmods = "mcspi4";
  3867. reg = <0x000ba000 0x00000004 0x000ba010 0x00000004>;
  3868. reg-names = "rev", "sysc";
  3869. ti,sysc-mask = <0x00000003>;
  3870. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3871. clocks = <0x00000090 0x000000e0 0x00000000>;
  3872. clock-names = "fck";
  3873. #address-cells = <0x00000001>;
  3874. #size-cells = <0x00000001>;
  3875. ranges = <0x00000000 0x000ba000 0x00001000>;
  3876. spi@0 {
  3877. compatible = "ti,omap4-mcspi";
  3878. reg = <0x00000000 0x00000200>;
  3879. interrupts = <0x00000000 0x0000002b 0x00000004>;
  3880. #address-cells = <0x00000001>;
  3881. #size-cells = <0x00000000>;
  3882. ti,spi-num-cs = <0x00000001>;
  3883. dmas = <0x00000091 0x00000046 0x00000091 0x00000047>;
  3884. dma-names = "tx0", "rx0";
  3885. status = "disabled";
  3886. };
  3887. };
  3888. target-module@d1000 {
  3889. compatible = "ti,sysc-omap4", "ti,sysc";
  3890. ti,hwmods = "mmc4";
  3891. reg = <0x000d1000 0x00000004 0x000d1010 0x00000004>;
  3892. reg-names = "rev", "sysc";
  3893. ti,sysc-mask = <0x00000003>;
  3894. ti,sysc-midle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3895. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3896. clocks = <0x00000090 0x00000100 0x00000000>;
  3897. clock-names = "fck";
  3898. #address-cells = <0x00000001>;
  3899. #size-cells = <0x00000001>;
  3900. ranges = <0x00000000 0x000d1000 0x00001000>;
  3901. mmc@0 {
  3902. compatible = "ti,dra7-sdhci";
  3903. reg = <0x00000000 0x00000400>;
  3904. interrupts = <0x00000000 0x0000005b 0x00000004>;
  3905. status = "disabled";
  3906. max-frequency = "qḞ";
  3907. sdhci-caps-mask = <0x00000000 0x00400000>;
  3908. };
  3909. };
  3910. target-module@d5000 {
  3911. compatible = "ti,sysc";
  3912. status = "disabled";
  3913. #address-cells = <0x00000001>;
  3914. #size-cells = <0x00000001>;
  3915. ranges = <0x00000000 0x000d5000 0x00001000>;
  3916. };
  3917. };
  3918. segment@200000 {
  3919. compatible = "simple-bus";
  3920. #address-cells = <0x00000001>;
  3921. #size-cells = <0x00000001>;
  3922. };
  3923. };
  3924. interconnect@48400000 {
  3925. compatible = "ti,dra7-l4-per2", "simple-bus";
  3926. reg = <0x48400000 0x00000800 0x48400800 0x00000800 0x48401000 0x00000400 0x48401400 0x00000400 0x48401800 0x00000400>;
  3927. reg-names = "ap", "la", "ia0", "ia1", "ia2";
  3928. #address-cells = <0x00000001>;
  3929. #size-cells = <0x00000001>;
  3930. ranges = * 0x83013338 [0x0000006c];
  3931. segment@0 {
  3932. compatible = "simple-bus";
  3933. #address-cells = <0x00000001>;
  3934. #size-cells = <0x00000001>;
  3935. ranges = * 0x830133f8 [0x00000354];
  3936. target-module@20000 {
  3937. compatible = "ti,sysc-omap2", "ti,sysc";
  3938. ti,hwmods = "uart7";
  3939. reg = <0x00020050 0x00000004 0x00020054 0x00000004 0x00020058 0x00000004>;
  3940. reg-names = "rev", "sysc", "syss";
  3941. ti,sysc-mask = <0x00000007>;
  3942. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3943. ti,syss-mask = <0x00000001>;
  3944. clocks = <0x00000057 0x000001c4 0x00000000>;
  3945. clock-names = "fck";
  3946. #address-cells = <0x00000001>;
  3947. #size-cells = <0x00000001>;
  3948. ranges = <0x00000000 0x00020000 0x00001000>;
  3949. serial@0 {
  3950. compatible = "ti,dra742-uart", "ti,omap4-uart";
  3951. reg = <0x00000000 0x00000100>;
  3952. interrupts = <0x00000000 0x000000da 0x00000004>;
  3953. clock-frequency = <0x02dc6c00>;
  3954. status = "disabled";
  3955. };
  3956. };
  3957. target-module@22000 {
  3958. compatible = "ti,sysc-omap2", "ti,sysc";
  3959. ti,hwmods = "uart8";
  3960. reg = <0x00022050 0x00000004 0x00022054 0x00000004 0x00022058 0x00000004>;
  3961. reg-names = "rev", "sysc", "syss";
  3962. ti,sysc-mask = <0x00000007>;
  3963. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3964. ti,syss-mask = <0x00000001>;
  3965. clocks = <0x00000057 0x000001d4 0x00000000>;
  3966. clock-names = "fck";
  3967. #address-cells = <0x00000001>;
  3968. #size-cells = <0x00000001>;
  3969. ranges = <0x00000000 0x00022000 0x00001000>;
  3970. serial@0 {
  3971. compatible = "ti,dra742-uart", "ti,omap4-uart";
  3972. reg = <0x00000000 0x00000100>;
  3973. interrupts = <0x00000000 0x000000db 0x00000004>;
  3974. clock-frequency = <0x02dc6c00>;
  3975. status = "disabled";
  3976. };
  3977. };
  3978. target-module@24000 {
  3979. compatible = "ti,sysc-omap2", "ti,sysc";
  3980. ti,hwmods = "uart9";
  3981. reg = <0x00024050 0x00000004 0x00024054 0x00000004 0x00024058 0x00000004>;
  3982. reg-names = "rev", "sysc", "syss";
  3983. ti,sysc-mask = <0x00000007>;
  3984. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  3985. ti,syss-mask = <0x00000001>;
  3986. clocks = <0x00000057 0x000001dc 0x00000000>;
  3987. clock-names = "fck";
  3988. #address-cells = <0x00000001>;
  3989. #size-cells = <0x00000001>;
  3990. ranges = <0x00000000 0x00024000 0x00001000>;
  3991. serial@0 {
  3992. compatible = "ti,dra742-uart", "ti,omap4-uart";
  3993. reg = <0x00000000 0x00000100>;
  3994. interrupts = <0x00000000 0x000000dc 0x00000004>;
  3995. clock-frequency = <0x02dc6c00>;
  3996. status = "disabled";
  3997. };
  3998. };
  3999. target-module@2c000 {
  4000. compatible = "ti,sysc";
  4001. status = "disabled";
  4002. #address-cells = <0x00000001>;
  4003. #size-cells = <0x00000001>;
  4004. ranges = <0x00000000 0x0002c000 0x00001000>;
  4005. };
  4006. target-module@36000 {
  4007. compatible = "ti,sysc";
  4008. status = "disabled";
  4009. #address-cells = <0x00000001>;
  4010. #size-cells = <0x00000001>;
  4011. ranges = <0x00000000 0x00036000 0x00001000>;
  4012. };
  4013. target-module@3a000 {
  4014. compatible = "ti,sysc";
  4015. status = "disabled";
  4016. #address-cells = <0x00000001>;
  4017. #size-cells = <0x00000001>;
  4018. ranges = <0x00000000 0x0003a000 0x00001000>;
  4019. };
  4020. target-module@3c000 {
  4021. compatible = "ti,sysc-omap4", "ti,sysc";
  4022. reg = <0x0003c000 0x00000004>;
  4023. reg-names = "rev";
  4024. clocks = <0x00000010 0x00000000 0x00000000>;
  4025. clock-names = "fck";
  4026. #address-cells = <0x00000001>;
  4027. #size-cells = <0x00000001>;
  4028. ranges = <0x00000000 0x0003c000 0x00001000>;
  4029. atl@0 {
  4030. compatible = "ti,dra7-atl";
  4031. reg = <0x00000000 0x000003ff>;
  4032. ti,provided-clocks = <0x000000aa 0x000000ab 0x000000ac 0x000000ad>;
  4033. clocks = <0x00000010 0x00000000 0x0000001a>;
  4034. clock-names = "fck";
  4035. status = "disabled";
  4036. };
  4037. };
  4038. target-module@3e000 {
  4039. compatible = "ti,sysc-omap4", "ti,sysc";
  4040. ti,hwmods = "epwmss0";
  4041. reg = <0x0003e000 0x00000004 0x0003e004 0x00000004>;
  4042. reg-names = "rev", "sysc";
  4043. ti,sysc-mask = <0x00000001>;
  4044. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002>;
  4045. clocks = <0x00000057 0x000000b8 0x00000000>;
  4046. clock-names = "fck";
  4047. #address-cells = <0x00000001>;
  4048. #size-cells = <0x00000001>;
  4049. ranges = <0x00000000 0x0003e000 0x00001000>;
  4050. epwmss@0 {
  4051. compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
  4052. reg = <0x00000000 0x00000030>;
  4053. #address-cells = <0x00000001>;
  4054. #size-cells = <0x00000001>;
  4055. status = "disabled";
  4056. ranges = <0x00000000 0x00000000 0x00001000>;
  4057. ecap@100 {
  4058. compatible = "ti,dra746-ecap", "ti,am3352-ecap";
  4059. #pwm-cells = <0x00000003>;
  4060. reg = <0x00000100 0x00000080>;
  4061. clocks = <0x0000000b>;
  4062. clock-names = "fck";
  4063. status = "disabled";
  4064. };
  4065. pwm@200 {
  4066. compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm";
  4067. #pwm-cells = <0x00000003>;
  4068. reg = <0x00000200 0x00000080>;
  4069. clocks = <0x000000ae 0x0000000b>;
  4070. clock-names = "tbclk", "fck";
  4071. status = "disabled";
  4072. };
  4073. };
  4074. };
  4075. target-module@40000 {
  4076. compatible = "ti,sysc-omap4", "ti,sysc";
  4077. ti,hwmods = "epwmss1";
  4078. reg = <0x00040000 0x00000004 0x00040004 0x00000004>;
  4079. reg-names = "rev", "sysc";
  4080. ti,sysc-mask = <0x00000001>;
  4081. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002>;
  4082. clocks = <0x00000057 0x00000084 0x00000000>;
  4083. clock-names = "fck";
  4084. #address-cells = <0x00000001>;
  4085. #size-cells = <0x00000001>;
  4086. ranges = <0x00000000 0x00040000 0x00001000>;
  4087. epwmss@0 {
  4088. compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
  4089. reg = <0x00000000 0x00000030>;
  4090. #address-cells = <0x00000001>;
  4091. #size-cells = <0x00000001>;
  4092. status = "disabled";
  4093. ranges = <0x00000000 0x00000000 0x00001000>;
  4094. ecap@100 {
  4095. compatible = "ti,dra746-ecap", "ti,am3352-ecap";
  4096. #pwm-cells = <0x00000003>;
  4097. reg = <0x00000100 0x00000080>;
  4098. clocks = <0x0000000b>;
  4099. clock-names = "fck";
  4100. status = "disabled";
  4101. };
  4102. pwm@200 {
  4103. compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm";
  4104. #pwm-cells = <0x00000003>;
  4105. reg = <0x00000200 0x00000080>;
  4106. clocks = <0x000000af 0x0000000b>;
  4107. clock-names = "tbclk", "fck";
  4108. status = "disabled";
  4109. };
  4110. };
  4111. };
  4112. target-module@42000 {
  4113. compatible = "ti,sysc-omap4", "ti,sysc";
  4114. ti,hwmods = "epwmss2";
  4115. reg = <0x00042000 0x00000004 0x00042004 0x00000004>;
  4116. reg-names = "rev", "sysc";
  4117. ti,sysc-mask = <0x00000001>;
  4118. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002>;
  4119. clocks = <0x00000057 0x0000008c 0x00000000>;
  4120. clock-names = "fck";
  4121. #address-cells = <0x00000001>;
  4122. #size-cells = <0x00000001>;
  4123. ranges = <0x00000000 0x00042000 0x00001000>;
  4124. epwmss@0 {
  4125. compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
  4126. reg = <0x00000000 0x00000030>;
  4127. #address-cells = <0x00000001>;
  4128. #size-cells = <0x00000001>;
  4129. status = "disabled";
  4130. ranges = <0x00000000 0x00000000 0x00001000>;
  4131. ecap@100 {
  4132. compatible = "ti,dra746-ecap", "ti,am3352-ecap";
  4133. #pwm-cells = <0x00000003>;
  4134. reg = <0x00000100 0x00000080>;
  4135. clocks = <0x0000000b>;
  4136. clock-names = "fck";
  4137. status = "disabled";
  4138. };
  4139. pwm@200 {
  4140. compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm";
  4141. #pwm-cells = <0x00000003>;
  4142. reg = <0x00000200 0x00000080>;
  4143. clocks = <0x000000b0 0x0000000b>;
  4144. clock-names = "tbclk", "fck";
  4145. status = "disabled";
  4146. };
  4147. };
  4148. };
  4149. target-module@46000 {
  4150. compatible = "ti,sysc";
  4151. status = "disabled";
  4152. #address-cells = <0x00000001>;
  4153. #size-cells = <0x00000001>;
  4154. ranges = <0x00000000 0x00046000 0x00001000>;
  4155. };
  4156. target-module@48000 {
  4157. compatible = "ti,sysc";
  4158. status = "disabled";
  4159. #address-cells = <0x00000001>;
  4160. #size-cells = <0x00000001>;
  4161. ranges = <0x00000000 0x00048000 0x00001000>;
  4162. };
  4163. target-module@4a000 {
  4164. compatible = "ti,sysc";
  4165. status = "disabled";
  4166. #address-cells = <0x00000001>;
  4167. #size-cells = <0x00000001>;
  4168. ranges = <0x00000000 0x0004a000 0x00001000>;
  4169. };
  4170. target-module@4c000 {
  4171. compatible = "ti,sysc";
  4172. status = "disabled";
  4173. #address-cells = <0x00000001>;
  4174. #size-cells = <0x00000001>;
  4175. ranges = <0x00000000 0x0004c000 0x00001000>;
  4176. };
  4177. target-module@50000 {
  4178. compatible = "ti,sysc";
  4179. status = "disabled";
  4180. #address-cells = <0x00000001>;
  4181. #size-cells = <0x00000001>;
  4182. ranges = <0x00000000 0x00050000 0x00001000>;
  4183. };
  4184. target-module@54000 {
  4185. compatible = "ti,sysc";
  4186. status = "disabled";
  4187. #address-cells = <0x00000001>;
  4188. #size-cells = <0x00000001>;
  4189. ranges = <0x00000000 0x00054000 0x00001000>;
  4190. };
  4191. target-module@58000 {
  4192. compatible = "ti,sysc";
  4193. status = "disabled";
  4194. #address-cells = <0x00000001>;
  4195. #size-cells = <0x00000001>;
  4196. ranges = <0x00000000 0x00058000 0x00002000>;
  4197. };
  4198. target-module@5b000 {
  4199. compatible = "ti,sysc";
  4200. status = "disabled";
  4201. #address-cells = <0x00000001>;
  4202. #size-cells = <0x00000001>;
  4203. ranges = <0x00000000 0x0005b000 0x00001000>;
  4204. };
  4205. target-module@5d000 {
  4206. compatible = "ti,sysc";
  4207. status = "disabled";
  4208. #address-cells = <0x00000001>;
  4209. #size-cells = <0x00000001>;
  4210. ranges = <0x00000000 0x0005d000 0x00001000>;
  4211. };
  4212. target-module@60000 {
  4213. compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
  4214. ti,hwmods = "mcasp1";
  4215. reg = <0x00060000 0x00000004 0x00060004 0x00000004>;
  4216. reg-names = "rev", "sysc";
  4217. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002>;
  4218. clocks = <0x00000094 0x00000000 0x00000000 0x00000094 0x00000000 0x00000018 0x00000094 0x00000000 0x0000001c>;
  4219. clock-names = "fck", "ahclkx", "ahclkr";
  4220. #address-cells = <0x00000001>;
  4221. #size-cells = <0x00000001>;
  4222. ranges = <0x00000000 0x00060000 0x00002000 0x45800000 0x45800000 0x00400000>;
  4223. mcasp@0 {
  4224. compatible = "ti,dra7-mcasp-audio";
  4225. reg = <0x00000000 0x00002000 0x45800000 0x00001000>;
  4226. reg-names = "mpu", "dat";
  4227. interrupts = <0x00000000 0x00000068 0x00000004 0x00000000 0x00000067 0x00000004>;
  4228. interrupt-names = "tx", "rx";
  4229. dmas = <0x000000b1 0x00000081 0x00000001 0x000000b1 0x00000080 0x00000001>;
  4230. dma-names = "tx", "rx";
  4231. clocks = <0x00000094 0x00000000 0x00000016 0x00000094 0x00000000 0x00000018 0x00000094 0x00000000 0x0000001c>;
  4232. clock-names = "fck", "ahclkx", "ahclkr";
  4233. status = "disabled";
  4234. };
  4235. };
  4236. target-module@64000 {
  4237. compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
  4238. ti,hwmods = "mcasp2";
  4239. reg = <0x00064000 0x00000004 0x00064004 0x00000004>;
  4240. reg-names = "rev", "sysc";
  4241. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002>;
  4242. clocks = <0x00000057 0x00000154 0x00000000 0x00000057 0x00000154 0x00000018 0x00000057 0x00000154 0x0000001c>;
  4243. clock-names = "fck", "ahclkx", "ahclkr";
  4244. #address-cells = <0x00000001>;
  4245. #size-cells = <0x00000001>;
  4246. ranges = <0x00000000 0x00064000 0x00002000 0x45c00000 0x45c00000 0x00400000>;
  4247. mcasp@0 {
  4248. compatible = "ti,dra7-mcasp-audio";
  4249. reg = <0x00000000 0x00002000 0x45c00000 0x00001000>;
  4250. reg-names = "mpu", "dat";
  4251. interrupts = <0x00000000 0x00000095 0x00000004 0x00000000 0x00000094 0x00000004>;
  4252. interrupt-names = "tx", "rx";
  4253. dmas = <0x000000b1 0x00000083 0x00000001 0x000000b1 0x00000082 0x00000001>;
  4254. dma-names = "tx", "rx";
  4255. clocks = <0x00000057 0x00000154 0x00000016 0x00000057 0x00000154 0x00000018 0x00000057 0x00000154 0x0000001c>;
  4256. clock-names = "fck", "ahclkx", "ahclkr";
  4257. status = "disabled";
  4258. };
  4259. };
  4260. target-module@68000 {
  4261. compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
  4262. ti,hwmods = "mcasp3";
  4263. reg = <0x00068000 0x00000004 0x00068004 0x00000004>;
  4264. reg-names = "rev", "sysc";
  4265. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002>;
  4266. clocks = <0x00000057 0x0000015c 0x00000000 0x00000057 0x0000015c 0x00000018 0x00000057 0x0000015c 0x0000001c>;
  4267. clock-names = "fck", "ahclkx", "ahclkr";
  4268. #address-cells = <0x00000001>;
  4269. #size-cells = <0x00000001>;
  4270. ranges = <0x00000000 0x00068000 0x00002000 0x46000000 0x46000000 0x00400000>;
  4271. mcasp@0 {
  4272. compatible = "ti,dra7-mcasp-audio";
  4273. reg = <0x00000000 0x00002000 0x46000000 0x00001000>;
  4274. reg-names = "mpu", "dat";
  4275. interrupts = <0x00000000 0x00000097 0x00000004 0x00000000 0x00000096 0x00000004>;
  4276. interrupt-names = "tx", "rx";
  4277. dmas = <0x000000b1 0x00000085 0x00000001 0x000000b1 0x00000084 0x00000001>;
  4278. dma-names = "tx", "rx";
  4279. clocks = <0x00000057 0x0000015c 0x00000016 0x00000057 0x0000015c 0x00000018>;
  4280. clock-names = "fck", "ahclkx";
  4281. status = "okay";
  4282. #sound-dai-cells = <0x00000000>;
  4283. assigned-clocks = <0x00000057 0x0000015c 0x00000018>;
  4284. assigned-clock-parents = <0x0000006c>;
  4285. op-mode = <0x00000000>;
  4286. tdm-slots = <0x00000002>;
  4287. serial-dir = <0x00000001 0x00000002 0x00000000 0x00000000>;
  4288. tx-num-evt = <0x00000020>;
  4289. rx-num-evt = <0x00000020>;
  4290. phandle = <0x000000da>;
  4291. };
  4292. };
  4293. target-module@6c000 {
  4294. compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
  4295. ti,hwmods = "mcasp4";
  4296. reg = <0x0006c000 0x00000004 0x0006c004 0x00000004>;
  4297. reg-names = "rev", "sysc";
  4298. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002>;
  4299. clocks = <0x00000057 0x0000018c 0x00000000 0x00000057 0x0000018c 0x00000018 0x00000057 0x0000018c 0x0000001c>;
  4300. clock-names = "fck", "ahclkx", "ahclkr";
  4301. #address-cells = <0x00000001>;
  4302. #size-cells = <0x00000001>;
  4303. ranges = <0x00000000 0x0006c000 0x00002000 0x48436000 0x48436000 0x00400000>;
  4304. mcasp@0 {
  4305. compatible = "ti,dra7-mcasp-audio";
  4306. reg = <0x00000000 0x00002000 0x48436000 0x00001000>;
  4307. reg-names = "mpu", "dat";
  4308. interrupts = <0x00000000 0x00000099 0x00000004 0x00000000 0x00000098 0x00000004>;
  4309. interrupt-names = "tx", "rx";
  4310. dmas = <0x000000b1 0x00000087 0x00000001 0x000000b1 0x00000086 0x00000001>;
  4311. dma-names = "tx", "rx";
  4312. clocks = <0x00000057 0x0000018c 0x00000016 0x00000057 0x0000018c 0x00000018>;
  4313. clock-names = "fck", "ahclkx";
  4314. status = "disabled";
  4315. };
  4316. };
  4317. target-module@70000 {
  4318. compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
  4319. ti,hwmods = "mcasp5";
  4320. reg = <0x00070000 0x00000004 0x00070004 0x00000004>;
  4321. reg-names = "rev", "sysc";
  4322. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002>;
  4323. clocks = <0x00000057 0x0000016c 0x00000000 0x00000057 0x0000016c 0x00000018 0x00000057 0x0000016c 0x0000001c>;
  4324. clock-names = "fck", "ahclkx", "ahclkr";
  4325. #address-cells = <0x00000001>;
  4326. #size-cells = <0x00000001>;
  4327. ranges = <0x00000000 0x00070000 0x00002000 0x4843a000 0x4843a000 0x00400000>;
  4328. mcasp@0 {
  4329. compatible = "ti,dra7-mcasp-audio";
  4330. reg = <0x00000000 0x00002000 0x4843a000 0x00001000>;
  4331. reg-names = "mpu", "dat";
  4332. interrupts = <0x00000000 0x0000009b 0x00000004 0x00000000 0x0000009a 0x00000004>;
  4333. interrupt-names = "tx", "rx";
  4334. dmas = <0x000000b1 0x00000089 0x00000001 0x000000b1 0x00000088 0x00000001>;
  4335. dma-names = "tx", "rx";
  4336. clocks = <0x00000057 0x0000016c 0x00000016 0x00000057 0x0000016c 0x00000018>;
  4337. clock-names = "fck", "ahclkx";
  4338. status = "disabled";
  4339. };
  4340. };
  4341. target-module@74000 {
  4342. compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
  4343. ti,hwmods = "mcasp6";
  4344. reg = <0x00074000 0x00000004 0x00074004 0x00000004>;
  4345. reg-names = "rev", "sysc";
  4346. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002>;
  4347. clocks = <0x00000057 0x000001f8 0x00000000 0x00000057 0x000001f8 0x00000018 0x00000057 0x000001f8 0x0000001c>;
  4348. clock-names = "fck", "ahclkx", "ahclkr";
  4349. #address-cells = <0x00000001>;
  4350. #size-cells = <0x00000001>;
  4351. ranges = <0x00000000 0x00074000 0x00002000 0x4844c000 0x4844c000 0x00400000>;
  4352. mcasp@0 {
  4353. compatible = "ti,dra7-mcasp-audio";
  4354. reg = <0x00000000 0x00002000 0x4844c000 0x00001000>;
  4355. reg-names = "mpu", "dat";
  4356. interrupts = <0x00000000 0x0000009d 0x00000004 0x00000000 0x0000009c 0x00000004>;
  4357. interrupt-names = "tx", "rx";
  4358. dmas = <0x000000b1 0x0000008b 0x00000001 0x000000b1 0x0000008a 0x00000001>;
  4359. dma-names = "tx", "rx";
  4360. clocks = <0x00000057 0x000001f8 0x00000016 0x00000057 0x000001f8 0x00000018>;
  4361. clock-names = "fck", "ahclkx";
  4362. status = "disabled";
  4363. };
  4364. };
  4365. target-module@78000 {
  4366. compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
  4367. ti,hwmods = "mcasp7";
  4368. reg = <0x00078000 0x00000004 0x00078004 0x00000004>;
  4369. reg-names = "rev", "sysc";
  4370. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002>;
  4371. clocks = <0x00000057 0x000001fc 0x00000000 0x00000057 0x000001fc 0x00000018 0x00000057 0x000001fc 0x0000001c>;
  4372. clock-names = "fck", "ahclkx", "ahclkr";
  4373. #address-cells = <0x00000001>;
  4374. #size-cells = <0x00000001>;
  4375. ranges = <0x00000000 0x00078000 0x00002000 0x48450000 0x48450000 0x00400000>;
  4376. mcasp@0 {
  4377. compatible = "ti,dra7-mcasp-audio";
  4378. reg = <0x00000000 0x00002000 0x48450000 0x00001000>;
  4379. reg-names = "mpu", "dat";
  4380. interrupts = <0x00000000 0x0000009f 0x00000004 0x00000000 0x0000009e 0x00000004>;
  4381. interrupt-names = "tx", "rx";
  4382. dmas = <0x000000b1 0x0000008d 0x00000001 0x000000b1 0x0000008c 0x00000001>;
  4383. dma-names = "tx", "rx";
  4384. clocks = <0x00000057 0x000001fc 0x00000016 0x00000057 0x000001fc 0x00000018>;
  4385. clock-names = "fck", "ahclkx";
  4386. status = "disabled";
  4387. };
  4388. };
  4389. target-module@7c000 {
  4390. compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
  4391. ti,hwmods = "mcasp8";
  4392. reg = <0x0007c000 0x00000004 0x0007c004 0x00000004>;
  4393. reg-names = "rev", "sysc";
  4394. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002>;
  4395. clocks = <0x00000057 0x00000184 0x00000000 0x00000057 0x00000184 0x00000018 0x00000057 0x00000184 0x0000001c>;
  4396. clock-names = "fck", "ahclkx", "ahclkr";
  4397. #address-cells = <0x00000001>;
  4398. #size-cells = <0x00000001>;
  4399. ranges = <0x00000000 0x0007c000 0x00002000 0x48454000 0x48454000 0x00400000>;
  4400. mcasp@0 {
  4401. compatible = "ti,dra7-mcasp-audio";
  4402. reg = <0x00000000 0x00002000 0x48454000 0x00001000>;
  4403. reg-names = "mpu", "dat";
  4404. interrupts = <0x00000000 0x000000a1 0x00000004 0x00000000 0x000000a0 0x00000004>;
  4405. interrupt-names = "tx", "rx";
  4406. dmas = <0x000000b1 0x0000008f 0x00000001 0x000000b1 0x0000008e 0x00000001>;
  4407. dma-names = "tx", "rx";
  4408. clocks = <0x00000057 0x00000184 0x00000016 0x00000057 0x00000184 0x00000018>;
  4409. clock-names = "fck", "ahclkx";
  4410. status = "disabled";
  4411. };
  4412. };
  4413. target-module@80000 {
  4414. compatible = "ti,sysc-omap4", "ti,sysc";
  4415. reg = <0x00080000 0x00000004>;
  4416. reg-names = "rev";
  4417. clocks = <0x00000057 0x000001e4 0x00000000>;
  4418. clock-names = "fck";
  4419. #address-cells = <0x00000001>;
  4420. #size-cells = <0x00000001>;
  4421. ranges = <0x00000000 0x00080000 0x00002000>;
  4422. can@0 {
  4423. compatible = "ti,dra7-d_can";
  4424. reg = <0x00000000 0x00002000>;
  4425. syscon-raminit = <0x00000009 0x00000558 0x00000001>;
  4426. interrupts = <0x00000000 0x000000e1 0x00000004>;
  4427. clocks = <0x00000011>;
  4428. status = "disabled";
  4429. };
  4430. };
  4431. target-module@84000 {
  4432. compatible = "ti,sysc-omap4-simple", "ti,sysc";
  4433. ti,hwmods = "gmac";
  4434. reg = <0x00085200 0x00000004 0x00085208 0x00000004 0x00085204 0x00000004>;
  4435. reg-names = "rev", "sysc", "syss";
  4436. ti,sysc-mask = <0x00000000>;
  4437. ti,sysc-midle = <0x00000000 0x00000001>;
  4438. ti,sysc-sidle = <0x00000000 0x00000001>;
  4439. ti,syss-mask = <0x00000001>;
  4440. clocks = <0x000000b2 0x00000000 0x00000000>;
  4441. clock-names = "fck";
  4442. #address-cells = <0x00000001>;
  4443. #size-cells = <0x00000001>;
  4444. ranges = <0x00000000 0x00084000 0x00004000>;
  4445. ti,no-idle;
  4446. ethernet@0 {
  4447. compatible = "ti,dra7-cpsw", "ti,cpsw";
  4448. clocks = <0x000000b3 0x000000b2 0x00000000 0x00000019>;
  4449. clock-names = "fck", "cpts";
  4450. cpdma_channels = <0x00000008>;
  4451. ale_entries = <0x00000400>;
  4452. bd_ram_size = <0x00002000>;
  4453. mac_control = <0x00000020>;
  4454. slaves = <0x00000002>;
  4455. active_slave = <0x00000000>;
  4456. cpts_clock_mult = <0x784cfe14>;
  4457. cpts_clock_shift = <0x0000001d>;
  4458. reg = <0x00000000 0x00001000 0x00001200 0x00002e00>;
  4459. #address-cells = <0x00000001>;
  4460. #size-cells = <0x00000001>;
  4461. interrupts = <0x00000000 0x0000014e 0x00000004 0x00000000 0x0000014f 0x00000004 0x00000000 0x00000150 0x00000004 0x00000000 0x00000151 0x00000004>;
  4462. ranges = <0x00000000 0x00000000 0x00004000>;
  4463. syscon = <0x00000009>;
  4464. status = "okay";
  4465. dual_emac;
  4466. mdio@1000 {
  4467. compatible = "ti,cpsw-mdio", "ti,davinci_mdio";
  4468. #address-cells = <0x00000001>;
  4469. #size-cells = <0x00000000>;
  4470. ti,hwmods = "davinci_mdio";
  4471. bus_freq = <0x000f4240>;
  4472. reg = <0x00001000 0x00000100>;
  4473. ethernet-phy@1 {
  4474. reg = <0x00000001>;
  4475. phandle = <0x000000b5>;
  4476. };
  4477. ethernet-phy@2 {
  4478. reg = <0x00000002>;
  4479. phandle = <0x000000b6>;
  4480. };
  4481. };
  4482. slave@200 {
  4483. mac-address = [00 00 00 00 00 00];
  4484. phys = <0x000000b4 0x00000001>;
  4485. phy-handle = <0x000000b5>;
  4486. phy-mode = "rgmii";
  4487. dual_emac_res_vlan = <0x00000001>;
  4488. };
  4489. slave@300 {
  4490. mac-address = [00 00 00 00 00 00];
  4491. phys = <0x000000b4 0x00000002>;
  4492. phy-handle = <0x000000b6>;
  4493. phy-mode = "rgmii";
  4494. dual_emac_res_vlan = <0x00000002>;
  4495. };
  4496. };
  4497. };
  4498. };
  4499. };
  4500. interconnect@48800000 {
  4501. compatible = "ti,dra7-l4-per3", "simple-bus";
  4502. reg = <0x48800000 0x00000800 0x48800800 0x00000800 0x48801000 0x00000400 0x48801400 0x00000400 0x48801800 0x00000400>;
  4503. reg-names = "ap", "la", "ia0", "ia1", "ia2";
  4504. #address-cells = <0x00000001>;
  4505. #size-cells = <0x00000001>;
  4506. ranges = <0x00000000 0x48800000 0x00200000>;
  4507. segment@0 {
  4508. compatible = "simple-bus";
  4509. #address-cells = <0x00000001>;
  4510. #size-cells = <0x00000001>;
  4511. ranges = * 0x830167f8 [0x0000048c];
  4512. target-module@2000 {
  4513. compatible = "ti,sysc-omap4", "ti,sysc";
  4514. ti,hwmods = "mailbox13";
  4515. reg = <0x00002000 0x00000004 0x00002010 0x00000004>;
  4516. reg-names = "rev", "sysc";
  4517. ti,sysc-mask = <0x00000001>;
  4518. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002>;
  4519. clocks = <0x00000063 0x00000080 0x00000000>;
  4520. clock-names = "fck";
  4521. #address-cells = <0x00000001>;
  4522. #size-cells = <0x00000001>;
  4523. ranges = <0x00000000 0x00002000 0x00001000>;
  4524. mailbox@0 {
  4525. compatible = "ti,omap4-mailbox";
  4526. reg = <0x00000000 0x00000200>;
  4527. interrupts = <0x00000000 0x0000017b 0x00000004 0x00000000 0x0000017c 0x00000004 0x00000000 0x0000017d 0x00000004 0x00000000 0x0000017e 0x00000004>;
  4528. #mbox-cells = <0x00000001>;
  4529. ti,mbox-num-users = <0x00000004>;
  4530. ti,mbox-num-fifos = <0x0000000c>;
  4531. status = "disabled";
  4532. };
  4533. };
  4534. target-module@4000 {
  4535. compatible = "ti,sysc";
  4536. status = "disabled";
  4537. #address-cells = <0x00000001>;
  4538. #size-cells = <0x00000001>;
  4539. ranges = <0x00000000 0x00004000 0x00001000>;
  4540. };
  4541. target-module@a000 {
  4542. compatible = "ti,sysc";
  4543. status = "disabled";
  4544. #address-cells = <0x00000001>;
  4545. #size-cells = <0x00000001>;
  4546. ranges = <0x00000000 0x0000a000 0x00001000>;
  4547. };
  4548. target-module@10000 {
  4549. compatible = "ti,sysc";
  4550. status = "disabled";
  4551. #address-cells = <0x00000001>;
  4552. #size-cells = <0x00000001>;
  4553. ranges = <0x00000000 0x00010000 0x00001000>;
  4554. };
  4555. target-module@16000 {
  4556. compatible = "ti,sysc";
  4557. status = "disabled";
  4558. #address-cells = <0x00000001>;
  4559. #size-cells = <0x00000001>;
  4560. ranges = <0x00000000 0x00016000 0x00001000>;
  4561. };
  4562. target-module@1c000 {
  4563. compatible = "ti,sysc";
  4564. status = "disabled";
  4565. #address-cells = <0x00000001>;
  4566. #size-cells = <0x00000001>;
  4567. ranges = <0x00000000 0x0001c000 0x00001000>;
  4568. };
  4569. target-module@1e000 {
  4570. compatible = "ti,sysc";
  4571. status = "disabled";
  4572. #address-cells = <0x00000001>;
  4573. #size-cells = <0x00000001>;
  4574. ranges = <0x00000000 0x0001e000 0x00001000>;
  4575. };
  4576. target-module@20000 {
  4577. compatible = "ti,sysc-omap4-timer", "ti,sysc";
  4578. ti,hwmods = "timer5";
  4579. reg = <0x00020000 0x00000004 0x00020010 0x00000004>;
  4580. reg-names = "rev", "sysc";
  4581. ti,sysc-mask = <0x00000003>;
  4582. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  4583. clocks = <0x00000094 0x00000008 0x00000000>;
  4584. clock-names = "fck";
  4585. #address-cells = <0x00000001>;
  4586. #size-cells = <0x00000001>;
  4587. ranges = <0x00000000 0x00020000 0x00001000>;
  4588. timer@0 {
  4589. compatible = "ti,omap5430-timer";
  4590. reg = <0x00000000 0x00000080>;
  4591. clocks = <0x00000094 0x00000008 0x00000018>;
  4592. clock-names = "fck";
  4593. interrupts = <0x00000000 0x00000024 0x00000004>;
  4594. };
  4595. };
  4596. target-module@22000 {
  4597. compatible = "ti,sysc-omap4-timer", "ti,sysc";
  4598. ti,hwmods = "timer6";
  4599. reg = <0x00022000 0x00000004 0x00022010 0x00000004>;
  4600. reg-names = "rev", "sysc";
  4601. ti,sysc-mask = <0x00000003>;
  4602. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  4603. clocks = <0x00000094 0x00000010 0x00000000>;
  4604. clock-names = "fck";
  4605. #address-cells = <0x00000001>;
  4606. #size-cells = <0x00000001>;
  4607. ranges = <0x00000000 0x00022000 0x00001000>;
  4608. timer@0 {
  4609. compatible = "ti,omap5430-timer";
  4610. reg = <0x00000000 0x00000080>;
  4611. clocks = <0x00000094 0x00000010 0x00000018>;
  4612. clock-names = "fck";
  4613. interrupts = <0x00000000 0x00000025 0x00000004>;
  4614. };
  4615. };
  4616. target-module@24000 {
  4617. compatible = "ti,sysc-omap4-timer", "ti,sysc";
  4618. ti,hwmods = "timer7";
  4619. reg = <0x00024000 0x00000004 0x00024010 0x00000004>;
  4620. reg-names = "rev", "sysc";
  4621. ti,sysc-mask = <0x00000003>;
  4622. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  4623. clocks = <0x00000094 0x00000018 0x00000000>;
  4624. clock-names = "fck";
  4625. #address-cells = <0x00000001>;
  4626. #size-cells = <0x00000001>;
  4627. ranges = <0x00000000 0x00024000 0x00001000>;
  4628. timer@0 {
  4629. compatible = "ti,omap5430-timer";
  4630. reg = <0x00000000 0x00000080>;
  4631. clocks = <0x00000094 0x00000018 0x00000018>;
  4632. clock-names = "fck";
  4633. interrupts = <0x00000000 0x00000026 0x00000004>;
  4634. };
  4635. };
  4636. target-module@26000 {
  4637. compatible = "ti,sysc-omap4-timer", "ti,sysc";
  4638. ti,hwmods = "timer8";
  4639. reg = <0x00026000 0x00000004 0x00026010 0x00000004>;
  4640. reg-names = "rev", "sysc";
  4641. ti,sysc-mask = <0x00000003>;
  4642. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  4643. clocks = <0x00000094 0x00000020 0x00000000>;
  4644. clock-names = "fck";
  4645. #address-cells = <0x00000001>;
  4646. #size-cells = <0x00000001>;
  4647. ranges = <0x00000000 0x00026000 0x00001000>;
  4648. timer@0 {
  4649. compatible = "ti,omap5430-timer";
  4650. reg = <0x00000000 0x00000080>;
  4651. clocks = <0x00000094 0x00000020 0x00000018>;
  4652. clock-names = "fck";
  4653. interrupts = <0x00000000 0x00000027 0x00000004>;
  4654. };
  4655. };
  4656. target-module@28000 {
  4657. compatible = "ti,sysc-omap4-timer", "ti,sysc";
  4658. ti,hwmods = "timer13";
  4659. reg = <0x00028000 0x00000004 0x00028010 0x00000004>;
  4660. reg-names = "rev", "sysc";
  4661. ti,sysc-mask = <0x00000003>;
  4662. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  4663. clocks = <0x000000b7 0x000000b4 0x00000000>;
  4664. clock-names = "fck";
  4665. #address-cells = <0x00000001>;
  4666. #size-cells = <0x00000001>;
  4667. ranges = <0x00000000 0x00028000 0x00001000>;
  4668. timer@0 {
  4669. compatible = "ti,omap5430-timer";
  4670. reg = <0x00000000 0x00000080>;
  4671. clocks = <0x000000b7 0x000000b4 0x00000018>;
  4672. clock-names = "fck";
  4673. interrupts = <0x00000000 0x00000153 0x00000004>;
  4674. };
  4675. };
  4676. target-module@2a000 {
  4677. compatible = "ti,sysc-omap4-timer", "ti,sysc";
  4678. ti,hwmods = "timer14";
  4679. reg = <0x0002a000 0x00000004 0x0002a010 0x00000004>;
  4680. reg-names = "rev", "sysc";
  4681. ti,sysc-mask = <0x00000003>;
  4682. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  4683. clocks = <0x000000b7 0x000000bc 0x00000000>;
  4684. clock-names = "fck";
  4685. #address-cells = <0x00000001>;
  4686. #size-cells = <0x00000001>;
  4687. ranges = <0x00000000 0x0002a000 0x00001000>;
  4688. timer@0 {
  4689. compatible = "ti,omap5430-timer";
  4690. reg = <0x00000000 0x00000080>;
  4691. clocks = <0x000000b7 0x000000bc 0x00000018>;
  4692. clock-names = "fck";
  4693. interrupts = <0x00000000 0x00000154 0x00000004>;
  4694. };
  4695. };
  4696. target-module@2c000 {
  4697. compatible = "ti,sysc-omap4-timer", "ti,sysc";
  4698. ti,hwmods = "timer15";
  4699. reg = <0x0002c000 0x00000004 0x0002c010 0x00000004>;
  4700. reg-names = "rev", "sysc";
  4701. ti,sysc-mask = <0x00000003>;
  4702. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  4703. clocks = <0x000000b7 0x000000c4 0x00000000>;
  4704. clock-names = "fck";
  4705. #address-cells = <0x00000001>;
  4706. #size-cells = <0x00000001>;
  4707. ranges = <0x00000000 0x0002c000 0x00001000>;
  4708. timer@0 {
  4709. compatible = "ti,omap5430-timer";
  4710. reg = <0x00000000 0x00000080>;
  4711. clocks = <0x000000b7 0x000000c4 0x00000018>;
  4712. clock-names = "fck";
  4713. interrupts = <0x00000000 0x00000155 0x00000004>;
  4714. };
  4715. };
  4716. target-module@2e000 {
  4717. compatible = "ti,sysc-omap4-timer", "ti,sysc";
  4718. ti,hwmods = "timer16";
  4719. reg = <0x0002e000 0x00000004 0x0002e010 0x00000004>;
  4720. reg-names = "rev", "sysc";
  4721. ti,sysc-mask = <0x00000003>;
  4722. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  4723. clocks = <0x000000b7 0x0000011c 0x00000000>;
  4724. clock-names = "fck";
  4725. #address-cells = <0x00000001>;
  4726. #size-cells = <0x00000001>;
  4727. ranges = <0x00000000 0x0002e000 0x00001000>;
  4728. timer@0 {
  4729. compatible = "ti,omap5430-timer";
  4730. reg = <0x00000000 0x00000080>;
  4731. clocks = <0x000000b7 0x0000011c 0x00000018>;
  4732. clock-names = "fck";
  4733. interrupts = <0x00000000 0x00000156 0x00000004>;
  4734. };
  4735. };
  4736. target-module@38000 {
  4737. compatible = "ti,sysc-omap4-simple", "ti,sysc";
  4738. ti,hwmods = "rtcss";
  4739. reg = <0x00038074 0x00000004 0x00038078 0x00000004>;
  4740. reg-names = "rev", "sysc";
  4741. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  4742. clocks = <0x000000b8 0x00000024 0x00000000>;
  4743. clock-names = "fck";
  4744. #address-cells = <0x00000001>;
  4745. #size-cells = <0x00000001>;
  4746. ranges = <0x00000000 0x00038000 0x00001000>;
  4747. rtc@0 {
  4748. compatible = "ti,am3352-rtc";
  4749. reg = <0x00000000 0x00000100>;
  4750. interrupts = <0x00000000 0x000000d9 0x00000004 0x00000000 0x000000d9 0x00000004>;
  4751. clocks = <0x00000050>;
  4752. };
  4753. };
  4754. target-module@3a000 {
  4755. compatible = "ti,sysc-omap4", "ti,sysc";
  4756. ti,hwmods = "mailbox2";
  4757. reg = <0x0003a000 0x00000004 0x0003a010 0x00000004>;
  4758. reg-names = "rev", "sysc";
  4759. ti,sysc-mask = <0x00000001>;
  4760. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002>;
  4761. clocks = <0x00000063 0x00000028 0x00000000>;
  4762. clock-names = "fck";
  4763. #address-cells = <0x00000001>;
  4764. #size-cells = <0x00000001>;
  4765. ranges = <0x00000000 0x0003a000 0x00001000>;
  4766. mailbox@0 {
  4767. compatible = "ti,omap4-mailbox";
  4768. reg = <0x00000000 0x00000200>;
  4769. interrupts = <0x00000000 0x000000ed 0x00000004 0x00000000 0x000000ee 0x00000004 0x00000000 0x000000ef 0x00000004 0x00000000 0x000000f0 0x00000004>;
  4770. #mbox-cells = <0x00000001>;
  4771. ti,mbox-num-users = <0x00000004>;
  4772. ti,mbox-num-fifos = <0x0000000c>;
  4773. status = "disabled";
  4774. };
  4775. };
  4776. target-module@3c000 {
  4777. compatible = "ti,sysc-omap4", "ti,sysc";
  4778. ti,hwmods = "mailbox3";
  4779. reg = <0x0003c000 0x00000004 0x0003c010 0x00000004>;
  4780. reg-names = "rev", "sysc";
  4781. ti,sysc-mask = <0x00000001>;
  4782. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002>;
  4783. clocks = <0x00000063 0x00000030 0x00000000>;
  4784. clock-names = "fck";
  4785. #address-cells = <0x00000001>;
  4786. #size-cells = <0x00000001>;
  4787. ranges = <0x00000000 0x0003c000 0x00001000>;
  4788. mailbox@0 {
  4789. compatible = "ti,omap4-mailbox";
  4790. reg = <0x00000000 0x00000200>;
  4791. interrupts = <0x00000000 0x000000f1 0x00000004 0x00000000 0x000000f2 0x00000004 0x00000000 0x000000f3 0x00000004 0x00000000 0x000000f4 0x00000004>;
  4792. #mbox-cells = <0x00000001>;
  4793. ti,mbox-num-users = <0x00000004>;
  4794. ti,mbox-num-fifos = <0x0000000c>;
  4795. status = "disabled";
  4796. };
  4797. };
  4798. target-module@3e000 {
  4799. compatible = "ti,sysc-omap4", "ti,sysc";
  4800. ti,hwmods = "mailbox4";
  4801. reg = <0x0003e000 0x00000004 0x0003e010 0x00000004>;
  4802. reg-names = "rev", "sysc";
  4803. ti,sysc-mask = <0x00000001>;
  4804. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002>;
  4805. clocks = <0x00000063 0x00000038 0x00000000>;
  4806. clock-names = "fck";
  4807. #address-cells = <0x00000001>;
  4808. #size-cells = <0x00000001>;
  4809. ranges = <0x00000000 0x0003e000 0x00001000>;
  4810. mailbox@0 {
  4811. compatible = "ti,omap4-mailbox";
  4812. reg = <0x00000000 0x00000200>;
  4813. interrupts = <0x00000000 0x000000f5 0x00000004 0x00000000 0x000000f6 0x00000004 0x00000000 0x000000f7 0x00000004 0x00000000 0x000000f8 0x00000004>;
  4814. #mbox-cells = <0x00000001>;
  4815. ti,mbox-num-users = <0x00000004>;
  4816. ti,mbox-num-fifos = <0x0000000c>;
  4817. status = "disabled";
  4818. };
  4819. };
  4820. target-module@40000 {
  4821. compatible = "ti,sysc-omap4", "ti,sysc";
  4822. ti,hwmods = "mailbox5";
  4823. reg = <0x00040000 0x00000004 0x00040010 0x00000004>;
  4824. reg-names = "rev", "sysc";
  4825. ti,sysc-mask = <0x00000001>;
  4826. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002>;
  4827. clocks = <0x00000063 0x00000040 0x00000000>;
  4828. clock-names = "fck";
  4829. #address-cells = <0x00000001>;
  4830. #size-cells = <0x00000001>;
  4831. ranges = <0x00000000 0x00040000 0x00001000>;
  4832. mailbox@0 {
  4833. compatible = "ti,omap4-mailbox";
  4834. reg = <0x00000000 0x00000200>;
  4835. interrupts = <0x00000000 0x000000f9 0x00000004 0x00000000 0x000000fa 0x00000004 0x00000000 0x000000fb 0x00000004 0x00000000 0x000000fc 0x00000004>;
  4836. #mbox-cells = <0x00000001>;
  4837. ti,mbox-num-users = <0x00000004>;
  4838. ti,mbox-num-fifos = <0x0000000c>;
  4839. status = "okay";
  4840. mbox_ipu1_ipc3x {
  4841. ti,mbox-tx = <0x00000006 0x00000002 0x00000002>;
  4842. ti,mbox-rx = <0x00000004 0x00000002 0x00000002>;
  4843. status = "okay";
  4844. };
  4845. mbox_dsp1_ipc3x {
  4846. ti,mbox-tx = <0x00000005 0x00000002 0x00000002>;
  4847. ti,mbox-rx = <0x00000001 0x00000002 0x00000002>;
  4848. status = "okay";
  4849. };
  4850. };
  4851. };
  4852. target-module@42000 {
  4853. compatible = "ti,sysc-omap4", "ti,sysc";
  4854. ti,hwmods = "mailbox6";
  4855. reg = <0x00042000 0x00000004 0x00042010 0x00000004>;
  4856. reg-names = "rev", "sysc";
  4857. ti,sysc-mask = <0x00000001>;
  4858. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002>;
  4859. clocks = <0x00000063 0x00000048 0x00000000>;
  4860. clock-names = "fck";
  4861. #address-cells = <0x00000001>;
  4862. #size-cells = <0x00000001>;
  4863. ranges = <0x00000000 0x00042000 0x00001000>;
  4864. mailbox@0 {
  4865. compatible = "ti,omap4-mailbox";
  4866. reg = <0x00000000 0x00000200>;
  4867. interrupts = <0x00000000 0x000000fd 0x00000004 0x00000000 0x000000fe 0x00000004 0x00000000 0x000000ff 0x00000004 0x00000000 0x00000100 0x00000004>;
  4868. #mbox-cells = <0x00000001>;
  4869. ti,mbox-num-users = <0x00000004>;
  4870. ti,mbox-num-fifos = <0x0000000c>;
  4871. status = "okay";
  4872. mbox_ipu2_ipc3x {
  4873. ti,mbox-tx = <0x00000006 0x00000002 0x00000002>;
  4874. ti,mbox-rx = <0x00000004 0x00000002 0x00000002>;
  4875. status = "okay";
  4876. };
  4877. mbox_dsp2_ipc3x {
  4878. ti,mbox-tx = <0x00000005 0x00000002 0x00000002>;
  4879. ti,mbox-rx = <0x00000001 0x00000002 0x00000002>;
  4880. status = "okay";
  4881. };
  4882. };
  4883. };
  4884. target-module@44000 {
  4885. compatible = "ti,sysc-omap4", "ti,sysc";
  4886. ti,hwmods = "mailbox7";
  4887. reg = <0x00044000 0x00000004 0x00044010 0x00000004>;
  4888. reg-names = "rev", "sysc";
  4889. ti,sysc-mask = <0x00000001>;
  4890. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002>;
  4891. clocks = <0x00000063 0x00000050 0x00000000>;
  4892. clock-names = "fck";
  4893. #address-cells = <0x00000001>;
  4894. #size-cells = <0x00000001>;
  4895. ranges = <0x00000000 0x00044000 0x00001000>;
  4896. mailbox@0 {
  4897. compatible = "ti,omap4-mailbox";
  4898. reg = <0x00000000 0x00000200>;
  4899. interrupts = <0x00000000 0x00000101 0x00000004 0x00000000 0x00000102 0x00000004 0x00000000 0x00000103 0x00000004 0x00000000 0x00000104 0x00000004>;
  4900. #mbox-cells = <0x00000001>;
  4901. ti,mbox-num-users = <0x00000004>;
  4902. ti,mbox-num-fifos = <0x0000000c>;
  4903. status = "disabled";
  4904. };
  4905. };
  4906. target-module@46000 {
  4907. compatible = "ti,sysc-omap4", "ti,sysc";
  4908. ti,hwmods = "mailbox8";
  4909. reg = <0x00046000 0x00000004 0x00046010 0x00000004>;
  4910. reg-names = "rev", "sysc";
  4911. ti,sysc-mask = <0x00000001>;
  4912. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002>;
  4913. clocks = <0x00000063 0x00000058 0x00000000>;
  4914. clock-names = "fck";
  4915. #address-cells = <0x00000001>;
  4916. #size-cells = <0x00000001>;
  4917. ranges = <0x00000000 0x00046000 0x00001000>;
  4918. mailbox@0 {
  4919. compatible = "ti,omap4-mailbox";
  4920. reg = <0x00000000 0x00000200>;
  4921. interrupts = <0x00000000 0x00000105 0x00000004 0x00000000 0x00000106 0x00000004 0x00000000 0x00000107 0x00000004 0x00000000 0x00000108 0x00000004>;
  4922. #mbox-cells = <0x00000001>;
  4923. ti,mbox-num-users = <0x00000004>;
  4924. ti,mbox-num-fifos = <0x0000000c>;
  4925. status = "disabled";
  4926. };
  4927. };
  4928. target-module@48000 {
  4929. compatible = "ti,sysc";
  4930. status = "disabled";
  4931. #address-cells = <0x00000001>;
  4932. #size-cells = <0x00000001>;
  4933. ranges = <0x00000000 0x00048000 0x00001000>;
  4934. };
  4935. target-module@4a000 {
  4936. compatible = "ti,sysc";
  4937. status = "disabled";
  4938. #address-cells = <0x00000001>;
  4939. #size-cells = <0x00000001>;
  4940. ranges = <0x00000000 0x0004a000 0x00001000>;
  4941. };
  4942. target-module@4c000 {
  4943. compatible = "ti,sysc";
  4944. status = "disabled";
  4945. #address-cells = <0x00000001>;
  4946. #size-cells = <0x00000001>;
  4947. ranges = <0x00000000 0x0004c000 0x00001000>;
  4948. };
  4949. target-module@4e000 {
  4950. compatible = "ti,sysc";
  4951. status = "disabled";
  4952. #address-cells = <0x00000001>;
  4953. #size-cells = <0x00000001>;
  4954. ranges = <0x00000000 0x0004e000 0x00001000>;
  4955. };
  4956. target-module@50000 {
  4957. compatible = "ti,sysc";
  4958. status = "disabled";
  4959. #address-cells = <0x00000001>;
  4960. #size-cells = <0x00000001>;
  4961. ranges = <0x00000000 0x00050000 0x00001000>;
  4962. };
  4963. target-module@52000 {
  4964. compatible = "ti,sysc";
  4965. status = "disabled";
  4966. #address-cells = <0x00000001>;
  4967. #size-cells = <0x00000001>;
  4968. ranges = <0x00000000 0x00052000 0x00001000>;
  4969. };
  4970. target-module@54000 {
  4971. compatible = "ti,sysc";
  4972. status = "disabled";
  4973. #address-cells = <0x00000001>;
  4974. #size-cells = <0x00000001>;
  4975. ranges = <0x00000000 0x00054000 0x00001000>;
  4976. };
  4977. target-module@56000 {
  4978. compatible = "ti,sysc";
  4979. status = "disabled";
  4980. #address-cells = <0x00000001>;
  4981. #size-cells = <0x00000001>;
  4982. ranges = <0x00000000 0x00056000 0x00001000>;
  4983. };
  4984. target-module@58000 {
  4985. compatible = "ti,sysc";
  4986. status = "disabled";
  4987. #address-cells = <0x00000001>;
  4988. #size-cells = <0x00000001>;
  4989. ranges = <0x00000000 0x00058000 0x00001000>;
  4990. };
  4991. target-module@5a000 {
  4992. compatible = "ti,sysc";
  4993. status = "disabled";
  4994. #address-cells = <0x00000001>;
  4995. #size-cells = <0x00000001>;
  4996. ranges = <0x00000000 0x0005a000 0x00001000>;
  4997. };
  4998. target-module@5c000 {
  4999. compatible = "ti,sysc";
  5000. status = "disabled";
  5001. #address-cells = <0x00000001>;
  5002. #size-cells = <0x00000001>;
  5003. ranges = <0x00000000 0x0005c000 0x00001000>;
  5004. };
  5005. target-module@5e000 {
  5006. compatible = "ti,sysc-omap4", "ti,sysc";
  5007. ti,hwmods = "mailbox9";
  5008. reg = <0x0005e000 0x00000004 0x0005e010 0x00000004>;
  5009. reg-names = "rev", "sysc";
  5010. ti,sysc-mask = <0x00000001>;
  5011. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002>;
  5012. clocks = <0x00000063 0x00000060 0x00000000>;
  5013. clock-names = "fck";
  5014. #address-cells = <0x00000001>;
  5015. #size-cells = <0x00000001>;
  5016. ranges = <0x00000000 0x0005e000 0x00001000>;
  5017. mailbox@0 {
  5018. compatible = "ti,omap4-mailbox";
  5019. reg = <0x00000000 0x00000200>;
  5020. interrupts = <0x00000000 0x00000109 0x00000004 0x00000000 0x0000010a 0x00000004 0x00000000 0x0000010b 0x00000004 0x00000000 0x0000010c 0x00000004>;
  5021. #mbox-cells = <0x00000001>;
  5022. ti,mbox-num-users = <0x00000004>;
  5023. ti,mbox-num-fifos = <0x0000000c>;
  5024. status = "disabled";
  5025. };
  5026. };
  5027. target-module@60000 {
  5028. compatible = "ti,sysc-omap4", "ti,sysc";
  5029. ti,hwmods = "mailbox10";
  5030. reg = <0x00060000 0x00000004 0x00060010 0x00000004>;
  5031. reg-names = "rev", "sysc";
  5032. ti,sysc-mask = <0x00000001>;
  5033. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002>;
  5034. clocks = <0x00000063 0x00000068 0x00000000>;
  5035. clock-names = "fck";
  5036. #address-cells = <0x00000001>;
  5037. #size-cells = <0x00000001>;
  5038. ranges = <0x00000000 0x00060000 0x00001000>;
  5039. mailbox@0 {
  5040. compatible = "ti,omap4-mailbox";
  5041. reg = <0x00000000 0x00000200>;
  5042. interrupts = <0x00000000 0x0000010d 0x00000004 0x00000000 0x0000010e 0x00000004 0x00000000 0x0000010f 0x00000004 0x00000000 0x00000110 0x00000004>;
  5043. #mbox-cells = <0x00000001>;
  5044. ti,mbox-num-users = <0x00000004>;
  5045. ti,mbox-num-fifos = <0x0000000c>;
  5046. status = "disabled";
  5047. };
  5048. };
  5049. target-module@62000 {
  5050. compatible = "ti,sysc-omap4", "ti,sysc";
  5051. ti,hwmods = "mailbox11";
  5052. reg = <0x00062000 0x00000004 0x00062010 0x00000004>;
  5053. reg-names = "rev", "sysc";
  5054. ti,sysc-mask = <0x00000001>;
  5055. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002>;
  5056. clocks = <0x00000063 0x00000070 0x00000000>;
  5057. clock-names = "fck";
  5058. #address-cells = <0x00000001>;
  5059. #size-cells = <0x00000001>;
  5060. ranges = <0x00000000 0x00062000 0x00001000>;
  5061. mailbox@0 {
  5062. compatible = "ti,omap4-mailbox";
  5063. reg = <0x00000000 0x00000200>;
  5064. interrupts = <0x00000000 0x00000111 0x00000004 0x00000000 0x00000112 0x00000004 0x00000000 0x00000113 0x00000004 0x00000000 0x00000114 0x00000004>;
  5065. #mbox-cells = <0x00000001>;
  5066. ti,mbox-num-users = <0x00000004>;
  5067. ti,mbox-num-fifos = <0x0000000c>;
  5068. status = "disabled";
  5069. };
  5070. };
  5071. target-module@64000 {
  5072. compatible = "ti,sysc-omap4", "ti,sysc";
  5073. ti,hwmods = "mailbox12";
  5074. reg = <0x00064000 0x00000004 0x00064010 0x00000004>;
  5075. reg-names = "rev", "sysc";
  5076. ti,sysc-mask = <0x00000001>;
  5077. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002>;
  5078. clocks = <0x00000063 0x00000078 0x00000000>;
  5079. clock-names = "fck";
  5080. #address-cells = <0x00000001>;
  5081. #size-cells = <0x00000001>;
  5082. ranges = <0x00000000 0x00064000 0x00001000>;
  5083. mailbox@0 {
  5084. compatible = "ti,omap4-mailbox";
  5085. reg = <0x00000000 0x00000200>;
  5086. interrupts = <0x00000000 0x00000115 0x00000004 0x00000000 0x00000116 0x00000004 0x00000000 0x00000117 0x00000004 0x00000000 0x00000118 0x00000004>;
  5087. #mbox-cells = <0x00000001>;
  5088. ti,mbox-num-users = <0x00000004>;
  5089. ti,mbox-num-fifos = <0x0000000c>;
  5090. status = "disabled";
  5091. };
  5092. };
  5093. target-module@80000 {
  5094. compatible = "ti,sysc-omap4", "ti,sysc";
  5095. ti,hwmods = "usb_otg_ss1";
  5096. reg = <0x00080000 0x00000004 0x00080010 0x00000004>;
  5097. reg-names = "rev", "sysc";
  5098. ti,sysc-mask = <0x00010000>;
  5099. ti,sysc-midle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  5100. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  5101. clocks = <0x0000005a 0x000000d0 0x00000000>;
  5102. clock-names = "fck";
  5103. #address-cells = <0x00000001>;
  5104. #size-cells = <0x00000001>;
  5105. ranges = <0x00000000 0x00080000 0x00020000>;
  5106. omap_dwc3_1@0 {
  5107. compatible = "ti,dwc3";
  5108. reg = <0x00000000 0x00010000>;
  5109. interrupts = <0x00000000 0x00000048 0x00000004>;
  5110. #address-cells = <0x00000001>;
  5111. #size-cells = <0x00000001>;
  5112. utmi-mode = <0x00000002>;
  5113. ranges = <0x00000000 0x00000000 0x00020000>;
  5114. usb@10000 {
  5115. compatible = "snps,dwc3";
  5116. reg = <0x00010000 0x00017000>;
  5117. interrupts = <0x00000000 0x00000047 0x00000004 0x00000000 0x00000047 0x00000004 0x00000000 0x00000048 0x00000004>;
  5118. interrupt-names = "peripheral", "host", "otg";
  5119. phys = <0x000000b9 0x000000ba>;
  5120. phy-names = "usb2-phy", "usb3-phy";
  5121. maximum-speed = "super-speed";
  5122. dr_mode = "host";
  5123. snps,dis_u3_susphy_quirk;
  5124. snps,dis_u2_susphy_quirk;
  5125. };
  5126. };
  5127. };
  5128. target-module@c0000 {
  5129. compatible = "ti,sysc-omap4", "ti,sysc";
  5130. ti,hwmods = "usb_otg_ss2";
  5131. reg = <0x000c0000 0x00000004 0x000c0010 0x00000004>;
  5132. reg-names = "rev", "sysc";
  5133. ti,sysc-mask = <0x00010000>;
  5134. ti,sysc-midle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  5135. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  5136. clocks = <0x0000005a 0x00000020 0x00000000>;
  5137. clock-names = "fck";
  5138. #address-cells = <0x00000001>;
  5139. #size-cells = <0x00000001>;
  5140. ranges = <0x00000000 0x000c0000 0x00020000>;
  5141. omap_dwc3_2@0 {
  5142. compatible = "ti,dwc3";
  5143. reg = <0x00000000 0x00010000>;
  5144. interrupts = <0x00000000 0x00000057 0x00000004>;
  5145. #address-cells = <0x00000001>;
  5146. #size-cells = <0x00000001>;
  5147. utmi-mode = <0x00000002>;
  5148. ranges = <0x00000000 0x00000000 0x00020000>;
  5149. extcon = <0x000000bb>;
  5150. usb@10000 {
  5151. compatible = "snps,dwc3";
  5152. reg = <0x00010000 0x00017000>;
  5153. interrupts = <0x00000000 0x00000049 0x00000004 0x00000000 0x00000049 0x00000004 0x00000000 0x00000057 0x00000004>;
  5154. interrupt-names = "peripheral", "host", "otg";
  5155. phys = <0x000000bc>;
  5156. phy-names = "usb2-phy";
  5157. maximum-speed = "high-speed";
  5158. dr_mode = "peripheral";
  5159. snps,dis_u3_susphy_quirk;
  5160. snps,dis_u2_susphy_quirk;
  5161. snps,dis_metastability_quirk;
  5162. };
  5163. };
  5164. };
  5165. target-module@100000 {
  5166. compatible = "ti,sysc-omap4", "ti,sysc";
  5167. ti,hwmods = "usb_otg_ss3";
  5168. reg = <0x00100000 0x00000004 0x00100010 0x00000004>;
  5169. reg-names = "rev", "sysc";
  5170. ti,sysc-mask = <0x00010000>;
  5171. ti,sysc-midle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  5172. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  5173. clocks = <0x0000005a 0x00000028 0x00000000>;
  5174. clock-names = "fck";
  5175. #address-cells = <0x00000001>;
  5176. #size-cells = <0x00000001>;
  5177. ranges = <0x00000000 0x00100000 0x00020000>;
  5178. omap_dwc3_3@0 {
  5179. compatible = "ti,dwc3";
  5180. reg = <0x00000000 0x00010000>;
  5181. interrupts = <0x00000000 0x00000158 0x00000004>;
  5182. #address-cells = <0x00000001>;
  5183. #size-cells = <0x00000001>;
  5184. utmi-mode = <0x00000002>;
  5185. ranges = <0x00000000 0x00000000 0x00020000>;
  5186. status = "disabled";
  5187. usb@10000 {
  5188. compatible = "snps,dwc3";
  5189. reg = <0x00010000 0x00017000>;
  5190. interrupts = <0x00000000 0x00000058 0x00000004 0x00000000 0x00000058 0x00000004 0x00000000 0x00000158 0x00000004>;
  5191. interrupt-names = "peripheral", "host", "otg";
  5192. maximum-speed = "high-speed";
  5193. dr_mode = "otg";
  5194. snps,dis_u3_susphy_quirk;
  5195. snps,dis_u2_susphy_quirk;
  5196. };
  5197. };
  5198. };
  5199. target-module@140000 {
  5200. compatible = "ti,sysc-omap4", "ti,sysc";
  5201. ti,hwmods = "usb_otg_ss4";
  5202. reg = <0x00140000 0x00000004 0x00140010 0x00000004>;
  5203. reg-names = "rev", "sysc";
  5204. ti,sysc-mask = <0x00010000>;
  5205. ti,sysc-midle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  5206. ti,sysc-sidle = <0x00000000 0x00000001 0x00000002 0x00000003>;
  5207. clocks = <0x0000005a 0x00000030 0x00000000>;
  5208. clock-names = "fck";
  5209. #address-cells = <0x00000001>;
  5210. #size-cells = <0x00000001>;
  5211. ranges = <0x00000000 0x00140000 0x00020000>;
  5212. };
  5213. target-module@170000 {
  5214. compatible = "ti,sysc";
  5215. status = "disabled";
  5216. #address-cells = <0x00000001>;
  5217. #size-cells = <0x00000001>;
  5218. ranges = <0x00000000 0x00170000 0x00010000>;
  5219. };
  5220. target-module@190000 {
  5221. compatible = "ti,sysc";
  5222. status = "disabled";
  5223. #address-cells = <0x00000001>;
  5224. #size-cells = <0x00000001>;
  5225. ranges = <0x00000000 0x00190000 0x00010000>;
  5226. };
  5227. target-module@1b0000 {
  5228. compatible = "ti,sysc";
  5229. status = "disabled";
  5230. #address-cells = <0x00000001>;
  5231. #size-cells = <0x00000001>;
  5232. ranges = <0x00000000 0x001b0000 0x00010000>;
  5233. };
  5234. target-module@1d0000 {
  5235. compatible = "ti,sysc";
  5236. status = "disabled";
  5237. #address-cells = <0x00000001>;
  5238. #size-cells = <0x00000001>;
  5239. ranges = <0x00000000 0x001d0000 0x00010000>;
  5240. };
  5241. };
  5242. };
  5243. axi@0 {
  5244. compatible = "simple-bus";
  5245. #size-cells = <0x00000001>;
  5246. #address-cells = <0x00000001>;
  5247. ranges = <0x51000000 0x51000000 0x00003000 0x00000000 0x20000000 0x10000000>;
  5248. pcie@51000000 {
  5249. reg = <0x51000000 0x00002000 0x51002000 0x0000014c 0x00001000 0x00002000>;
  5250. reg-names = "rc_dbics", "ti_conf", "config";
  5251. interrupts = <0x00000000 0x000000e8 0x00000004 0x00000000 0x000000e9 0x00000004>;
  5252. #address-cells = <0x00000003>;
  5253. #size-cells = <0x00000002>;
  5254. device_type = "pci";
  5255. ranges = <0x81000000 0x00000000 0x00000000 0x00003000 0x00000000 0x00010000 0x82000000 0x00000000 0x20013000 0x00013000 0x00000000 0x0ffed000>;
  5256. bus-range = <0x00000000 0x000000ff>;
  5257. #interrupt-cells = <0x00000001>;
  5258. num-lanes = <0x00000001>;
  5259. linux,pci-domain = <0x00000000>;
  5260. ti,hwmods = "pcie1";
  5261. phys = <0x000000bd>;
  5262. phy-names = "pcie-phy0";
  5263. interrupt-map-mask = <0x00000000 0x00000000 0x00000000 0x00000007>;
  5264. interrupt-map = * 0x8301a924 [0x00000060];
  5265. ti,syscon-unaligned-access = <0x000000bf 0x00000014 0x00000001>;
  5266. status = "ok";
  5267. compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
  5268. gpios = <0x000000c0 0x00000008 0x00000001>;
  5269. interrupt-controller {
  5270. interrupt-controller;
  5271. #address-cells = <0x00000000>;
  5272. #interrupt-cells = <0x00000001>;
  5273. phandle = <0x000000be>;
  5274. };
  5275. };
  5276. pcie_ep@51000000 {
  5277. reg = <0x51000000 0x00000028 0x51002000 0x0000014c 0x51001000 0x00000028 0x00001000 0x10000000>;
  5278. reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
  5279. interrupts = <0x00000000 0x000000e8 0x00000004>;
  5280. num-lanes = <0x00000001>;
  5281. num-ib-windows = <0x00000004>;
  5282. num-ob-windows = <0x00000010>;
  5283. ti,hwmods = "pcie1";
  5284. phys = <0x000000bd>;
  5285. phy-names = "pcie-phy0";
  5286. ti,syscon-unaligned-access = <0x000000bf 0x00000014 0x00000001>;
  5287. status = "disabled";
  5288. compatible = "ti,dra746-pcie-ep", "ti,dra7-pcie-ep";
  5289. gpios = <0x000000c0 0x00000008 0x00000001>;
  5290. };
  5291. };
  5292. axi@1 {
  5293. compatible = "simple-bus";
  5294. #size-cells = <0x00000001>;
  5295. #address-cells = <0x00000001>;
  5296. ranges = <0x51800000 0x51800000 0x00003000 0x00000000 0x30000000 0x10000000>;
  5297. status = "disabled";
  5298. pcie@51800000 {
  5299. reg = <0x51800000 0x00002000 0x51802000 0x0000014c 0x00001000 0x00002000>;
  5300. reg-names = "rc_dbics", "ti_conf", "config";
  5301. interrupts = <0x00000000 0x00000163 0x00000004 0x00000000 0x00000164 0x00000004>;
  5302. #address-cells = <0x00000003>;
  5303. #size-cells = <0x00000002>;
  5304. device_type = "pci";
  5305. ranges = <0x81000000 0x00000000 0x00000000 0x00003000 0x00000000 0x00010000 0x82000000 0x00000000 0x30013000 0x00013000 0x00000000 0x0ffed000>;
  5306. bus-range = <0x00000000 0x000000ff>;
  5307. #interrupt-cells = <0x00000001>;
  5308. num-lanes = <0x00000001>;
  5309. linux,pci-domain = <0x00000001>;
  5310. ti,hwmods = "pcie2";
  5311. phys = <0x000000c1>;
  5312. phy-names = "pcie-phy0";
  5313. interrupt-map-mask = <0x00000000 0x00000000 0x00000000 0x00000007>;
  5314. interrupt-map = * 0x8301ade0 [0x00000060];
  5315. ti,syscon-unaligned-access = <0x000000bf 0x00000014 0x00000002>;
  5316. compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
  5317. interrupt-controller {
  5318. interrupt-controller;
  5319. #address-cells = <0x00000000>;
  5320. #interrupt-cells = <0x00000001>;
  5321. phandle = <0x000000c2>;
  5322. };
  5323. };
  5324. };
  5325. ocmcram@40300000 {
  5326. compatible = "mmio-sram";
  5327. reg = <0x40300000 0x00080000>;
  5328. ranges = <0x00000000 0x40300000 0x00080000>;
  5329. #address-cells = <0x00000001>;
  5330. #size-cells = <0x00000001>;
  5331. sram-hs@0 {
  5332. compatible = "ti,secure-ram";
  5333. reg = <0x00000000 0x00000000>;
  5334. };
  5335. };
  5336. ocmcram@40400000 {
  5337. status = "disabled";
  5338. compatible = "mmio-sram";
  5339. reg = <0x40400000 0x00100000>;
  5340. ranges = <0x00000000 0x40400000 0x00100000>;
  5341. #address-cells = <0x00000001>;
  5342. #size-cells = <0x00000001>;
  5343. };
  5344. ocmcram@40500000 {
  5345. status = "disabled";
  5346. compatible = "mmio-sram";
  5347. reg = <0x40500000 0x00100000>;
  5348. ranges = <0x00000000 0x40500000 0x00100000>;
  5349. #address-cells = <0x00000001>;
  5350. #size-cells = <0x00000001>;
  5351. };
  5352. bandgap@4a0021e0 {
  5353. reg = <0x4a0021e0 0x0000000c 0x4a00232c 0x0000000c 0x4a002380 0x0000002c 0x4a0023c0 0x0000003c 0x4a002564 0x00000008 0x4a002574 0x00000050>;
  5354. compatible = "ti,dra752-bandgap";
  5355. interrupts = <0x00000000 0x00000079 0x00000004>;
  5356. #thermal-sensor-cells = <0x00000001>;
  5357. phandle = <0x000000cc>;
  5358. };
  5359. dsp_system@40d00000 {
  5360. compatible = "syscon";
  5361. reg = <0x40d00000 0x00000100>;
  5362. phandle = <0x000000c5>;
  5363. };
  5364. padconf@4844a000 {
  5365. compatible = "ti,dra7-iodelay";
  5366. reg = <0x4844a000 0x00000d1c>;
  5367. #address-cells = <0x00000001>;
  5368. #size-cells = <0x00000000>;
  5369. #pinctrl-cells = <0x00000002>;
  5370. mmc1_iodelay_ddr_rev11_conf {
  5371. pinctrl-pin-array = * 0x8301b284 [0x000000cc];
  5372. };
  5373. mmc1_iodelay_ddr50_rev20_conf {
  5374. pinctrl-pin-array = * 0x8301b384 [0x000000cc];
  5375. phandle = <0x000000a3>;
  5376. };
  5377. mmc1_iodelay_sdr104_rev11_conf {
  5378. pinctrl-pin-array = * 0x8301b494 [0x00000084];
  5379. };
  5380. mmc1_iodelay_sdr104_rev20_conf {
  5381. pinctrl-pin-array = * 0x8301b54c [0x00000084];
  5382. phandle = <0x000000a5>;
  5383. };
  5384. mmc2_iodelay_hs200_rev11_conf {
  5385. pinctrl-pin-array = * 0x8301b614 [0x000000e4];
  5386. };
  5387. mmc2_iodelay_hs200_rev20_conf {
  5388. pinctrl-pin-array = * 0x8301b72c [0x000000e4];
  5389. };
  5390. mmc2_iodelay_ddr_3_3v_rev11_conf {
  5391. pinctrl-pin-array = * 0x8301b848 [0x0000015c];
  5392. };
  5393. mmc2_iodelay_ddr_1_8v_rev11_conf {
  5394. pinctrl-pin-array = * 0x8301b9dc [0x0000015c];
  5395. };
  5396. mmc3_iodelay_manual1_conf {
  5397. pinctrl-pin-array = * 0x8301bb68 [0x000000cc];
  5398. };
  5399. mmc4_iodelay_ds_rev11_conf {
  5400. pinctrl-pin-array = * 0x8301bc64 [0x000000cc];
  5401. };
  5402. mmc4_iodelay_ds_rev20_conf {
  5403. pinctrl-pin-array = * 0x8301bd60 [0x000000cc];
  5404. };
  5405. mmc4_iodelay_sdr12_hs_sdr25_rev11_conf {
  5406. pinctrl-pin-array = * 0x8301be68 [0x000000cc];
  5407. };
  5408. mmc4_iodelay_sdr12_hs_sdr25_rev20_conf {
  5409. pinctrl-pin-array = * 0x8301bf70 [0x000000cc];
  5410. };
  5411. };
  5412. edma@43300000 {
  5413. compatible = "ti,edma3-tpcc";
  5414. ti,hwmods = "tpcc";
  5415. reg = <0x43300000 0x00100000>;
  5416. reg-names = "edma3_cc";
  5417. interrupts = <0x00000000 0x00000169 0x00000004 0x00000000 0x00000168 0x00000004 0x00000000 0x00000167 0x00000004>;
  5418. interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint";
  5419. dma-requests = <0x00000040>;
  5420. #dma-cells = <0x00000002>;
  5421. ti,tptcs = <0x000000c3 0x00000007 0x000000c4 0x00000000>;
  5422. phandle = <0x0000000f>;
  5423. };
  5424. tptc@43400000 {
  5425. compatible = "ti,edma3-tptc";
  5426. ti,hwmods = "tptc0";
  5427. reg = <0x43400000 0x00100000>;
  5428. interrupts = <0x00000000 0x00000172 0x00000004>;
  5429. interrupt-names = "edma3_tcerrint";
  5430. phandle = <0x000000c3>;
  5431. };
  5432. tptc@43500000 {
  5433. compatible = "ti,edma3-tptc";
  5434. ti,hwmods = "tptc1";
  5435. reg = <0x43500000 0x00100000>;
  5436. interrupts = <0x00000000 0x00000173 0x00000004>;
  5437. interrupt-names = "edma3_tcerrint";
  5438. phandle = <0x000000c4>;
  5439. };
  5440. dmm@4e000000 {
  5441. compatible = "ti,omap5-dmm";
  5442. reg = <0x4e000000 0x00000800>;
  5443. interrupts = <0x00000000 0x0000006c 0x00000004>;
  5444. ti,hwmods = "dmm";
  5445. };
  5446. mmu@40d01000 {
  5447. compatible = "ti,dra7-dsp-iommu";
  5448. reg = <0x40d01000 0x00000100>;
  5449. interrupts = <0x00000000 0x00000017 0x00000004>;
  5450. ti,hwmods = "mmu0_dsp1";
  5451. #iommu-cells = <0x00000000>;
  5452. ti,syscon-mmuconfig = <0x000000c5 0x00000000>;
  5453. status = "disabled";
  5454. };
  5455. mmu@40d02000 {
  5456. compatible = "ti,dra7-dsp-iommu";
  5457. reg = <0x40d02000 0x00000100>;
  5458. interrupts = <0x00000000 0x00000091 0x00000004>;
  5459. ti,hwmods = "mmu1_dsp1";
  5460. #iommu-cells = <0x00000000>;
  5461. ti,syscon-mmuconfig = <0x000000c5 0x00000001>;
  5462. status = "disabled";
  5463. };
  5464. mmu@58882000 {
  5465. compatible = "ti,dra7-iommu";
  5466. reg = <0x58882000 0x00000100>;
  5467. interrupts = <0x00000000 0x0000018b 0x00000004>;
  5468. ti,hwmods = "mmu_ipu1";
  5469. #iommu-cells = <0x00000000>;
  5470. ti,iommu-bus-err-back;
  5471. status = "disabled";
  5472. };
  5473. mmu@55082000 {
  5474. compatible = "ti,dra7-iommu";
  5475. reg = <0x55082000 0x00000100>;
  5476. interrupts = <0x00000000 0x0000018c 0x00000004>;
  5477. ti,hwmods = "mmu_ipu2";
  5478. #iommu-cells = <0x00000000>;
  5479. ti,iommu-bus-err-back;
  5480. status = "disabled";
  5481. };
  5482. regulator-abb-mpu {
  5483. compatible = "ti,abb-v3";
  5484. regulator-name = "abb_mpu";
  5485. #address-cells = <0x00000000>;
  5486. #size-cells = <0x00000000>;
  5487. clocks = <0x00000011>;
  5488. ti,settling-time = <0x00000032>;
  5489. ti,clock-cycles = <0x00000010>;
  5490. reg = <0x4ae07ddc 0x00000004 0x4ae07de0 0x00000004 0x4ae06014 0x00000004 0x4a003b20 0x0000000c 0x4ae0c158 0x00000004>;
  5491. reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address";
  5492. ti,tranxdone-status-mask = <0x00000080>;
  5493. ti,ldovbb-override-mask = <0x00000400>;
  5494. ti,ldovbb-vset-mask = <0x0000001f>;
  5495. ti,abb_info = * 0x8301c734 [0x00000048];
  5496. phandle = <0x00000005>;
  5497. };
  5498. regulator-abb-ivahd {
  5499. compatible = "ti,abb-v3";
  5500. regulator-name = "abb_ivahd";
  5501. #address-cells = <0x00000000>;
  5502. #size-cells = <0x00000000>;
  5503. clocks = <0x00000011>;
  5504. ti,settling-time = <0x00000032>;
  5505. ti,clock-cycles = <0x00000010>;
  5506. reg = <0x4ae07e34 0x00000004 0x4ae07e24 0x00000004 0x4ae06010 0x00000004 0x4a0025cc 0x0000000c 0x4a002470 0x00000004>;
  5507. reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address";
  5508. ti,tranxdone-status-mask = <0x40000000>;
  5509. ti,ldovbb-override-mask = <0x00000400>;
  5510. ti,ldovbb-vset-mask = <0x0000001f>;
  5511. ti,abb_info = * 0x8301c8e8 [0x00000048];
  5512. };
  5513. regulator-abb-dspeve {
  5514. compatible = "ti,abb-v3";
  5515. regulator-name = "abb_dspeve";
  5516. #address-cells = <0x00000000>;
  5517. #size-cells = <0x00000000>;
  5518. clocks = <0x00000011>;
  5519. ti,settling-time = <0x00000032>;
  5520. ti,clock-cycles = <0x00000010>;
  5521. reg = <0x4ae07e30 0x00000004 0x4ae07e20 0x00000004 0x4ae06010 0x00000004 0x4a0025e0 0x0000000c 0x4a00246c 0x00000004>;
  5522. reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address";
  5523. ti,tranxdone-status-mask = <0x20000000>;
  5524. ti,ldovbb-override-mask = <0x00000400>;
  5525. ti,ldovbb-vset-mask = <0x0000001f>;
  5526. ti,abb_info = * 0x8301ca90 [0x00000048];
  5527. };
  5528. regulator-abb-gpu {
  5529. compatible = "ti,abb-v3";
  5530. regulator-name = "abb_gpu";
  5531. #address-cells = <0x00000000>;
  5532. #size-cells = <0x00000000>;
  5533. clocks = <0x00000011>;
  5534. ti,settling-time = <0x00000032>;
  5535. ti,clock-cycles = <0x00000010>;
  5536. reg = <0x4ae07de4 0x00000004 0x4ae07de8 0x00000004 0x4ae06010 0x00000004 0x4a003b08 0x0000000c 0x4ae0c154 0x00000004>;
  5537. reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address";
  5538. ti,tranxdone-status-mask = <0x10000000>;
  5539. ti,ldovbb-override-mask = <0x00000400>;
  5540. ti,ldovbb-vset-mask = <0x0000001f>;
  5541. ti,abb_info = * 0x8301cc30 [0x00000048];
  5542. };
  5543. spi@4b300000 {
  5544. compatible = "ti,dra7xxx-qspi";
  5545. reg = <0x4b300000 0x00000100 0x5c000000 0x04000000>;
  5546. reg-names = "qspi_base", "qspi_mmap";
  5547. syscon-chipselects = <0x00000009 0x00000558>;
  5548. #address-cells = <0x00000001>;
  5549. #size-cells = <0x00000000>;
  5550. ti,hwmods = "qspi";
  5551. clocks = <0x00000057 0x0000012c 0x00000019>;
  5552. clock-names = "fck";
  5553. num-cs = <0x00000004>;
  5554. interrupts = <0x00000000 0x00000157 0x00000004>;
  5555. status = "disabled";
  5556. };
  5557. sata@4a141100 {
  5558. compatible = "snps,dwc-ahci";
  5559. reg = <0x4a140000 0x00001100 0x4a141100 0x00000007>;
  5560. interrupts = <0x00000000 0x00000031 0x00000004>;
  5561. phys = <0x000000c6>;
  5562. phy-names = "sata-phy";
  5563. clocks = <0x0000005a 0x00000068 0x00000008>;
  5564. ti,hwmods = "sata";
  5565. ports-implemented = <0x00000001>;
  5566. status = "okay";
  5567. };
  5568. gpmc@50000000 {
  5569. compatible = "ti,am3352-gpmc";
  5570. ti,hwmods = "gpmc";
  5571. reg = <0x50000000 0x0000037c>;
  5572. interrupts = <0x00000000 0x0000000f 0x00000004>;
  5573. dmas = <0x000000b1 0x00000004 0x00000000>;
  5574. dma-names = "rxtx";
  5575. gpmc,num-cs = <0x00000008>;
  5576. gpmc,num-waitpins = <0x00000002>;
  5577. #address-cells = <0x00000002>;
  5578. #size-cells = <0x00000001>;
  5579. interrupt-controller;
  5580. #interrupt-cells = <0x00000002>;
  5581. gpio-controller;
  5582. #gpio-cells = <0x00000002>;
  5583. status = "disabled";
  5584. };
  5585. crossbar@4a002a48 {
  5586. compatible = "ti,irq-crossbar";
  5587. reg = <0x4a002a48 0x00000130>;
  5588. interrupt-controller;
  5589. interrupt-parent = <0x00000008>;
  5590. #interrupt-cells = <0x00000003>;
  5591. ti,max-irqs = <0x000000a0>;
  5592. ti,max-crossbar-sources = <0x00000190>;
  5593. ti,reg-size = <0x00000002>;
  5594. ti,irqs-reserved = <0x00000000 0x00000001 0x00000002 0x00000003 0x00000005 0x00000006 0x00000083 0x00000084>;
  5595. ti,irqs-skip = <0x0000000a 0x00000085 0x0000008b 0x0000008c>;
  5596. ti,irqs-safe-map = <0x00000000>;
  5597. phandle = <0x00000001>;
  5598. };
  5599. dss@58000000 {
  5600. compatible = "ti,dra7-dss";
  5601. status = "ok";
  5602. ti,hwmods = "dss_core";
  5603. syscon-pll-ctrl = <0x00000009 0x00000538>;
  5604. #address-cells = <0x00000001>;
  5605. #size-cells = <0x00000001>;
  5606. ranges;
  5607. reg = <0x58000000 0x00000080 0x58004054 0x00000004 0x58004300 0x00000020 0x58009054 0x00000004 0x58009300 0x00000020>;
  5608. reg-names = "dss", "pll1_clkctrl", "pll1", "pll2_clkctrl", "pll2";
  5609. clocks = <0x000000c7 0x00000000 0x00000008 0x000000c7 0x00000000 0x0000000c 0x000000c7 0x00000000 0x0000000d>;
  5610. clock-names = "fck", "video1_clk", "video2_clk";
  5611. vdda_video-supply = <0x000000c8>;
  5612. dispc@58001000 {
  5613. compatible = "ti,dra7-dispc";
  5614. reg = <0x58001000 0x00001000>;
  5615. interrupts = <0x00000000 0x00000014 0x00000004>;
  5616. ti,hwmods = "dss_dispc";
  5617. clocks = <0x000000c7 0x00000000 0x00000008>;
  5618. clock-names = "fck";
  5619. syscon-pol = <0x00000009 0x00000534>;
  5620. };
  5621. encoder@58060000 {
  5622. compatible = "ti,dra7-hdmi";
  5623. reg = <0x58040000 0x00000200 0x58040200 0x00000080 0x58040300 0x00000080 0x58060000 0x00019000>;
  5624. reg-names = "wp", "pll", "phy", "core";
  5625. interrupts = <0x00000000 0x00000060 0x00000004>;
  5626. status = "ok";
  5627. ti,hwmods = "dss_hdmi";
  5628. clocks = <0x000000c7 0x00000000 0x00000009 0x000000c7 0x00000000 0x0000000a>;
  5629. clock-names = "fck", "sys_clk";
  5630. dmas = <0x00000091 0x0000004c>;
  5631. dma-names = "audio_tx";
  5632. vdda-supply = <0x000000c9>;
  5633. port {
  5634. endpoint {
  5635. remote-endpoint = <0x000000ca>;
  5636. phandle = <0x000000d7>;
  5637. };
  5638. };
  5639. };
  5640. };
  5641. aes@4b500000 {
  5642. compatible = "ti,omap4-aes";
  5643. ti,hwmods = "aes1";
  5644. reg = <0x4b500000 0x000000a0>;
  5645. interrupts = <0x00000000 0x00000050 0x00000004>;
  5646. dmas = <0x000000b1 0x0000006f 0x00000000 0x000000b1 0x0000006e 0x00000000>;
  5647. dma-names = "tx", "rx";
  5648. clocks = <0x0000000a>;
  5649. clock-names = "fck";
  5650. };
  5651. aes@4b700000 {
  5652. compatible = "ti,omap4-aes";
  5653. ti,hwmods = "aes2";
  5654. reg = <0x4b700000 0x000000a0>;
  5655. interrupts = <0x00000000 0x0000003b 0x00000004>;
  5656. dmas = <0x000000b1 0x00000072 0x00000000 0x000000b1 0x00000071 0x00000000>;
  5657. dma-names = "tx", "rx";
  5658. clocks = <0x0000000a>;
  5659. clock-names = "fck";
  5660. };
  5661. des@480a5000 {
  5662. compatible = "ti,omap4-des";
  5663. ti,hwmods = "des";
  5664. reg = <0x480a5000 0x000000a0>;
  5665. interrupts = <0x00000000 0x0000004d 0x00000004>;
  5666. dmas = <0x00000091 0x00000075 0x00000091 0x00000074>;
  5667. dma-names = "tx", "rx";
  5668. clocks = <0x0000000a>;
  5669. clock-names = "fck";
  5670. };
  5671. sham@53100000 {
  5672. compatible = "ti,omap5-sham";
  5673. ti,hwmods = "sham";
  5674. reg = <0x4b101000 0x00000300>;
  5675. interrupts = <0x00000000 0x0000002e 0x00000004>;
  5676. dmas = <0x000000b1 0x00000077 0x00000000>;
  5677. dma-names = "rx";
  5678. clocks = <0x0000000a>;
  5679. clock-names = "fck";
  5680. };
  5681. opp-supply@4a003b20 {
  5682. compatible = "ti,omap5-opp-supply";
  5683. reg = <0x4a003b20 0x0000000c>;
  5684. ti,efuse-settings = <0x00102ca0 0x00000000 0x0011b340 0x00000004 0x00127690 0x00000008>;
  5685. ti,absolute-max-voltage-uv = <0x0016e360>;
  5686. };
  5687. dsp_system@41500000 {
  5688. compatible = "syscon";
  5689. reg = <0x41500000 0x00000100>;
  5690. phandle = <0x000000cb>;
  5691. };
  5692. omap_dwc3_4@48940000 {
  5693. compatible = "ti,dwc3";
  5694. ti,hwmods = "usb_otg_ss4";
  5695. reg = <0x48940000 0x00010000>;
  5696. interrupts = <0x00000000 0x0000015a 0x00000004>;
  5697. #address-cells = <0x00000001>;
  5698. #size-cells = <0x00000001>;
  5699. utmi-mode = <0x00000002>;
  5700. ranges;
  5701. status = "disabled";
  5702. usb@48950000 {
  5703. compatible = "snps,dwc3";
  5704. reg = <0x48950000 0x00017000>;
  5705. interrupts = <0x00000000 0x00000159 0x00000004 0x00000000 0x00000159 0x00000004 0x00000000 0x0000015a 0x00000004>;
  5706. interrupt-names = "peripheral", "host", "otg";
  5707. maximum-speed = "high-speed";
  5708. dr_mode = "otg";
  5709. };
  5710. };
  5711. mmu@41501000 {
  5712. compatible = "ti,dra7-dsp-iommu";
  5713. reg = <0x41501000 0x00000100>;
  5714. interrupts = <0x00000000 0x00000092 0x00000004>;
  5715. ti,hwmods = "mmu0_dsp2";
  5716. #iommu-cells = <0x00000000>;
  5717. ti,syscon-mmuconfig = <0x000000cb 0x00000000>;
  5718. status = "disabled";
  5719. };
  5720. mmu@41502000 {
  5721. compatible = "ti,dra7-dsp-iommu";
  5722. reg = <0x41502000 0x00000100>;
  5723. interrupts = <0x00000000 0x00000093 0x00000004>;
  5724. ti,hwmods = "mmu1_dsp2";
  5725. #iommu-cells = <0x00000000>;
  5726. ti,syscon-mmuconfig = <0x000000cb 0x00000001>;
  5727. status = "disabled";
  5728. };
  5729. };
  5730. thermal-zones {
  5731. cpu_thermal {
  5732. polling-delay-passive = <0x000000fa>;
  5733. polling-delay = <0x000001f4>;
  5734. thermal-sensors = <0x000000cc 0x00000000>;
  5735. coefficients = <0x00000000 0x000007d0>;
  5736. trips {
  5737. cpu_alert {
  5738. temperature = <0x00013880>;
  5739. hysteresis = <0x000007d0>;
  5740. type = "passive";
  5741. phandle = <0x000000cd>;
  5742. };
  5743. cpu_crit {
  5744. temperature = <0x00015f90>;
  5745. hysteresis = <0x000007d0>;
  5746. type = "critical";
  5747. };
  5748. cpu_alert1 {
  5749. temperature = <0x0000c350>;
  5750. hysteresis = <0x000007d0>;
  5751. type = "active";
  5752. phandle = <0x000000cf>;
  5753. };
  5754. };
  5755. cooling-maps {
  5756. map0 {
  5757. trip = <0x000000cd>;
  5758. cooling-device = <0x000000ce 0xffffffff 0xffffffff>;
  5759. };
  5760. map1 {
  5761. trip = <0x000000cf>;
  5762. cooling-device = <0x000000d0 0xffffffff 0xffffffff>;
  5763. };
  5764. };
  5765. };
  5766. gpu_thermal {
  5767. polling-delay-passive = <0x000000fa>;
  5768. polling-delay = <0x000001f4>;
  5769. thermal-sensors = <0x000000cc 0x00000001>;
  5770. coefficients = <0x00000000 0x000007d0>;
  5771. trips {
  5772. gpu_crit {
  5773. temperature = <0x00015f90>;
  5774. hysteresis = <0x000007d0>;
  5775. type = "critical";
  5776. };
  5777. };
  5778. };
  5779. core_thermal {
  5780. polling-delay-passive = <0x000000fa>;
  5781. polling-delay = <0x000001f4>;
  5782. thermal-sensors = <0x000000cc 0x00000002>;
  5783. coefficients = <0x00000000 0x000007d0>;
  5784. trips {
  5785. core_crit {
  5786. temperature = <0x00015f90>;
  5787. hysteresis = <0x000007d0>;
  5788. type = "critical";
  5789. };
  5790. };
  5791. };
  5792. dspeve_thermal {
  5793. polling-delay-passive = <0x000000fa>;
  5794. polling-delay = <0x000001f4>;
  5795. thermal-sensors = <0x000000cc 0x00000003>;
  5796. coefficients = <0x00000000 0x000007d0>;
  5797. trips {
  5798. dspeve_crit {
  5799. temperature = <0x00015f90>;
  5800. hysteresis = <0x000007d0>;
  5801. type = "critical";
  5802. };
  5803. };
  5804. };
  5805. iva_thermal {
  5806. polling-delay-passive = <0x000000fa>;
  5807. polling-delay = <0x000001f4>;
  5808. thermal-sensors = <0x000000cc 0x00000004>;
  5809. coefficients = <0x00000000 0x000007d0>;
  5810. trips {
  5811. iva_crit {
  5812. temperature = <0x00015f90>;
  5813. hysteresis = <0x000007d0>;
  5814. type = "critical";
  5815. };
  5816. };
  5817. };
  5818. board_thermal {
  5819. polling-delay-passive = <0x000004e2>;
  5820. polling-delay = <0x000005dc>;
  5821. thermal-sensors = <0x000000d1 0x00000000>;
  5822. trips {
  5823. board_alert {
  5824. temperature = <0x00009c40>;
  5825. hysteresis = <0x000007d0>;
  5826. type = "active";
  5827. phandle = <0x000000d2>;
  5828. };
  5829. board_crit {
  5830. temperature = <0x00019a28>;
  5831. hysteresis = <0x00000000>;
  5832. type = "critical";
  5833. };
  5834. };
  5835. cooling-maps {
  5836. map0 {
  5837. trip = <0x000000d2>;
  5838. cooling-device = <0x000000d0 0xffffffff 0xffffffff>;
  5839. };
  5840. };
  5841. };
  5842. };
  5843. pmu {
  5844. compatible = "arm,cortex-a15-pmu";
  5845. interrupt-parent = <0x00000008>;
  5846. interrupts = <0x00000000 0x00000083 0x00000004 0x00000000 0x00000084 0x00000004>;
  5847. };
  5848. memory@0 {
  5849. device_type = "memory";
  5850. reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
  5851. };
  5852. fixedregulator-vdd_3v3 {
  5853. compatible = "regulator-fixed";
  5854. regulator-name = "vdd_3v3";
  5855. vin-supply = <0x000000d3>;
  5856. regulator-min-microvolt = <0x00325aa0>;
  5857. regulator-max-microvolt = <0x00325aa0>;
  5858. phandle = <0x00000093>;
  5859. };
  5860. fixedregulator-aic_dvdd {
  5861. compatible = "regulator-fixed";
  5862. regulator-name = "aic_dvdd_fixed";
  5863. vin-supply = <0x00000093>;
  5864. regulator-min-microvolt = <0x001b7740>;
  5865. regulator-max-microvolt = <0x001b7740>;
  5866. phandle = <0x00000099>;
  5867. };
  5868. fixedregulator-vtt {
  5869. compatible = "regulator-fixed";
  5870. regulator-name = "vtt_fixed";
  5871. vin-supply = <0x000000d4>;
  5872. regulator-min-microvolt = <0x00325aa0>;
  5873. regulator-max-microvolt = <0x00325aa0>;
  5874. regulator-always-on;
  5875. regulator-boot-on;
  5876. enable-active-high;
  5877. gpio = <0x00000098 0x0000000b 0x00000000>;
  5878. };
  5879. leds {
  5880. compatible = "gpio-leds";
  5881. led0 {
  5882. label = "beagle-x15:usr0";
  5883. gpios = <0x00000098 0x00000009 0x00000000>;
  5884. linux,default-trigger = "heartbeat";
  5885. default-state = "off";
  5886. };
  5887. led1 {
  5888. label = "beagle-x15:usr1";
  5889. gpios = <0x00000098 0x00000008 0x00000000>;
  5890. linux,default-trigger = "cpu0";
  5891. default-state = "off";
  5892. };
  5893. led2 {
  5894. label = "beagle-x15:usr2";
  5895. gpios = <0x00000098 0x0000000e 0x00000000>;
  5896. linux,default-trigger = "mmc0";
  5897. default-state = "off";
  5898. };
  5899. led3 {
  5900. label = "beagle-x15:usr3";
  5901. gpios = <0x00000098 0x0000000f 0x00000000>;
  5902. linux,default-trigger = "disk-activity";
  5903. default-state = "off";
  5904. };
  5905. };
  5906. gpio_fan {
  5907. compatible = "gpio-fan";
  5908. gpios = <0x000000d5 0x00000002 0x00000000>;
  5909. gpio-fan,speed-map = <0x00000000 0x00000000 0x000032c8 0x00000001>;
  5910. #cooling-cells = <0x00000002>;
  5911. phandle = <0x000000d0>;
  5912. };
  5913. connector {
  5914. compatible = "hdmi-connector";
  5915. label = "hdmi";
  5916. type = "a";
  5917. port {
  5918. endpoint {
  5919. remote-endpoint = <0x000000d6>;
  5920. phandle = <0x000000d8>;
  5921. };
  5922. };
  5923. };
  5924. encoder {
  5925. compatible = "ti,tpd12s015";
  5926. gpios = <0x00000098 0x0000000a 0x00000000 0x000000c0 0x0000001e 0x00000000 0x00000098 0x0000000c 0x00000000>;
  5927. ports {
  5928. #address-cells = <0x00000001>;
  5929. #size-cells = <0x00000000>;
  5930. port@0 {
  5931. reg = <0x00000000>;
  5932. endpoint {
  5933. remote-endpoint = <0x000000d7>;
  5934. phandle = <0x000000ca>;
  5935. };
  5936. };
  5937. port@1 {
  5938. reg = <0x00000001>;
  5939. endpoint {
  5940. remote-endpoint = <0x000000d8>;
  5941. phandle = <0x000000d6>;
  5942. };
  5943. };
  5944. };
  5945. };
  5946. sound0 {
  5947. compatible = "simple-audio-card";
  5948. simple-audio-card,name = "BeagleBoard-X15";
  5949. simple-audio-card,widgets = "Line", "Line Out", "Line", "Line In";
  5950. simple-audio-card,routing = "Line Out", "LLOUT", "Line Out", "RLOUT", "MIC2L", "Line In", "MIC2R", "Line In";
  5951. simple-audio-card,format = "dsp_b";
  5952. simple-audio-card,bitclock-master = <0x000000d9>;
  5953. simple-audio-card,frame-master = <0x000000d9>;
  5954. simple-audio-card,bitclock-inversion;
  5955. simple-audio-card,cpu {
  5956. sound-dai = <0x000000da>;
  5957. };
  5958. simple-audio-card,codec {
  5959. sound-dai = <0x000000db>;
  5960. clocks = <0x000000dc>;
  5961. phandle = <0x000000d9>;
  5962. };
  5963. };
  5964. };
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