// Verilog test fixture created from schematic /home/ise/ShareFolder/Assign1/Assign1.sch - Mon Mar 30 07:49:17 2020

`timescale 1ns / 1ps

module Assign1_Assign1_sch_tb();

// Inputs
   reg X1;
   reg Y1;
   reg Y2;
   reg Y3;
   reg X2;
   reg X3;
   reg X4;

// Output
   wire A;
   wire B;
   wire C;
   wire D;
   wire E;
   wire F;
   wire G;

// Bidirs

// Instantiate the UUT
   Assign1 UUT (
		.X1(X1),
		.Y1(Y1),
		.Y2(Y2),
		.Y3(Y3),
		.X2(X2),
		.X3(X3),
		.X4(X4),
		.A(A),
		.B(B),
		.C(C),
		.D(D),
		.E(E),
		.F(F),
		.G(G)
   );
// Initialize Inputs
 //  `ifdef auto_init
      initial begin
			X1 = 1'b0;
			Y1 = 1'b0;
			Y2 = 1'b0;
			Y3 = 1'b0;
			X2 = 1'b0;
			X3 = 1'b0;
			X4 = 1'b0;
			#100;
			X1 = 1'b1;
			Y1 = 1'b1;
			#100;
			Y1 = 1'b0;
			Y2 = 1'b1;
			#100;
			Y2 = 1'b0;
			Y3 = 1'b1;
			#100;
			X1 = 1'b0;
			Y3 = 1'b0;
			X2 = 1'b1;
			Y1 = 1'b1;
			#100;
			Y1 = 1'b0;
			Y2 = 1'b1;
			#100;
			Y2 = 1'b0;
			Y3 = 1'b1;
			#100;
			X2 = 1'b0;
			Y3 = 1'b0;
			X3 = 1'b1;
			Y1 = 1'b1;
			#100;
			Y1 = 1'b0;
			Y2 = 1'b1;
			#100;
			Y2 = 1'b0;
			Y3 = 1'b1;
			#100;
			X3 = 1'b0;
			Y3 = 1'b0;
			X4 = 1'b1;
			Y1 = 1'b1;
			#100;
			Y1 = 1'b0;
			Y2 = 1'b1;
			#100;
			Y2 = 1'b0;
			Y3 = 1'b1;
			end
 //  `endif
endmodule