BCD Counter

`timescale 1ns / 1ps
module bcdCounter
    #(parameter width = 25, maxcount = 26_999_999)(
    input logic clk, reset,
    output logic [3:0] counter, //units place
    output logic [3:0] counter2,//tens place
    output logic [6:0] seg7, seg7_2//units and tens place respectively
    );
    logic [width-1:0] count;//enable generator count
    logic en, carry;
    always_ff @(posedge clk, posedge reset) //asynch reset
        if (reset) begin
            count <= 0;
            en <= 0;
        end
        else begin
            en <= 0;
            count <= count + 1;
            if (count <= maxcount) begin
                en <= 1; //enable generated
                count <= 0;
            end
        end

    always_ff @(posedge clk, posedge reset) //asynch reset
        begin
            if (reset) begin
                counter <= 4'b0000;
                carry <= 0;
            end
            else if (en) begin
                counter <= counter + 1;
                carry <= 0; //carry generated for only 1 clock cycle
                if (counter == 9) begin
                    counter <= 0;
                    carry <= 1; //carry generated
                end
            end
        end
    always_ff @(posedge carry, posedge reset) //asynch reset
        begin
            if (reset) begin
                counter2 <= 4'b0000;
            end
            else if (en) begin
                counter2 <= counter2 + 1;
                if (counter2 == 9) begin
                    counter2 <= 0;
                end
            end
        end
    always_comb //combinational design to connect counter output to 7 seg display
        begin
            case(counter)
            0: seg7 = 7'b011_1111;
            1: seg7 = 7'b000_0110;
            2: seg7 = 7'b101_1011;
            3: seg7 = 7'b100_1111;
            4: seg7 = 7'b110_0110;
            5: seg7 = 7'b110_1101;
            6: seg7 = 7'b111_1101;
            7: seg7 = 7'b000_0111;
            8: seg7 = 7'b111_1111;
            9: seg7 = 7'b110_1111;
            default: seg7 = 7'bxxx_xxxx;
            endcase
            case(counter2)
            0: seg7_2 = 7'b011_1111;
            1: seg7_2 = 7'b000_0110;
            2: seg7_2 = 7'b101_1011;
            3: seg7_2 = 7'b100_1111;
            4: seg7_2 = 7'b110_0110;
            5: seg7_2 = 7'b110_1101;
            6: seg7_2 = 7'b111_1101;
            7: seg7_2 = 7'b000_0111;
            8: seg7_2 = 7'b111_1111;
            9: seg7_2 = 7'b110_1111;
            default: seg7_2 = 7'bxxx_xxxx;
            endcase
        end
endmodule