module fetch(pc_in,instrReg,clk);
    input clk;
    input [31:0] pc_in;
    output reg [31:0] instrReg;
    wire [31:0] addr;
    wire pcOutput;
    wire [31:0] npc;
    reg pcOut;

    integer mem[99:0];
    initial begin
        pcOut <=0;
        mem[0] = 32'b00000001000010000100100000100000;
        mem[1] = 32'b00000001000010010101000000100010;
        mem[2] = 32'b00000001010010000101000000100100;
        mem[3] = 32'b00000001001010100101100000100101;
        mem[4] = 32'b00000001011010000110000000101010;
        mem[5] = 32'b10001110000010110000000000000100;
        mem[6] = 32'b10001110000010100000000000001000;
        mem[7] = 32'b10001110000100010000000000000000;
        mem[8] = 32'b10001111110101100000000000000000;
        mem[9] = 32'b10001110000110010000000000001100;
        mem[10] = 32'b10101100101111010000000000000100;
        mem[11] = 32'b10101111000001000000000000000000;
        mem[12] = 32'b10101100011111100000000000000100;
        mem[13] = 32'b10101110000100000000000000001000;
        mem[14] = 32'b10101100100000100000000000001100;
    end


    //PC
    always@(npc) begin
        pcOut <= npc;
    end
    //PC Increment
    always @(pc_in) begin
        pcOut <= pc_in + 1;
    end
    //Mux
    if (pc_in) begin
        //This is for branching
    end
    else begin

    end
    //Accessing memory
    always @(addr) begin
        instrReg <= mem[addr];
    end



endmodule