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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3.  
  4. entity ripple_adder is
  5.     port( input_1 : in STD_LOGIC_VECTOR(3 downto 0);
  6.           input_2 : in STD_LOGIC_VECTOR(3 downto 0);
  7.       o_sum : out STD_LOGIC_VECTOR(3 downto 0);
  8.       o_carry : out STD_LOGIC);
  9. end ripple_adder;
  10. architecture STRUCTURAL of ripple_adder is
  11. component full_adder is
  12.     port( i_carry: in STD_LOGIC;
  13.       i_1 : in STD_LOGIC;
  14.       i_2 : in STD_LOGIC;
  15.       o_sum : out STD_LOGIC;
  16.       o_carry : out STD_LOGIC);
  17. end component;
  18. signal t1,t2,t3,t4:  STD_LOGIC;
  19.  
  20. begin
  21. m1: full_adder port map(i_1=>input_1(0),i_2=>input_2(0),i_carry=>'0',o_sum=>o_sum(0),o_carry=>t1);
  22. m2: full_adder port map(i_1=>input_1(1),i_2=>input_2(1),i_carry=>t1,o_sum=>o_sum(1),o_carry=>t2);
  23. m3: full_adder port map(i_1=>input_1(2),i_2=>input_2(2),i_carry=>t2,o_sum=>o_sum(2),o_carry=>t3);
  24. m4: full_adder port map(i_1=>input_1(3),i_2=>input_2(3),i_carry=>t3,o_sum=>o_sum(3),o_carry=>t4);
  25. o_carry<=t4;
  26.  
  27. end STRUCTURAL;
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