library ieee;
use ieee.std_logic_1164.all;

entity ripple_adder is
    port( input_1 : in STD_LOGIC_VECTOR(3 downto 0);
          input_2 : in STD_LOGIC_VECTOR(3 downto 0);
	  o_sum : out STD_LOGIC_VECTOR(3 downto 0);
	  o_carry : out STD_LOGIC);
end ripple_adder;
architecture STRUCTURAL of ripple_adder is
component full_adder is
    port( i_carry: in STD_LOGIC;
	  i_1 : in STD_LOGIC;
	  i_2 : in STD_LOGIC;
	  o_sum : out STD_LOGIC;
	  o_carry : out STD_LOGIC);
end component;
signal t1,t2,t3,t4:  STD_LOGIC;

begin
m1: full_adder port map(i_1=>input_1(0),i_2=>input_2(0),i_carry=>'0',o_sum=>o_sum(0),o_carry=>t1);
m2: full_adder port map(i_1=>input_1(1),i_2=>input_2(1),i_carry=>t1,o_sum=>o_sum(1),o_carry=>t2);
m3: full_adder port map(i_1=>input_1(2),i_2=>input_2(2),i_carry=>t2,o_sum=>o_sum(2),o_carry=>t3);
m4: full_adder port map(i_1=>input_1(3),i_2=>input_2(3),i_carry=>t3,o_sum=>o_sum(3),o_carry=>t4);
o_carry<=t4;

end STRUCTURAL;