diff --git a/examples/litedram_gen.py b/examples/litedram_gen.py
index bb68fb2..ab8e6a2 100755
--- a/examples/litedram_gen.py
+++ b/examples/litedram_gen.py
@@ -71,6 +71,16 @@ def get_dram_ios(core_config):
         ),
     ]

+def get_csr_ios(aw, dw):
+    return [
+        ("csr_port", 0,
+            Subsignal("adr", Pins(aw)),
+            Subsignal("we", Pins(1)),
+            Subsignal("dat_w", Pins(dw)),
+            Subsignal("dat_r", Pins(dw))
+        ),
+    ]
+
 def get_native_user_port_ios(_id, aw, dw):
     return [
         ("user_port", _id,
@@ -197,6 +207,7 @@ class LiteDRAMCore(SoCSDRAM):
         SoCSDRAM.__init__(self, platform, sys_clk_freq,
             cpu_type=core_config["cpu"],
             l2_size=16*core_config["sdram_module_nb"],
+            csr_expose=(core_config["expose_csr_port"] == "yes"),
             **kwargs)

         # crg
@@ -234,6 +245,19 @@ class LiteDRAMCore(SoCSDRAM):
             platform.request("init_error").eq(self.ddrctrl.init_error.storage)
         ]

+        # CSR port
+        if core_config["expose_csr_port"] == "yes":
+            csr_port = self.csr # FIXME: this is probably incorrect -- GLS
+            platform.add_extension(get_csr_ios(self.csr_address_width,
+                                               self.csr_data_width))
+            _csr_port_io = platform.request("csr_port", 0)
+            self.comb += [
+                csr_port.adr.eq(_csr_port_io.adr),
+                csr_port.we.eq(_csr_port_io.we),
+                csr_port.dat_w.eq(_csr_port_io.dat_w),
+                _csr_port_io.dat_r.eq(csr_port.dat_w),
+            ]
+
         # user port
         self.comb += [
             platform.request("user_clk").eq(ClockSignal()),
diff --git a/examples/nexys4ddr_config.py b/examples/nexys4ddr_config.py
index efa597e..9c34002 100644
--- a/examples/nexys4ddr_config.py
+++ b/examples/nexys4ddr_config.py
@@ -3,7 +3,7 @@ from litedram.phy import A7DDRPHY

 core_config = {
     # General ------------------------------------------------------------------
-    "cpu":        "vexriscv",  # Type of CPU used for init/calib (vexriscv, lm32)
+    "cpu":        "None",  # Type of CPU used for init/calib (vexriscv, lm32)
     "speedgrade": -1,          # FPGA speedgrade
     "memtype":    "DDR2",      # DRAM type

@@ -24,7 +24,10 @@ core_config = {
     "cmd_buffer_depth": 16,    # Depth of the command buffer

     # User Ports ---------------------------------------------------------------
-    "user_ports_nb":       2,     # Number of user ports
+    "user_ports_nb":       1,     # Number of user ports
     "user_ports_type":     "axi", # Type of ports (axi, native)
-    "user_ports_id_width": 32,    # AXI identifier width
+    "user_ports_id_width": 4,    # AXI identifier width
+
+    # CSR Port -----------------------------------------------------------------
+    "expose_csr_port": "yes", # expose access to CSR (I/O) ports
 }