fir_tb.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 06/22/2021 04:41:03 PM
// Design Name:
// Module Name: fir_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module fir_tb(
    );
    parameter COEFF_WIDTH = 8, DATA_WIDTH = 16, OUT_WIDTH = 32, FIR_LENGTH = 16;

    reg clk, reset;
    reg coeff_en;
    reg signed [COEFF_WIDTH-1:0] coeff;
    reg data_en;
    reg signed [DATA_WIDTH-1:0] data;
    wire out_en;
    wire signed [OUT_WIDTH-1:0] out;

    fir #(.COEFF_WIDTH(COEFF_WIDTH), .DATA_WIDTH(DATA_WIDTH), .OUT_WIDTH(OUT_WIDTH), .FIR_LENGTH(FIR_LENGTH)) f0(
        .clk(clk), .reset(reset), .coeff_en(coeff_en), .coeff(coeff),
        .data_en(data_en), .data(data), .out_en(out_en), .out(out));

    always
        #5 clk <= ~clk;

    initial
    begin
        clk <= 1; reset <= 1; coeff_en <= 0; data_en <= 0; coeff <= 0; data <= 0;
        #10 reset <= 0;
        #0.01
        #10 coeff <= 1; coeff_en <= 1;
        #10 coeff <= 3; coeff_en <= 1;
        #10 coeff <= 9; coeff_en <= 1;
        #10 coeff <= 22; coeff_en <= 1;
        #10 coeff <= 44; coeff_en <= 1;
        #10 coeff <= 74; coeff_en <= 1;
        #10 coeff <= 105; coeff_en <= 1;
        #10 coeff <= 124; coeff_en <= 1;
        #10 coeff <= 124; coeff_en <= 1;
        #10 coeff <= 105; coeff_en <= 1;
        #10 coeff <= 74; coeff_en <= 1;
        #10 coeff <= 44; coeff_en <= 1;
        #10 coeff <= 22; coeff_en <= 1;
        #10 coeff <= 9; coeff_en <= 1;
        #10 coeff <= 3; coeff_en <= 1;
        #10 coeff <= 1; coeff_en <= 1;
        #10 data <= 0; coeff_en <= 0; data_en <= 1;
        #10 data <= 49; data_en <= 1;
        #10 data <= 90; data_en <= 1;
        #10 data <= 117; data_en <= 1;
        #10 data <= 127; data_en <= 1;
        #10 data <= 117; data_en <= 1;
        #10 data <= 90; data_en <= 1;
        #10 data <= 49; data_en <= 1;
        #10 data <= 0; data_en <= 1;
        #10 data <= -49; data_en <= 1;
        #10 data <= -90; data_en <= 1;
        #10 data <= -117; data_en <= 1;
        #10 data <= -127; data_en <= 1;
        #10 data <= -117; data_en <= 1;
        #10 data <= -90; data_en <= 1;
        #10 data <= -49; data_en <= 1;
        #10 data <= 0; data_en <= 1;
        #10 data <= 0; data_en <= 1;
        #10 data <= 0; data_en <= 1;
        #10 data <= 0; data_en <= 1;
        #10 data <= 0; data_en <= 1;
        #10 data <= 0; data_en <= 1;
        #10 data <= 0; data_en <= 1;
        #10 data <= 0; data_en <= 1;
        #10 data <= 0; data_en <= 1;
        #10 data <= 0; data_en <= 1;
        #10 data <= 0; data_en <= 1;
        #10 data <= 0; data_en <= 1;
        #10 data <= 0; data_en <= 1;
        #10 data <= 0; data_en <= 1;
        #10 data <= 0; data_en <= 1;
        #10 data_en <= 0;
        #50 $finish;
    end
endmodule