Advertisement
Benny1994

verilog testbench error v2

Sep 10th, 2023
1,081
0
Never
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
  1. `timescale 1ns/1ps
  2. module buttontoled_tb(input i_sw, output o_led);  
  3.         buttontoled UUT (.i_sw(ai_sw), .o_led(o_led));
  4.         i_sw = ~i_sw;
  5.         #10;
  6.        
  7.  
  8.  endmodule
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement