Bleh

module MEDIAN #(parameter SIZE = 8) (input [SIZE - 1:0] DI, input DSI, nRST, CLK, output [SIZE - 1:0] DO, output DSO);

    logic BYP, inCalc;
    MED #(.SIZE(SIZE)) med(.DI(DI), .DSI(DSI), .BYP(BYP), .CLK(CLK), .DO(DO));
    enum logic [3:0] { PXL1, PXL2, PXL3, PXL4, PXL5, PXL6, PXL7, PXL8, PXL9, CALC, DONE } state;

    always @(negedge nRST) begin
        BYP = 1'b0;
        DSO = 1'b0;
        state = PXL1;
        inCalc = 1'b0;
    end

    // Also happens to be synchronous
    always_ff @(posedge inCalc) begin
        for(bit [2:0] step = 0; step < 5; step++) begin
            BYP = 1'b0;
            for(bit [3:0] i = step; i < 8; i++)
                @(posedge CLK);
            BYP = 1'b1;
            if(step < 4)
                for(bit [2:0] i = 0; i < step + 1; i++)
                    @(posedge CLK);
        end
        BYP = 1'b0;
        state = DONE;
        inCalc = 1'b0;
    end

    // Synchronous state machine
    always @(posedge CLK) begin
        case(state)
        PXL1:
            if(DSI)
            begin
                DSO = 1'b0;
                state += 1;
            end
        // All pixels have been sent, calculate the thing now
        CALC:
            inCalc = 1'b1;
        DONE:
        begin
            DSO = 1'b1;
            state = PXL1;
        end
        default:
            state += 1;
            // loop through all the pixel states as the pixels get sent and then reach CALC
        endcase
    end

endmodule