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Radxa DTS

rvdr
May 20th, 2025 (edited)
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  1. /*
  2. * Allwinner Technology CO., Ltd. sun50iw10p1 platform
  3. *
  4. * modify base on juno.dts
  5. */
  6. /dts-v1/;
  7. #include <dt-bindings/interrupt-controller/arm-gic.h>
  8. #include <dt-bindings/gpio/gpio.h>
  9. /*#include "sun50iw10p1-pinctrl.dtsi"*/
  10. #include <dt-bindings/thermal/thermal.h>
  11. #include <media_bus_format.h>
  12. #include <drm/drm_mipi_dsi.h>
  13. #include <dt-bindings/phy/phy.h>
  14. #include <dt-bindings/clock/sun55iw3-ccu.h>
  15. #include <dt-bindings/clock/sun55iw3-rtc.h>
  16. #include <dt-bindings/clock/sun55iw3-r-ccu.h>
  17. #include <dt-bindings/clock/sun55iw3-mcu-ccu.h>
  18. #include <dt-bindings/clock/sun55iw3-displl-ccu.h>
  19. #include <dt-bindings/reset/sun55iw3-ccu.h>
  20. #include <dt-bindings/reset/sun55iw3-r-ccu.h>
  21. #include <dt-bindings/reset/sun55iw3-mcu-ccu.h>
  22. #include <dt-bindings/spi/sunxi-spi.h>
  23. #include <dt-bindings/clock/sunxi-ccu.h>
  24.  
  25. / {
  26. model = "sun55iw3";
  27. compatible = "allwinner,a523", "arm,sun55iw3p1";
  28. #address-cells = <2>;
  29. #size-cells = <2>;
  30.  
  31. aliases: aliases
  32. {
  33. nand0 = &nand0;
  34. twi6 = &twi6;
  35. disp = &disp;
  36. lcd0 = &lcd0;
  37. lcd1 = &lcd1;
  38. lcd2 = &lcd2;
  39. eink = &eink;
  40. hdmi = &hdmi;
  41. pwm = &pwm;
  42. pwm0 = &pwm0;
  43. pwm1 = &pwm1;
  44. pwm2 = &pwm2;
  45. pwm3 = &pwm3;
  46. pwm4 = &pwm4;
  47. pwm5 = &pwm5;
  48. s_pwm = &s_pwm;
  49. spwm0 = &spwm0;
  50. spi0 = &spi0;
  51. spif = &spif;
  52. edp0 = &edp0;
  53. ir0 = &s_cir0;
  54. pcie = &pcie;
  55. gpio0 = &pio;
  56. };
  57.  
  58. dcxo24M: dcxo24M_clk {
  59. #clock-cells = <0>;
  60. compatible = "fixed-clock";
  61. clock-frequency = <24000000>;
  62. clock-output-names = "dcxo24M";
  63. };
  64.  
  65. rc_16m: rc16m_clk {
  66. #clock-cells = <0>;
  67. compatible = "fixed-clock";
  68. clock-frequency = <16000000>;
  69. clock-accuracy = <300000000>;
  70. clock-output-names = "rc-16m";
  71. };
  72.  
  73. ccu: ccu@2001000 {
  74. compatible = "allwinner,sun55iw3-ccu";
  75. reg = <0x0 0x02001000 0x0 0x1000>;
  76. clocks = <&dcxo24M>, <&rtc_ccu CLK_OSC32K>, <&rc_16m>;
  77. clock-names = "hosc", "losc", "iosc";
  78. #clock-cells = <1>;
  79. #reset-cells = <1>;
  80. };
  81.  
  82. rtc_ccu: rtc_ccu@7090000 {
  83. compatible = "allwinner,sun55iw3-rtc-ccu";
  84. reg = <0x0 0x07090000 0x0 0x400>;
  85. #clock-cells = <1>;
  86. #reset-cells = <1>;
  87. };
  88.  
  89. soc: soc@29000000 {
  90. compatible = "simple-bus";
  91. #address-cells = <2>;
  92. #size-cells = <2>;
  93. r_pio: pinctrl@07022000 {
  94. gpio-controller;
  95. #gpio-cells = <3>;
  96. s_twi0_pins_a: s_twi0@0 {
  97. allwinner,pins = "PL0", "PL1";
  98. allwinner,pname = "s_twi0_scl", "s_twi0_sda";
  99. allwinner,function = "s_twi0";
  100. allwinner,muxsel = <2>;
  101. allwinner,drive = <1>;
  102. allwinner,pull = <1>;
  103. };
  104.  
  105. s_twi0_pins_b: s_twi0@1 {
  106. allwinner,pins = "PL0", "PL1";
  107. allwinner,function = "gpio_out";
  108. allwinner,muxsel = <1>;
  109. allwinner,drive = <1>;
  110. allwinner,pull = <1>;
  111. };
  112.  
  113. pcie_pwren_pins: pcie-pwren-pins {
  114. allwinner,pins = "PL11";
  115. allwinner,function = "gpio_out";
  116. allwinner,muxsel = <1>;
  117. allwinner,drive = <1>;
  118. allwinner,pull = <0>;
  119. };
  120. };
  121.  
  122. twi6: s_twi@0x07081400 {
  123. };
  124.  
  125. pck: power-controller@7060000 {
  126. compatible = "allwinner,a523-pck-600";
  127. reg = <0x00 0x7060000 0x00 0x8000>;
  128. #power-domain-cells = <1>;
  129. clocks = <&ccu 0x15>; /* CLK_PCK */
  130. resets = <&ccu 0x0c>; /* RST_PCK */
  131. clock-names = "pck";
  132. reset-names = "pck_rst";
  133. };
  134.  
  135. s_twi0@7081400 {
  136. #address-cells = <0x01>;
  137. #size-cells = <0x00>;
  138. compatible = "allwinner,sunxi-twi-v101";
  139. device_type = "twi6";
  140. reg = <0x00 0x7081400 0x00 0x400>;
  141. interrupts = <0x00 0xa4 0x04>;
  142. clocks = <0x19 0x13>;
  143. clock-names = "bus";
  144. resets = <0x19 0x0a>;
  145. dmas = <0x9e 0x09 0x9e 0x09>;
  146. dma-names = "tx\0rx";
  147. interrupt-parent = <&gic>;
  148. status = "okay";
  149. clock-frequency = <0x61a80>;
  150. pinctrl-0 = <0x9f>;
  151. pinctrl-1 = <0xa0>;
  152. pinctrl-names = "default\0sleep";
  153. twi_drv_used = <0x01>;
  154. no_suspend = <0x01>;
  155. phandle = <0x19b>;
  156.  
  157. axp1530@36 {
  158. compatible = "ext,axp1530";
  159. status = "okay";
  160. reg = <0x36>;
  161. wakeup-source;
  162. phandle = <0x19c>;
  163.  
  164. regulators {
  165.  
  166. dcdc1 {
  167. regulator-name = "axp1530-dcdc1";
  168. regulator-min-microvolt = <0x7a120>;
  169. regulator-max-microvolt = <0x33e140>;
  170. regulator-step-delay-us = <0x19>;
  171. regulator-final-delay-us = <0x32>;
  172. regulator-always-on;
  173. phandle = <0x08>;
  174. };
  175.  
  176. dcdc2 {
  177. regulator-name = "axp1530-dcdc2";
  178. regulator-min-microvolt = <0x7a120>;
  179. regulator-max-microvolt = <0x177fa0>;
  180. regulator-step-delay-us = <0x19>;
  181. regulator-final-delay-us = <0x32>;
  182. regulator-ramp-delay = <0xc8>;
  183. regulator-always-on;
  184. phandle = <0xa1>;
  185. };
  186.  
  187. dcdc3 {
  188. regulator-name = "axp1530-dcdc3";
  189. regulator-min-microvolt = <0x7a120>;
  190. regulator-max-microvolt = <0x1c1380>;
  191. regulator-step-delay-us = <0x19>;
  192. regulator-final-delay-us = <0x32>;
  193. regulator-always-on;
  194. phandle = <0xa2>;
  195. };
  196.  
  197. ldo1 {
  198. regulator-name = "axp1530-aldo1";
  199. regulator-min-microvolt = <0x7a120>;
  200. regulator-max-microvolt = <0x3567e0>;
  201. regulator-step-delay-us = <0x19>;
  202. regulator-final-delay-us = <0x32>;
  203. phandle = <0xa3>;
  204. };
  205.  
  206. ldo2 {
  207. regulator-name = "axp1530-dldo1";
  208. regulator-min-microvolt = <0x7a120>;
  209. regulator-max-microvolt = <0x3567e0>;
  210. regulator-step-delay-us = <0x19>;
  211. regulator-final-delay-us = <0x32>;
  212. phandle = <0xa4>;
  213. };
  214. };
  215.  
  216. virtual-ext-dcdc1 {
  217. compatible = "xpower-vregulator,ext-dcdc1";
  218. dcdc1-supply = <0x08>;
  219. };
  220.  
  221. virtual-ext-dcdc2 {
  222. compatible = "xpower-vregulator,ext-dcdc2";
  223. dcdc2-supply = <0xa1>;
  224. };
  225.  
  226. virtual-ext-dcdc3 {
  227. compatible = "xpower-vregulator,ext-dcdc3";
  228. dcdc3-supply = <0xa2>;
  229. };
  230.  
  231. virtual-ext-aldo1 {
  232. compatible = "xpower-vregulator,ext-aldo1";
  233. aldo1-supply = <0xa3>;
  234. };
  235.  
  236. virtual-ext-dldo1 {
  237. compatible = "xpower-vregulator,ext-dldo1";
  238. dldo1-supply = <0xa4>;
  239. };
  240. };
  241.  
  242. pmu@34 {
  243. compatible = "x-powers,axp2202";
  244. reg = <0x34>;
  245. status = "okay";
  246. interrupts = <0x00 0x08>;
  247. interrupt-parent = <0xa5>;
  248. x-powers,drive-vbus-en;
  249. pmu_reset = <0x00>;
  250. pmu_irq_wakeup = <0x01>;
  251. pmu_hot_shutdown = <0x01>;
  252. wakeup-source;
  253. phandle = <0x19d>;
  254.  
  255. usb_power_supply {
  256. compatible = "x-powers,axp2202-usb-power-supply";
  257. status = "okay";
  258. pmu_usbpc_vol = <0x11f8>;
  259. pmu_usbpc_cur = <0x1f4>;
  260. pmu_usbad_vol = <0xfa0>;
  261. pmu_usbad_cur = <0x9c4>;
  262. pmu_usb_typec_used = <0x01>;
  263. wakeup_usb_in;
  264. wakeup_usb_out;
  265. det_acin_supply = <0xa6>;
  266. pmu_acin_usbid_drv = <0x59 0x07 0x0c 0x01>;
  267. pmu_vbus_det_gpio = <0x59 0x07 0x0d 0x01>;
  268. phandle = <0xa7>;
  269. };
  270.  
  271. gpio_power_supply {
  272. compatible = "x-powers,gpio-supply";
  273. status = "disabled";
  274. pmu_acin_det_gpio = <0x59 0x07 0x0e 0x01>;
  275. det_usb_supply = <0xa7>;
  276. phandle = <0xa6>;
  277. };
  278.  
  279. powerkey@0 {
  280. status = "okay";
  281. compatible = "x-powers,axp2101-pek";
  282. pmu_powkey_off_time = <0x1770>;
  283. pmu_powkey_off_func = <0x00>;
  284. pmu_powkey_off_en = <0x01>;
  285. pmu_powkey_long_time = <0x5dc>;
  286. pmu_powkey_on_time = <0x200>;
  287. wakeup_rising;
  288. wakeup_falling;
  289. phandle = <0x19e>;
  290. };
  291.  
  292. regulators@0 {
  293. phandle = <0x19f>;
  294.  
  295. dcdc1 {
  296. regulator-name = "axp2202-dcdc1";
  297. regulator-min-microvolt = <0x7a120>;
  298. regulator-max-microvolt = <0x177fa0>;
  299. regulator-ramp-delay = <0xfa>;
  300. regulator-enable-ramp-delay = <0x3e8>;
  301. regulator-boot-on;
  302. regulator-always-on;
  303. phandle = <0x06>;
  304. };
  305.  
  306. dcdc2 {
  307. regulator-name = "axp2202-dcdc2";
  308. regulator-min-microvolt = <0x7a120>;
  309. regulator-max-microvolt = <0x33e140>;
  310. regulator-ramp-delay = <0xfa>;
  311. regulator-enable-ramp-delay = <0x3e8>;
  312. regulator-boot-on;
  313. regulator-always-on;
  314. phandle = <0x20>;
  315. };
  316.  
  317. dcdc3 {
  318. regulator-name = "axp2202-dcdc3";
  319. regulator-min-microvolt = <0x7a120>;
  320. regulator-max-microvolt = <0x1c1380>;
  321. regulator-ramp-delay = <0xfa>;
  322. regulator-enable-ramp-delay = <0x3e8>;
  323. regulator-always-on;
  324. phandle = <0xa9>;
  325. };
  326.  
  327. dcdc4 {
  328. regulator-name = "axp2202-dcdc4";
  329. regulator-min-microvolt = <0xf4240>;
  330. regulator-max-microvolt = <0x387520>;
  331. regulator-ramp-delay = <0xfa>;
  332. regulator-enable-ramp-delay = <0x3e8>;
  333. phandle = <0xaa>;
  334. };
  335.  
  336. rtcldo {
  337. regulator-name = "axp2202-rtcldo";
  338. regulator-min-microvolt = <0x1b7740>;
  339. regulator-max-microvolt = <0x1b7740>;
  340. regulator-boot-on;
  341. regulator-always-on;
  342. phandle = <0xab>;
  343. };
  344.  
  345. aldo1 {
  346. regulator-name = "axp2202-aldo1";
  347. regulator-min-microvolt = <0x7a120>;
  348. regulator-max-microvolt = <0x3567e0>;
  349. regulator-enable-ramp-delay = <0x3e8>;
  350. phandle = <0xac>;
  351. };
  352.  
  353. aldo2 {
  354. regulator-name = "axp2202-aldo2";
  355. regulator-min-microvolt = <0x7a120>;
  356. regulator-max-microvolt = <0x3567e0>;
  357. regulator-enable-ramp-delay = <0x3e8>;
  358. phandle = <0xad>;
  359. };
  360.  
  361. aldo3 {
  362. regulator-name = "axp2202-aldo3";
  363. regulator-min-microvolt = <0x7a120>;
  364. regulator-max-microvolt = <0x3567e0>;
  365. regulator-enable-ramp-delay = <0x3e8>;
  366. regulator-always-on;
  367. regulator-boot-on;
  368. phandle = <0xae>;
  369. };
  370.  
  371. aldo4 {
  372. regulator-name = "axp2202-aldo4";
  373. regulator-min-microvolt = <0x7a120>;
  374. regulator-max-microvolt = <0x3567e0>;
  375. regulator-enable-ramp-delay = <0x3e8>;
  376. regulator-always-on;
  377. regulator-boot-on;
  378. phandle = <0xaf>;
  379. };
  380.  
  381. bldo1 {
  382. regulator-name = "axp2202-bldo1";
  383. regulator-min-microvolt = <0x7a120>;
  384. regulator-max-microvolt = <0x3567e0>;
  385. regulator-enable-ramp-delay = <0x3e8>;
  386. regulator-boot-on;
  387. regulator-always-on;
  388. phandle = <0xb0>;
  389. };
  390.  
  391. bldo2 {
  392. regulator-name = "axp2202-bldo2";
  393. regulator-min-microvolt = <0x7a120>;
  394. regulator-max-microvolt = <0x3567e0>;
  395. regulator-enable-ramp-delay = <0x3e8>;
  396. regulator-boot-on;
  397. regulator-always-on;
  398. phandle = <0xb1>;
  399. };
  400.  
  401. bldo3 {
  402. regulator-name = "axp2202-bldo3";
  403. regulator-min-microvolt = <0x7a120>;
  404. regulator-max-microvolt = <0x3567e0>;
  405. regulator-enable-ramp-delay = <0x3e8>;
  406. regulator-boot-on;
  407. regulator-always-on;
  408. phandle = <0xb2>;
  409. };
  410.  
  411. bldo4 {
  412. regulator-name = "axp2202-bldo4";
  413. regulator-min-microvolt = <0x7a120>;
  414. regulator-max-microvolt = <0x3567e0>;
  415. regulator-enable-ramp-delay = <0x3e8>;
  416. phandle = <0xb3>;
  417. };
  418.  
  419. cldo1 {
  420. regulator-name = "axp2202-cldo1";
  421. regulator-min-microvolt = <0x7a120>;
  422. regulator-max-microvolt = <0x3567e0>;
  423. regulator-enable-ramp-delay = <0x3e8>;
  424. phandle = <0x4f>;
  425. };
  426.  
  427. cldo2 {
  428. regulator-name = "axp2202-cldo2";
  429. regulator-min-microvolt = <0x7a120>;
  430. regulator-max-microvolt = <0x3567e0>;
  431. regulator-enable-ramp-delay = <0x3e8>;
  432. phandle = <0xb4>;
  433. };
  434.  
  435. cldo3 {
  436. regulator-name = "axp2202-cldo3";
  437. regulator-min-microvolt = <0x7a120>;
  438. regulator-max-microvolt = <0x3567e0>;
  439. regulator-ramp-delay = <0x9c4>;
  440. regulator-enable-ramp-delay = <0x3e8>;
  441. regulator-boot-on;
  442. regulator-always-on;
  443. phandle = <0x5d>;
  444. };
  445.  
  446. cldo4 {
  447. regulator-name = "axp2202-cldo4";
  448. regulator-min-microvolt = <0x7a120>;
  449. regulator-max-microvolt = <0x3567e0>;
  450. regulator-enable-ramp-delay = <0x3e8>;
  451. regulator-boot-on;
  452. regulator-always-on;
  453. phandle = <0xb5>;
  454. };
  455.  
  456. cpusldo {
  457. regulator-name = "axp2202-cpusldo";
  458. regulator-min-microvolt = <0x7a120>;
  459. regulator-max-microvolt = <0x155cc0>;
  460. regulator-boot-on;
  461. regulator-always-on;
  462. phandle = <0xb6>;
  463. };
  464.  
  465. vmid {
  466. regulator-name = "axp2202-vmid";
  467. regulator-enable-ramp-delay = <0x3e8>;
  468. phandle = <0xa8>;
  469. };
  470.  
  471. drivevbus {
  472. regulator-name = "axp2202-drivevbus";
  473. regulator-enable-ramp-delay = <0x3e8>;
  474. drivevbusin-supply = <0xa8>;
  475. phandle = <0xb7>;
  476. };
  477. };
  478.  
  479. virtual-dcdc1 {
  480. compatible = "xpower-vregulator,dcdc1";
  481. dcdc1-supply = <0x06>;
  482. };
  483.  
  484. virtual-dcdc2 {
  485. compatible = "xpower-vregulator,dcdc2";
  486. dcdc2-supply = <0x20>;
  487. };
  488.  
  489. virtual-dcdc3 {
  490. compatible = "xpower-vregulator,dcdc3";
  491. dcdc3-supply = <0xa9>;
  492. };
  493.  
  494. virtual-dcdc4 {
  495. compatible = "xpower-vregulator,dcdc4";
  496. dcdc4-supply = <0xaa>;
  497. };
  498.  
  499. virtual-rtcldo {
  500. compatible = "xpower-vregulator,rtcldo";
  501. rtcldo-supply = <0xab>;
  502. };
  503.  
  504. virtual-aldo1 {
  505. compatible = "xpower-vregulator,aldo1";
  506. aldo1-supply = <0xac>;
  507. };
  508.  
  509. virtual-aldo2 {
  510. compatible = "xpower-vregulator,aldo2";
  511. aldo2-supply = <0xad>;
  512. };
  513.  
  514. virtual-aldo3 {
  515. compatible = "xpower-vregulator,aldo3";
  516. aldo3-supply = <0xae>;
  517. };
  518.  
  519. virtual-aldo4 {
  520. compatible = "xpower-vregulator,aldo4";
  521. aldo4-supply = <0xaf>;
  522. };
  523.  
  524. virtual-bldo1 {
  525. compatible = "xpower-vregulator,bldo1";
  526. bldo1-supply = <0xb0>;
  527. };
  528.  
  529. virtual-bldo2 {
  530. compatible = "xpower-vregulator,bldo2";
  531. bldo2-supply = <0xb1>;
  532. };
  533.  
  534. virtual-bldo3 {
  535. compatible = "xpower-vregulator,bldo3";
  536. bldo3-supply = <0xb2>;
  537. };
  538.  
  539. virtual-bldo4 {
  540. compatible = "xpower-vregulator,bldo4";
  541. bldo4-supply = <0xb3>;
  542. };
  543.  
  544. virtual-cldo1 {
  545. compatible = "xpower-vregulator,cldo1";
  546. cldo1-supply = <0x4f>;
  547. };
  548.  
  549. virtual-cldo2 {
  550. compatible = "xpower-vregulator,cldo2";
  551. cldo2-supply = <0xb4>;
  552. };
  553.  
  554. virtual-cldo3 {
  555. compatible = "xpower-vregulator,cldo3";
  556. cldo3-supply = <0x5d>;
  557. };
  558.  
  559. virtual-cldo4 {
  560. compatible = "xpower-vregulator,cldo4";
  561. cldo4-supply = <0xb5>;
  562. };
  563.  
  564. virtual-cpusldo {
  565. compatible = "xpower-vregulator,cpusldo";
  566. cpusldo-supply = <0xb6>;
  567. };
  568.  
  569. virtual-drivevbus {
  570. compatible = "xpower-vregulator,drivevbus";
  571. drivevbus-supply = <0xb7>;
  572. };
  573.  
  574. axp_gpio@0 {
  575. gpio-controller;
  576. #size-cells = <0x00>;
  577. #gpio-cells = <0x06>;
  578. status = "okay";
  579. phandle = <0x1a0>;
  580. };
  581. };
  582. };
  583.  
  584. s_twi1@7081800 {
  585. #address-cells = <0x01>;
  586. #size-cells = <0x00>;
  587. compatible = "allwinner,sunxi-twi-v101";
  588. device_type = "twi7";
  589. reg = <0x00 0x7081800 0x00 0x400>;
  590. interrupts = <0x00 0xa5 0x04>;
  591. clocks = <0x19 0x12>;
  592. clock-names = "bus";
  593. resets = <0x19 0x09>;
  594. dmas = <0x9e 0x0a 0x9e 0x0a>;
  595. dma-names = "tx\0rx";
  596. status = "disabled";
  597. phandle = <0x1a1>;
  598. };
  599.  
  600. s_twi2@7081c00 {
  601. #address-cells = <0x01>;
  602. #size-cells = <0x00>;
  603. compatible = "allwinner,sunxi-twi-v101";
  604. device_type = "twi8";
  605. reg = <0x00 0x7081c00 0x00 0x400>;
  606. interrupts = <0x00 0x9c 0x04>;
  607. clocks = <0x19 0x11>;
  608. clock-names = "bus";
  609. resets = <0x19 0x08>;
  610. dmas = <0x9e 0x0e 0x9e 0x0e>;
  611. dma-names = "tx\0rx";
  612. status = "disabled";
  613. phandle = <0x1a2>;
  614. };
  615.  
  616. power_sply:power_sply@4500000c {
  617. device_type = "power_sply";
  618.  
  619. };
  620.  
  621. power_delay:power_delay@4500024 {
  622. device_type = "power_delay";
  623. };
  624.  
  625. platform:platform@45000004 {
  626. device_type = "platform";
  627.  
  628. };
  629.  
  630. target:target@45000008 {
  631. device_type = "target";
  632. advert_enable = <1>;
  633.  
  634. };
  635.  
  636. charger0:charger0@45000010 {
  637. device_type = "charger0";
  638.  
  639. };
  640. card_boot:card_boot@45000014 {
  641. device_type = "card_boot";
  642. logical_start = <40960>;
  643. /* sprite_gpio0 = <&pio PC 7 1 0xffffffff 0xffffffff 1>; */
  644. sprite_gpio0 = <&pio 0x2 0x7 0x1 0xffffffff 0xffffffff 0x1>;
  645. };
  646.  
  647. gpio_bias:gpio_bias@45000018 {
  648. device_type = "gpio_bias";
  649. };
  650.  
  651. fastboot_key:fastboot_key@4500001c {
  652. device_type = "fastboot_key";
  653. key_max = <42>;
  654. key_min = <38>;
  655. };
  656.  
  657. recovery_key:recovery_key@45000020 {
  658. device_type = "recovery_key";
  659. key_max = <31>;
  660. key_min = <28>;
  661. };
  662.  
  663. adc_boot_recovery:adc_boot_recovery@45000024 {
  664. device_type = "adc_boot_recovery";
  665. };
  666.  
  667. reg_pfo: regulator_pfo {
  668. compatible = "regulator-fixed";
  669. regulator-name = "vcc-pfo";
  670. regulator-min-microvolt = <3300000>; /* 3.3V */
  671. regulator-max-microvolt = <3300000>;
  672. regulator-always-on;
  673. regulator-boot-on;
  674. };
  675.  
  676. reg_pc: regulator_pc {
  677. compatible = "regulator-fixed";
  678. regulator-name = "vcc-pc";
  679. regulator-min-microvolt = <3300000>; /* 3.3V */
  680. regulator-max-microvolt = <3300000>;
  681. regulator-always-on;
  682. regulator-boot-on;
  683. };
  684.  
  685. reg_pf: regulator_pf {
  686. compatible = "regulator-fixed";
  687. regulator-name = "vcc-pf";
  688. regulator-min-microvolt = <3300000>; /* 3.3V */
  689. regulator-max-microvolt = <3300000>;
  690. regulator-always-on;
  691. regulator-boot-on;
  692. };
  693.  
  694. reg_pg: regulator_pg {
  695. compatible = "regulator-fixed";
  696. regulator-name = "vcc-pg";
  697. regulator-min-microvolt = <3300000>; /* 3.3V */
  698. regulator-max-microvolt = <3300000>;
  699. regulator-always-on;
  700. regulator-boot-on;
  701. };
  702.  
  703. pio: pinctrl@0300b000 {
  704. compatible = "allwinner,sun55iw3-pinctrl";
  705. device_type = "pio";
  706. reg = <0x00 0x02000000 0x00 0x800>,
  707. <0x00 0x07010374 0x00 0x04>,
  708. <0x00 0x07010378 0x00 0x04>;
  709. reg-names = "pio", "i2s0", "dmic";
  710. gpio-controller;
  711. #size-cells = <0>;
  712. #gpio-cells = <6>;
  713. input-debounce = <0 0 0 0 0 0 0 0 0>;
  714. interrupt-controller;
  715. #interrupt-cells = <3>;
  716. clocks = <&ccu 0x1a>, <&ccu 0x30>, <&rtc_ccu 0x04>;
  717. clock-names = "apb", "hosc", "losc";
  718. vcc-pf-supply = <&reg_pf>;
  719. vcc-pg-supply = <&reg_pg>;
  720. vcc-pc-supply = <&reg_pc>;
  721. vcc-pfo-supply = <&reg_pfo>;
  722. phandle = <0x59>;
  723. status = "okay";
  724.  
  725. gma340_mux_pin: gma340-mux-pin {
  726. pins = "PB6";
  727. function = "gpio_out";
  728. drive-strength = <10>;
  729. bias-disable;
  730. power-source = <3300>;
  731. };
  732.  
  733. pcie0_pins_ph: pcie0-ph {
  734. pins = "PH11", "PH12", "PH19";
  735. function = "pcie0";
  736. drive-strength = <20>;
  737. bias-pull-up;
  738. power-source = <3300>;
  739. };
  740.  
  741. /* TODO: add jtag pin */
  742. sdc0_pins_d: sdc0@3 {
  743. pins = "PF2", "PF4";
  744. function = "uart0";
  745. drive-strength = <10>;
  746. bias-pull-up;
  747. power-source = <3300>;
  748. };
  749.  
  750. sdc0_pins_e: sdc0@4 {
  751. pins = "PF0", "PF1", "PF3",
  752. "PF5";
  753. function = "jtag";
  754. drive-strength = <10>;
  755. bias-pull-up;
  756. power-source = <3300>;
  757. };
  758.  
  759. sdc1_pins_a: sdc1@0 {
  760. pins = "PG1", "PG2",
  761. "PG3", "PG4", "PG5";
  762. function = "sdc1";
  763. drive-strength = <20>;
  764. bias-pull-up;
  765. };
  766.  
  767. sdc1_pins_b: sdc1@1 {
  768. pins = "PG0", "PG1", "PG2",
  769. "PG3", "PG4", "PG5";
  770. function = "gpio_in";
  771. };
  772.  
  773. sdc1_pins_c: sdc1@2 {
  774. pins = "PG0";
  775. function = "sdc1";
  776. drive-strength = <30>;
  777. bias-pull-up;
  778. };
  779.  
  780. sdc0_pins_a: sdc0@0 {
  781. };
  782.  
  783. sdc0_pins_b: sdc0@1 {
  784. };
  785.  
  786. sdc0_pins_c: sdc0@2 {
  787. };
  788.  
  789. sdc2_pins_a: sdc2@0 {
  790. };
  791.  
  792. sdc2_pins_b: sdc2@1 {
  793. };
  794.  
  795. sdc2_pins_c: sdc2@2 {
  796. };
  797.  
  798. nand0_pins_a: nand0@0 {
  799. };
  800.  
  801. nand0_pins_b: nand0@1 {
  802. };
  803.  
  804. nand0_pins_c: nand0@2 {
  805. };
  806.  
  807. spi0_pins_a: spi0@0 {
  808. };
  809.  
  810. spi0_pins_b: spi0@1 {
  811. };
  812.  
  813. spi0_pins_c: spi0@2 {
  814. };
  815.  
  816. spif_pins_a: spif@0 {
  817. };
  818.  
  819. spif_pins_b: spif@1 {
  820. };
  821.  
  822. spif_pins_c: spif@2 {
  823. };
  824.  
  825. lvds0_pins_a: lvds0@0 {
  826. };
  827. lvds0_pins_b: lvds0@1 {
  828. };
  829. lvds1_pins_a: lvds1@0 {
  830. };
  831. lvds1_pins_b: lvds1@1 {
  832. };
  833. lvds2_pins_a: lvds2@0 {
  834. };
  835. lvds2_pins_b: lvds2@1 {
  836. };
  837. lvds3_pins_a: lvds3@0 {
  838. };
  839. lvds3_pins_b: lvds3@1 {
  840. };
  841. lcd1_lvds2link_pins_a: lcd1_lvds2link@0 {
  842. };
  843. lcd1_lvds2link_pins_b: lcd1_lvds2link@1 {
  844. };
  845. lvds2link_pins_a: lvds2link@0 {
  846. };
  847. lvds2link_pins_b: lvds2link@1 {
  848. };
  849. rgb24_pins_a: rgb24@0 {
  850. };
  851. rgb24_pins_b: rgb24@1 {
  852. };
  853. rgb18_pins_a: rgb18@0 {
  854. };
  855. rgb18_pins_b: rgb18@1 {
  856. };
  857. eink_pins_a: eink@0 {
  858. };
  859. eink_pins_b: eink@1 {
  860. };
  861. dsi4lane_pins_a: dsi4lane@0{
  862. }; /* avoid compile err */
  863. dsi4lane_pins_b: dsi4lane@1{
  864. }; /* avoid compile err */
  865. dsi0_4lane_pins_a: dsi0_4lane@0 {
  866. };
  867. dsi0_4lane_pins_b: dsi0_4lane@1 {
  868. };
  869. dsi1_4lane_pins_a: dsi1_4lane@0 {
  870. };
  871. dsi1_4lane_pins_b: dsi1_4lane@1 {
  872. };
  873. pwm0_pin_a: pwm0@0 {
  874. };
  875.  
  876. pwm0_pin_b: pwm0@1 {
  877. };
  878.  
  879. pwm1_pin_a: pwm1@0 {
  880. };
  881.  
  882. pwm1_pin_b: pwm1@1 {
  883. };
  884.  
  885. pwm2_pin_a: pwm2@0 {
  886. };
  887.  
  888. pwm2_pin_b: pwm2@1 {
  889. };
  890.  
  891. pwm3_pin_a: pwm3@0 {
  892. };
  893.  
  894. pwm3_pin_b: pwm3@1 {
  895. };
  896.  
  897. pwm4_pin_a: pwm4@0 {
  898. };
  899.  
  900. pwm4_pin_b: pwm4@1 {
  901. };
  902.  
  903. pwm5_pin_a: pwm5@0 {
  904. };
  905.  
  906. pwm5_pin_b: pwm5@1 {
  907. };
  908.  
  909. spwm0_pin_active: spwm0@0 {
  910. };
  911.  
  912. spwm0_pin_sleep: spwm0@1 {
  913. };
  914.  
  915. s_cir0_pins_a: s_cir0@0 {
  916. };
  917. s_cir0_pins_b: s_cir0@1 {
  918. };
  919. };
  920.  
  921. ir_boot_recovery:ir_boot_recovery@45000024 {
  922. device_type = "ir_boot_recovery";
  923. };
  924.  
  925. key_boot_recovery:key_boot_recovery@45000028 {
  926. device_type = "key_boot_recovery";
  927. };
  928.  
  929. pwm: pwm@2000c00 {
  930. #pwm-cells = <0x3>;
  931. #clock-cells = <0>;
  932. #reset-cells = <0>;
  933. compatible = "allwinner,sunxi-pwm";
  934. reg = <0x0 0x02000c00 0x0 0x3ff>;
  935. pwm-number = <16>;
  936. pwm-base = <0x0>;
  937. sunxi-pwms = <&pwm0>, <&pwm1>, <&pwm2>, <&pwm3>, <&pwm4>,
  938. <&pwm5>, <&pwm6>, <&pwm7>, <&pwm8>, <&pwm9>,
  939. <&pwm10>, <&pwm11>, <&pwm12>, <&pwm13>,
  940. <&pwm14>, <&pwm15>;
  941. };
  942.  
  943. pwm0: pwm0@2000c10 {
  944. compatible = "allwinner,sunxi-pwm0";
  945. reg = <0x0 0x02000c10 0x0 0x4>;
  946. reg_base = <0x02000c00>;
  947. status = "disabled";
  948. };
  949.  
  950. pwm1: pwm1@2000c11 {
  951. compatible = "allwinner,sunxi-pwm1";
  952. reg = <0x0 0x02000c11 0x0 0x4>;
  953. reg_base = <0x02000c00>;
  954. status = "disabled";
  955. };
  956.  
  957. pwm2: pwm2@2000c12 {
  958. compatible = "allwinner,sunxi-pwm2";
  959. reg = <0x0 0x02000c12 0x0 0x4>;
  960. reg_base = <0x02000c00>;
  961. status = "disabled";
  962. };
  963.  
  964. pwm3: pwm3@2000c13 {
  965. compatible = "allwinner,sunxi-pwm3";
  966. reg = <0x0 0x02000c13 0x0 0x4>;
  967. reg_base = <0x02000c00>;
  968. status = "disabled";
  969. };
  970.  
  971. pwm4: pwm4@2000c14 {
  972. compatible = "allwinner,sunxi-pwm4";
  973. reg = <0x0 0x02000c14 0x0 0x4>;
  974. reg_base = <0x02000c00>;
  975. status = "disabled";
  976. };
  977.  
  978. pwm5: pwm5@2000c15 {
  979. compatible = "allwinner,sunxi-pwm5";
  980. reg = <0x0 0x02000c15 0x0 0x4>;
  981. reg_base = <0x02000c00>;
  982. status = "disabled";
  983. };
  984.  
  985. pwm6: pwm6@2000c16 {
  986. compatible = "allwinner,sunxi-pwm6";
  987. reg = <0x0 0x02000c16 0x0 0x4>;
  988. reg_base = <0x02000c00>;
  989. status = "disabled";
  990. };
  991.  
  992. pwm7: pwm7@2000c17 {
  993. compatible = "allwinner,sunxi-pwm7";
  994. reg = <0x0 0x02000c17 0x0 0x4>;
  995. reg_base = <0x02000c00>;
  996. status = "disabled";
  997. };
  998.  
  999. pwm8: pwm8@2000c18 {
  1000. compatible = "allwinner,sunxi-pwm8";
  1001. reg = <0x0 0x02000c18 0x0 0x4>;
  1002. reg_base = <0x02000c00>;
  1003. status = "disabled";
  1004. };
  1005.  
  1006. pwm9: pwm9@2000c19 {
  1007. compatible = "allwinner,sunxi-pwm9";
  1008. reg = <0x0 0x02000c19 0x0 0x4>;
  1009. reg_base = <0x02000c00>;
  1010. status = "disabled";
  1011. };
  1012.  
  1013. pwm10: pwm10@2000c1a {
  1014. compatible = "allwinner,sunxi-pwm10";
  1015. reg = <0x0 0x02000c1a 0x0 0x4>;
  1016. reg_base = <0x02000c00>;
  1017. status = "disabled";
  1018. };
  1019.  
  1020. pwm11: pwm11@2000c1b {
  1021. compatible = "allwinner,sunxi-pwm11";
  1022. reg = <0x0 0x02000c1b 0x0 0x4>;
  1023. reg_base = <0x02000c00>;
  1024. status = "disabled";
  1025. };
  1026.  
  1027. pwm12: pwm12@2000c1c {
  1028. compatible = "allwinner,sunxi-pwm12";
  1029. reg = <0x0 0x02000c1c 0x0 0x4>;
  1030. reg_base = <0x02000c00>;
  1031. status = "disabled";
  1032. };
  1033.  
  1034. pwm13: pwm13@2000c1d {
  1035. compatible = "allwinner,sunxi-pwm13";
  1036. reg = <0x0 0x02000c1d 0x0 0x4>;
  1037. reg_base = <0x02000c00>;
  1038. status = "disabled";
  1039. };
  1040.  
  1041. pwm14: pwm14@2000c1e {
  1042. compatible = "allwinner,sunxi-pwm14";
  1043. reg = <0x0 0x02000c1e 0x0 0x4>;
  1044. reg_base = <0x02000c00>;
  1045. status = "disabled";
  1046. };
  1047.  
  1048. pwm15: pwm15@2000c1f {
  1049. compatible = "allwinner,sunxi-pwm15";
  1050. reg = <0x0 0x02000c1f 0x0 0x4>;
  1051. reg_base = <0x02000c00>;
  1052. status = "disabled";
  1053. };
  1054.  
  1055. s_pwm: spwm@2051010 {
  1056. #pwm-cells = <0x3>;
  1057. compatible = "allwinner,sunxi-pwm";
  1058. reg = <0x0 0x02000c00 0x0 0x3ff>;
  1059. pwm-number = <4>;
  1060. pwm-base = <0x10>;
  1061. sunxi-pwms = <&spwm0>, <&spwm1>, <&spwm2>, <&spwm3>;
  1062. };
  1063.  
  1064. spwm0: spwm0@2051010 {
  1065. compatible = "allwinner,sunxi-pwm16";
  1066. pinctrl-names = "active", "sleep";
  1067. reg = <0x0 0x02051010 0x0 0x4>;
  1068. reg_base = <0x02051000>;
  1069. status = "disabled";
  1070. };
  1071.  
  1072. spwm1: spwm1@2051011 {
  1073. compatible = "allwinner,sunxi-pwm17";
  1074. pinctrl-names = "active", "sleep";
  1075. reg = <0x0 0x02051011 0x0 0x4>;
  1076. reg_base = <0x02051000>;
  1077. status = "disabled";
  1078. };
  1079.  
  1080. spwm2: spwm2@2051012 {
  1081. compatible = "allwinner,sunxi-pwm18";
  1082. pinctrl-names = "active", "sleep";
  1083. reg = <0x0 0x02051012 0x0 0x4>;
  1084. reg_base = <0x02051000>;
  1085. status = "disabled";
  1086. };
  1087.  
  1088. spwm3: spwm3@2051013 {
  1089. compatible = "allwinner,sunxi-pwm19";
  1090. pinctrl-names = "active", "sleep";
  1091. reg = <0x0 0x02051013 0x0 0x4>;
  1092. reg_base = <0x02051000>;
  1093. status = "disabled";
  1094. };
  1095.  
  1096. card0_boot_para:card0_boot_para@2 {
  1097. device_type = "card0_boot_para";
  1098. };
  1099.  
  1100. card2_boot_para:card2_boot_para@3 {
  1101. device_type = "card2_boot_para";
  1102. };
  1103.  
  1104. nand0:nand0@04011000 {
  1105. device_type = "nand0";
  1106. };
  1107.  
  1108.  
  1109. sdc2: sdmmc@4022000 {
  1110. compatible = "allwinner,sunxi-mmc-v4p6x";
  1111. device_type = "sdc2";
  1112. reg = <0x0 0x04022000 0x0 0x1000>;
  1113. interrupt-parent = <&gic>;
  1114. interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
  1115. clocks = <&dcxo24M>,
  1116. <&ccu CLK_PLL_PERI1_800M>,
  1117. <&ccu CLK_PLL_PERI1_600M>,
  1118. <&ccu CLK_SMHC2>,
  1119. <&ccu CLK_BUS_SMHC2>;
  1120. clock-names = "osc24m","pll_periph","pll_periph_2","mmc","ahb";
  1121. resets = <&ccu RST_BUS_SMHC2>;
  1122. reset-names = "rst";
  1123. pinctrl-names = "default","sleep";
  1124. pinctrl-0 = <&sdc2_pins_a &sdc2_pins_c>;
  1125. pinctrl-1 = <&sdc2_pins_b>;
  1126. bus-width = <8>;
  1127. req-page-count = <2>;
  1128. cap-mmc-highspeed;
  1129. cap-cmd23;
  1130. mmc-cache-ctrl;
  1131. non-removable;
  1132. /*max-frequency = <200000000>;*/
  1133. max-frequency = <50000000>;
  1134. cap-erase;
  1135. mmc-high-capacity-erase-size;
  1136. no-sdio;
  1137. no-sd;
  1138. /*-- speed mode --*/
  1139. /*sm0: DS26_SDR12*/
  1140. /*sm1: HSSDR52_SDR25*/
  1141. /*sm2: HSDDR52_DDR50*/
  1142. /*sm3: HS200_SDR104*/
  1143. /*sm4: HS400*/
  1144. /*-- frequency point --*/
  1145. /*f0: CLK_400K*/
  1146. /*f1: CLK_25M*/
  1147. /*f2: CLK_50M*/
  1148. /*f3: CLK_100M*/
  1149. /*f4: CLK_150M*/
  1150. /*f5: CLK_200M*/
  1151. ctl-spec-caps = <0x328>;
  1152. sdc_tm4_sm0_freq0 = <0>;
  1153. sdc_tm4_sm0_freq1 = <0>;
  1154. sdc_tm4_sm1_freq0 = <0x00000000>;
  1155. sdc_tm4_sm1_freq1 = <0>;
  1156. sdc_tm4_sm2_freq0 = <0x00000000>;
  1157. sdc_tm4_sm2_freq1 = <0>;
  1158. sdc_tm4_sm3_freq0 = <0x05000000>;
  1159. sdc_tm4_sm3_freq1 = <0x00000005>;
  1160. sdc_tm4_sm4_freq0 = <0x00050000>;
  1161. sdc_tm4_sm4_freq1 = <0x00000004>;
  1162. sdc_tm4_sm4_freq0_cmd = <0>;
  1163. sdc_tm4_sm4_freq1_cmd = <0>;
  1164.  
  1165. /*vmmc-supply = <&reg_3p3v>;*/
  1166. /*vqmc-supply = <&reg_3p3v>;*/
  1167. /*vdmc-supply = <&reg_3p3v>;*/
  1168. /*vmmc = "vcc-card";*/
  1169. /*vqmc = "";*/
  1170. /*vdmc = "";*/
  1171. /*sunxi-power-save-mode;*/
  1172. };
  1173.  
  1174. sdc0: sdmmc@4020000 {
  1175. compatible = "allwinner,sunxi-mmc-v5p3x";
  1176. device_type = "sdc0";
  1177. reg = <0x0 0x04020000 0x0 0x1000>;
  1178. interrupt-parent = <&gic>;
  1179. interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
  1180. clocks = <&dcxo24M>,
  1181. <&ccu CLK_PLL_PERI1_400M>,
  1182. <&ccu CLK_PLL_PERI1_300M>,
  1183. <&ccu CLK_SMHC0>,
  1184. <&ccu CLK_BUS_SMHC0>;
  1185. clock-names = "osc24m","pll_periph","pll_periph_2","mmc","ahb";
  1186. resets = <&ccu RST_BUS_SMHC0>;
  1187. reset-names = "rst";
  1188. pinctrl-names = "default","mmc_1v8","sleep","uart_jtag";
  1189. pinctrl-0 = <&sdc0_pins_a>;
  1190. pinctrl-1 = <&sdc0_pins_b>;
  1191. pinctrl-2 = <&sdc0_pins_c>;
  1192. pinctrl-3 = <&sdc0_pins_d &sdc0_pins_e>;
  1193. max-frequency = <50000000>;
  1194. bus-width = <4>;
  1195. req-page-count = <2>;
  1196. /*non-removable;*/
  1197. /*broken-cd;*/
  1198. /*cd-inverted*/
  1199. /*cd-gpios = <&pio PF 6 GPIO_ACTIVE_LOW>;*/
  1200. /* vmmc-supply = <&reg_3p3v>;*/
  1201. /* vqmc-supply = <&reg_3p3v>;*/
  1202. /* vdmc-supply = <&reg_3p3v>;*/
  1203. /*vmmc = "vcc-card";*/
  1204. /*vqmc = "";*/
  1205. /*vdmc = "";*/
  1206. cap-sd-highspeed;
  1207. cap-wait-while-busy;
  1208. /*sd-uhs-sdr50;*/
  1209. /*sd-uhs-ddr50;*/
  1210. /*cap-sdio-irq;*/
  1211. /*keep-power-in-suspend;*/
  1212. /*ignore-pm-notify;*/
  1213. /*sunxi-power-save-mode;*/
  1214. /*sunxi-dly-400k = <1 0 0 0>; */
  1215. /*sunxi-dly-26M = <1 0 0 0>;*/
  1216. /*sunxi-dly-52M = <1 0 0 0>;*/
  1217. /*sunxi-dly-52M-ddr4 = <1 0 0 0>;*/
  1218. /*sunxi-dly-52M-ddr8 = <1 0 0 0>;*/
  1219. /*sunxi-dly-104M = <1 0 0 0>;*/
  1220. /*sunxi-dly-208M = <1 0 0 0>;*/
  1221. /*sunxi-dly-104M-ddr = <1 0 0 0>;*/
  1222. /*sunxi-dly-208M-ddr = <1 0 0 0>;*/
  1223. ctl-spec-caps = <0x428>;
  1224. status = "okay";
  1225. };
  1226.  
  1227. sdc1: sdmmc@4021000 {
  1228. compatible = "allwinner,sunxi-mmc-v5p3x";
  1229. device_type = "sdc1";
  1230. reg = <0x0 0x04021000 0x0 0x1000>;
  1231. interrupt-parent = <&gic>;
  1232. interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
  1233. clocks = <&dcxo24M>,
  1234. <&ccu CLK_PLL_PERI1_400M>,
  1235. <&ccu CLK_PLL_PERI1_300M>,
  1236. <&ccu CLK_SMHC1>,
  1237. <&ccu CLK_BUS_SMHC1>;
  1238. clock-names = "osc24m","pll_periph","pll_periph_2","mmc","ahb";
  1239. resets = <&ccu RST_BUS_SMHC1>;
  1240. reset-names = "rst";
  1241. pinctrl-names = "default","sleep";
  1242. pinctrl-0 = <&sdc1_pins_a &sdc1_pins_c>;
  1243. pinctrl-1 = <&sdc1_pins_b>;
  1244. max-frequency = <50000000>;
  1245. bus-width = <4>;
  1246. /*broken-cd;*/
  1247. /*cd-inverted*/
  1248. /*cd-gpios = <&pio PG 6 6 1 2 0>;*/
  1249. /* vmmc-supply = <&reg_3p3v>;*/
  1250. /* vqmc-supply = <&reg_3p3v>;*/
  1251. /* vdmc-supply = <&reg_3p3v>;*/
  1252. /*vmmc = "vcc-card";*/
  1253. /*vqmc = "";*/
  1254. /*vdmc = "";*/
  1255. cap-sd-highspeed;
  1256. cap-sdio-irq;
  1257. ignore-pm-notify;
  1258. /*sd-uhs-sdr50;*/
  1259. /*sd-uhs-ddr50;*/
  1260. /*sd-uhs-sdr104;*/
  1261. /*cap-sdio-irq;*/
  1262. keep-power-in-suspend;
  1263. execute_tuning_in_kernel;
  1264. /*ignore-pm-notify;*/
  1265. /*sunxi-power-save-mode;*/
  1266. /*sunxi-dly-400k = <0xff 0xff 0xff 0xff 0xff 0xff>; */
  1267. /*sunxi-dly-26M = <0xff 0xff 0xff 0xff 0xff 0xff>;*/
  1268. /*sunxi-dly-52M = <0xff 0xff 0xff 0xff 0xff 0xff>;*/
  1269. /*sunxi-dly-52M-ddr4 = <0xff 0xff 0xff 0xff 0xff 0xff>;*/
  1270. /*sunxi-dly-52M-ddr8 = <0xff 0xff 0xff 0xff 0xff 0xff>;*/
  1271. /*sunxi-dly-104M = <0xff 0xff 0xff 0xff 0xff 0xff>;*/
  1272. /*sunxi-dly-208M = <0xff 0xff 0xff 0xff 0xff 0xff> ;*/
  1273. /*sunxi-dly-104M-ddr = <0xff 0xff 0xff 0xff 0xff 0xff>;*/
  1274. /*sunxi-dly-208M-ddr = <0xff 0xff 0xff 0xff 0xff 0xff>;*/
  1275. sunxi-dly-208M = <0xff 0x1 0xff 0xff 0xff 0xff>;
  1276. ctl-spec-caps = <0x428>;
  1277. status = "okay";
  1278. };
  1279.  
  1280. spi0: spi@4025000 {
  1281. #address-cells = <1>;
  1282. #size-cells = <0>;
  1283. compatible = "allwinner,sun55i-spi";
  1284. device_type = "spi0";
  1285. reg = <0x0 0x04025000 0x0 0x1000>;
  1286. //interrupts-extended = <&plic0 31 IRQ_TYPE_LEVEL_HIGH>;
  1287. //clocks = <&ccu CLK_PLL_PERIPH0>, <&ccu CLK_SPI0>, <&ccu CLK_BUS_SPI0>;
  1288. //clock-names = "pll", "mod", "bus";
  1289. //resets = <&ccu RST_BUS_SPI0>;
  1290. };
  1291.  
  1292. spif: spif@4f00000 {
  1293. #address-cells = <1>;
  1294. #size-cells = <0>;
  1295. compatible = "allwinner,sun55i-spif";
  1296. device_type = "spif";
  1297. reg = <0x0 0x047f0000 0x0 0x1000>;
  1298. //interrupts-extended = <&plic0 19 IRQ_TYPE_LEVEL_HIGH>;
  1299. //clocks = <&ccu CLK_PLL_PERIPH0>, <&ccu CLK_SPIF>, <&ccu CLK_BUS_SPIF>;
  1300. //clock-names = "pll", "mod", "bus";
  1301. //resets = <&ccu RST_BUS_SPIF>;
  1302. };
  1303.  
  1304. sunxi_drm: sunxi-drm {
  1305. compatible = "allwinner,sunxi-drm";
  1306. status = "okay";
  1307. route {
  1308. disp0_lvds0: disp0_lvds0 {
  1309. status = "disabled";
  1310. endpoints = <&disp0_out_tcon0 &tcon0_out_lvds0>;
  1311. logo,uboot = "bootlogo.bmp";
  1312. };
  1313. disp0_rgb0: disp0_rgb0 {
  1314. status = "disabled";
  1315. endpoints = <&disp0_out_tcon0 &tcon0_out_rgb0>;
  1316. logo,uboot = "bootlogo.bmp";
  1317. };
  1318. disp0_dsi0: disp0_dsi0 {
  1319. status = "disabled";
  1320. endpoints = <&disp0_out_tcon0 &tcon0_out_dsi0>;
  1321. logo,uboot = "bootlogo.bmp";
  1322. };
  1323. disp0_lvds1: disp0_lvds1 {
  1324. status = "disabled";
  1325. endpoints = <&disp0_out_tcon4 &tcon4_out_lvds1>;
  1326. logo,uboot = "bootlogo.bmp";
  1327. };
  1328. disp0_rgb1: disp0_rgb1 {
  1329. status = "disabled";
  1330. endpoints = <&disp0_out_tcon4 &tcon4_out_rgb1>;
  1331. logo,uboot = "bootlogo.bmp";
  1332. };
  1333. disp0_dsi1: disp0_dsi1 {
  1334. status = "disabled";
  1335. endpoints = <&disp0_out_tcon1 &tcon1_out_dsi1>;
  1336. logo,uboot = "bootlogo.bmp";
  1337. };
  1338. disp0_edp: disp0_edp {
  1339. status = "disabled";
  1340. endpoints = <&disp0_out_tcon3 &tcon3_out_edp>;
  1341. logo,uboot = "bootlogo.bmp";
  1342. };
  1343. disp0_hdmi: disp0_hdmi {
  1344. status = "disabled";
  1345. endpoints = <&disp0_out_tcon2 &tcon2_out_hdmi>;
  1346. logo,uboot = "bootlogo.bmp";
  1347. };
  1348. disp1_lvds0: disp1_lvds0 {
  1349. status = "disabled";
  1350. endpoints = <&disp1_out_tcon0 &tcon0_out_lvds0>;
  1351. logo,uboot = "bootlogo.bmp";
  1352. };
  1353. disp1_rgb0: disp1_rgb0 {
  1354. status = "disabled";
  1355. endpoints = <&disp1_out_tcon0 &tcon0_out_rgb0>;
  1356. logo,uboot = "bootlogo.bmp";
  1357. };
  1358. disp1_dsi0: disp1_dsi0 {
  1359. status = "disabled";
  1360. endpoints = <&disp1_out_tcon0 &tcon0_out_dsi0>;
  1361. logo,uboot = "bootlogo.bmp";
  1362. };
  1363. disp1_lvds1: disp1_lvds1 {
  1364. status = "disabled";
  1365. endpoints = <&disp1_out_tcon4 &tcon4_out_lvds1>;
  1366. logo,uboot = "bootlogo.bmp";
  1367. };
  1368. disp1_rgb1: disp1_rgb1 {
  1369. status = "disabled";
  1370. endpoints = <&disp1_out_tcon4 &tcon4_out_rgb1>;
  1371. logo,uboot = "bootlogo.bmp";
  1372. };
  1373. disp1_dsi1: disp1_dsi1 {
  1374. status = "disabled";
  1375. endpoints = <&disp1_out_tcon1 &tcon1_out_dsi1>;
  1376. logo,uboot = "bootlogo.bmp";
  1377. };
  1378. disp1_edp: disp1_edp {
  1379. status = "disabled";
  1380. endpoints = <&disp1_out_tcon3 &tcon3_out_edp>;
  1381. logo,uboot = "bootlogo.bmp";
  1382. };
  1383. disp1_hdmi: disp1_hdmi {
  1384. status = "disabled";
  1385. endpoints = <&disp1_out_tcon2 &tcon2_out_hdmi>;
  1386. logo,uboot = "bootlogo.bmp";
  1387. };
  1388. };
  1389. };
  1390.  
  1391. de: de@5000000 {
  1392. compatible = "allwinner,display-engine-v350";
  1393. reg = <0x0 0x5000000 0x0 0x400000>;
  1394. interrupt-parent = <&gic>;
  1395. interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
  1396. clocks = <&clk_de0>;
  1397. clock-names = "clk_de";
  1398. status = "okay";
  1399. ports {
  1400. #address-cells = <1>;
  1401. #size-cells = <0>;
  1402. disp0: port@0 {
  1403. reg = <0>;
  1404. #address-cells = <1>;
  1405. #size-cells = <0>;
  1406. disp0_out_tcon0: endpoint@0 {
  1407. reg = <0>;
  1408. remote-endpoint = <&tcon0_in_disp0>;
  1409. };
  1410. disp0_out_tcon1: endpoint@1 {
  1411. reg = <1>;
  1412. remote-endpoint = <&tcon1_in_disp0>;
  1413. };
  1414. disp0_out_tcon2: endpoint@2 {
  1415. reg = <2>;
  1416. remote-endpoint = <&tcon2_in_disp0>;
  1417. };
  1418. disp0_out_tcon3: endpoint@3 {
  1419. reg = <3>;
  1420. remote-endpoint = <&tcon3_in_disp0>;
  1421. };
  1422. disp0_out_tcon4: endpoint@4 {
  1423. reg = <4>;
  1424. remote-endpoint = <&tcon4_in_disp0>;
  1425. };
  1426. };
  1427. disp1: port@1 {
  1428. reg = <1>;
  1429. #address-cells = <1>;
  1430. #size-cells = <0>;
  1431. disp1_out_tcon0: endpoint@0 {
  1432. reg = <0>;
  1433. remote-endpoint = <&tcon0_in_disp1>;
  1434. };
  1435. disp1_out_tcon1: endpoint@1 {
  1436. reg = <1>;
  1437. remote-endpoint = <&tcon1_in_disp1>;
  1438. };
  1439. disp1_out_tcon2: endpoint@2 {
  1440. reg = <2>;
  1441. remote-endpoint = <&tcon2_in_disp1>;
  1442. };
  1443. disp1_out_tcon3: endpoint@3 {
  1444. reg = <3>;
  1445. remote-endpoint = <&tcon3_in_disp1>;
  1446. };
  1447. disp1_out_tcon4: endpoint@4 {
  1448. reg = <4>;
  1449. remote-endpoint = <&tcon4_in_disp1>;
  1450. };
  1451. };
  1452. };
  1453. };
  1454. vo0: vo0@5500000 {
  1455. compatible = "allwinner,tcon-top0";
  1456. reg = <0x0 0x05500000 0x0 0xfff>;
  1457. clocks = <&clk_dpss_top0>;
  1458. clock-names = "clk_bus_dpss_top";
  1459. status = "disabled";
  1460. };
  1461.  
  1462. vo1: vo1@5730000 {
  1463. compatible = "allwinner,tcon-top1";
  1464. reg = <0x0 0x05730000 0x0 0xfff>;
  1465. status = "disabled";
  1466. };
  1467.  
  1468. dlcd0: tcon0@5501000 {
  1469. compatible = "allwinner,tcon-lcd";
  1470. reg = <0x0 0x05501000 0x0 0x1000>;
  1471. interrupt-parent = <&gic>;
  1472. interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
  1473. clocks = <&clk_tcon_lcd0>;
  1474. clock-names = "clk_tcon";
  1475. top = <&vo0>;
  1476. status = "disabled";
  1477. ports {
  1478. #address-cells = <1>;
  1479. #size-cells = <0>;
  1480. tcon0_in: port@0 {
  1481. #address-cells = <1>;
  1482. #size-cells = <0>;
  1483. reg = <0>;
  1484. tcon0_in_disp0: endpoint@0 {
  1485. reg = <0>;
  1486. remote-endpoint = <&disp0_out_tcon0>;
  1487. };
  1488. tcon0_in_disp1: endpoint@1 {
  1489. reg = <1>;
  1490. remote-endpoint = <&disp1_out_tcon0>;
  1491. };
  1492. };
  1493. tcon0_out: port@1 {
  1494. #address-cells = <1>;
  1495. #size-cells = <0>;
  1496. reg = <1>;
  1497. tcon0_out_lvds0: endpoint@0 {
  1498. reg = <0>;
  1499. remote-endpoint = <&lvds0_in_tcon0>;
  1500. };
  1501. tcon0_out_dsi0: endpoint@1 {
  1502. reg = <1>;
  1503. remote-endpoint = <&dsi0_in_tcon0>;
  1504. };
  1505. tcon0_out_dsi1: endpoint@2 {
  1506. reg = <2>;
  1507. remote-endpoint = <&dsi1_in_tcon0>;
  1508. };
  1509. tcon0_out_rgb0: endpoint@3 {
  1510. reg = <3>;
  1511. remote-endpoint = <&rgb0_in_tcon0>;
  1512. };
  1513. };
  1514. };
  1515. };
  1516.  
  1517. dlcd1: tcon1@5502000 {
  1518. compatible = "allwinner,tcon-lcd";
  1519. reg = <0x0 0x05502000 0x0 0x1000>;
  1520. interrupt-parent = <&gic>;
  1521. interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
  1522. clocks = <&clk_tcon_lcd1>;
  1523. clock-names = "clk_tcon";
  1524. top = <&vo0>;
  1525. status = "disabled";
  1526. // TODO find panel used of_graph?
  1527. ports {
  1528. #address-cells = <1>;
  1529. #size-cells = <0>;
  1530. tcon1_in: port@0 {
  1531. reg = <0>;
  1532. #address-cells = <1>;
  1533. #size-cells = <0>;
  1534. tcon1_in_disp0: endpoint@0 {
  1535. reg = <0>;
  1536. remote-endpoint = <&disp0_out_tcon1>;
  1537. };
  1538. tcon1_in_disp1: endpoint@1 {
  1539. reg = <1>;
  1540. remote-endpoint = <&disp1_out_tcon1>;
  1541. };
  1542. };
  1543. tcon1_out: port@1 {
  1544. #address-cells = <1>;
  1545. #size-cells = <0>;
  1546. reg = <1>;
  1547. tcon1_out_dsi1: endpoint@0 {
  1548. reg = <0>;
  1549. remote-endpoint = <&dsi1_in_tcon1>;
  1550. };
  1551. };
  1552. };
  1553. };
  1554.  
  1555. dlcd2: tcon4@5731000 {
  1556. compatible = "allwinner,tcon-lcd";
  1557. reg = <0x0 0x05731000 0x0 0x1000>;
  1558. interrupt-parent = <&gic>;
  1559. interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
  1560. clocks = <&clk_tcon_lcd2>;
  1561. clock-names = "clk_tcon";
  1562. top = <&vo1>;
  1563. status = "disabled";
  1564. ports {
  1565. #address-cells = <1>;
  1566. #size-cells = <0>;
  1567. tcon4_in: port@0 {
  1568. #address-cells = <1>;
  1569. #size-cells = <0>;
  1570. reg = <0>;
  1571. tcon4_in_disp0: endpoint@0 {
  1572. reg = <0>;
  1573. remote-endpoint = <&disp0_out_tcon4>;
  1574. };
  1575. tcon4_in_disp1: endpoint@1 {
  1576. reg = <1>;
  1577. remote-endpoint = <&disp1_out_tcon4>;
  1578. };
  1579. };
  1580. tcon4_out: port@1 {
  1581. #address-cells = <1>;
  1582. #size-cells = <0>;
  1583. reg = <1>;
  1584. tcon4_out_lvds1: endpoint@0 {
  1585. reg = <0>;
  1586. remote-endpoint = <&lvds1_in_tcon4>;
  1587. };
  1588. tcon4_out_rgb1: endpoint@1 {
  1589. reg = <1>;
  1590. remote-endpoint = <&rgb1_in_tcon4>;
  1591. };
  1592. };
  1593. };
  1594. };
  1595.  
  1596. lvds0: lvds0@0001000 {
  1597. compatible = "allwinner,lvds0";
  1598. /* resets = <&ccu RST_BUS_LVDS0>;
  1599. reset-names = "rst_bus_lvds";*/
  1600. clocks = <&clk_lvds0>;
  1601. clock-names = "clk_lvds";
  1602. phys = <&dsi0combophy>, <&dsi1combophy>;
  1603. phy-names = "combophy0", "combophy1";
  1604. status = "disabled";
  1605.  
  1606. ports {
  1607. #address-cells = <1>;
  1608. #size-cells = <0>;
  1609. lvds0_in: port@0 {
  1610. #address-cells = <1>;
  1611. #size-cells = <0>;
  1612. reg = <0>;
  1613. lvds0_in_tcon0: endpoint@0 {
  1614. reg = <0>;
  1615. remote-endpoint = <&tcon0_out_lvds0>;
  1616. };
  1617. };
  1618. };
  1619. };
  1620.  
  1621. lvds1: lvds1@0001000 {
  1622. compatible = "allwinner,lvds1";
  1623. reg = <0>;
  1624. clocks = <&clk_lvds1>;
  1625. clock-names = "clk_lvds";
  1626. status = "disabled";
  1627.  
  1628. ports {
  1629. #address-cells = <1>;
  1630. #size-cells = <0>;
  1631. lvds1_in: port@0 {
  1632. #address-cells = <1>;
  1633. #size-cells = <0>;
  1634. reg = <0>;
  1635. lvds1_in_tcon4: endpoint@0 {
  1636. reg = <0>;
  1637. remote-endpoint = <&tcon4_out_lvds1>;
  1638. };
  1639. };
  1640. };
  1641. };
  1642.  
  1643. rgb0: rgb0@0001000 {
  1644. compatible = "allwinner,rgb0";
  1645. reg = <0>;
  1646. status = "disabled";
  1647.  
  1648. ports {
  1649. #address-cells = <1>;
  1650. #size-cells = <0>;
  1651. rgb0_in: port@0 {
  1652. #address-cells = <1>;
  1653. #size-cells = <0>;
  1654. reg = <0>;
  1655. rgb0_in_tcon0: endpoint@0 {
  1656. reg = <0>;
  1657. remote-endpoint = <&tcon0_out_rgb0>;
  1658. };
  1659. };
  1660. };
  1661. };
  1662.  
  1663. rgb1: rgb1@0001000 {
  1664. compatible = "allwinner,rgb1";
  1665. reg = <0>;
  1666. status = "disabled";
  1667.  
  1668. ports {
  1669. #address-cells = <1>;
  1670. #size-cells = <0>;
  1671. rgb1_in: port@0 {
  1672. #address-cells = <1>;
  1673. #size-cells = <0>;
  1674. reg = <0>;
  1675. rgb1_in_tcon4: endpoint@0 {
  1676. reg = <0>;
  1677. remote-endpoint = <&tcon4_out_rgb1>;
  1678. };
  1679. };
  1680. };
  1681. };
  1682.  
  1683. dsi0combophy: phy@5507000 {
  1684. compatible = "allwinner,sunxi-dsi-combo-phy0";
  1685. reg = <0x0 0x05507000 0x0 0x1ff>;
  1686. clocks = <&clk_mipi_dsi_combphy0>,
  1687. <&clk_mipi_dsi0>;
  1688. clock-names = "phy_gating_clk",
  1689. "phy_clk";
  1690. #phy-cells = <0>;
  1691. status = "okay";
  1692. };
  1693.  
  1694. dsi0: dsi0@5506000 {
  1695. compatible = "allwinner,dsi0";
  1696. reg = <0x0 0x05506000 0x0 0xfff>;
  1697. interrupt-parent = <&gic>;
  1698. interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
  1699. clocks = <&clk_mipi_dsi0>;
  1700. clock-names = "dsi_clk";
  1701. phys = <&dsi0combophy>;
  1702. phy-names = "combophy";
  1703. status = "disabled";
  1704.  
  1705. ports {
  1706. #address-cells = <1>;
  1707. #size-cells = <0>;
  1708. dsi0_in: port@0 {
  1709. #address-cells = <1>;
  1710. #size-cells = <0>;
  1711. reg = <0>;
  1712. dsi0_in_tcon0: endpoint@0 {
  1713. reg = <0>;
  1714. remote-endpoint = <&tcon0_out_dsi0>;
  1715. };
  1716. };
  1717. };
  1718. };
  1719.  
  1720. dsi1combophy: phy@5509000 {
  1721. compatible = "allwinner,sunxi-dsi-combo-phy1";
  1722. reg = <0x0 0x05509000 0x0 0x1ff>;
  1723. clocks = <&clk_mipi_dsi_combphy1>,
  1724. <&clk_mipi_dsi0>;
  1725. clock-names = "phy_gating_clk",
  1726. "phy_clk";
  1727. #phy-cells = <0>;
  1728. status = "disabled";
  1729. };
  1730.  
  1731. dsi1: dsi1@5508000 {
  1732. compatible = "allwinner,dsi1";
  1733. reg = <0x0 0x05508000 0x0 0xfff>;
  1734. interrupt-parent = <&gic>;
  1735. interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
  1736. clocks = <&clk_mipi_dsi1>;
  1737. clock-names = "dsi_clk";
  1738. phys = <&dsi1combophy>;
  1739. phy-names = "combophy";
  1740. status = "disabled";
  1741. ports {
  1742. #address-cells = <1>;
  1743. #size-cells = <0>;
  1744. dsi1_in: port@0 {
  1745. reg = <0>;
  1746. #address-cells = <1>;
  1747. #size-cells = <0>;
  1748. dsi1_in_tcon1: endpoint@0 {
  1749. reg = <0>;
  1750. remote-endpoint = <&tcon1_out_dsi1>;
  1751. };
  1752. dsi1_in_tcon0: endpoint@1 {
  1753. reg = <1>;
  1754. remote-endpoint = <&tcon0_out_dsi1>;
  1755. };
  1756. };
  1757. };
  1758. };
  1759.  
  1760. tv0: tcon2@5503000 {
  1761. compatible = "allwinner,tcon-tv";
  1762. reg = <0x0 0x05503000 0x0 0x1000>;
  1763. interrupt-parent = <&gic>;
  1764. interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
  1765. clocks = <&clk_tcon_tv0>;
  1766. clock-names = "clk_tcon";
  1767.  
  1768. top = <&vo0>;
  1769. status = "disabled";
  1770. ports {
  1771. #address-cells = <1>;
  1772. #size-cells = <0>;
  1773. tcon2_in: port@0 {
  1774. #address-cells = <1>;
  1775. #size-cells = <0>;
  1776. reg = <0>;
  1777. tcon2_in_disp0: endpoint@0 {
  1778. reg = <0>;
  1779. remote-endpoint = <&disp0_out_tcon2>;
  1780. };
  1781. tcon2_in_disp1: endpoint@1 {
  1782. reg = <1>;
  1783. remote-endpoint = <&disp1_out_tcon2>;
  1784. };
  1785. };
  1786. tcon2_out: port@1 {
  1787. #address-cells = <1>;
  1788. #size-cells = <0>;
  1789. reg = <1>;
  1790. tcon2_out_hdmi: endpoint@0 {
  1791. reg = <0>;
  1792. remote-endpoint = <&hdmi_in_tcon2>;
  1793. };
  1794. };
  1795. };
  1796. };
  1797.  
  1798. tv1: tcon3@5504000 {
  1799. compatible = "allwinner,tcon-tv";
  1800. reg = <0x0 0x05504000 0x0 0x1000>;
  1801. interrupt-parent = <&gic>;
  1802. interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
  1803. clocks = <&clk_tcon_tv1>;
  1804. clock-names = "clk_tcon";
  1805. top = <&vo0>;
  1806. status = "disabled";
  1807.  
  1808. ports {
  1809. #address-cells = <1>;
  1810. #size-cells = <0>;
  1811. tcon3_in: port@0 {
  1812. reg = <0>;
  1813. #address-cells = <1>;
  1814. #size-cells = <0>;
  1815. tcon3_in_disp0: endpoint@0 {
  1816. reg = <0>;
  1817. remote-endpoint = <&disp0_out_tcon3>;
  1818. };
  1819. tcon3_in_disp1: endpoint@1 {
  1820. reg = <1>;
  1821. remote-endpoint = <&disp1_out_tcon3>;
  1822. };
  1823. };
  1824. tcon3_out: port@1 {
  1825. #address-cells = <1>;
  1826. #size-cells = <0>;
  1827. reg = <1>;
  1828. tcon3_out_edp: endpoint@0 {
  1829. reg = <0>;
  1830. remote-endpoint = <&edp_in_tcon3>;
  1831. };
  1832. };
  1833. };
  1834. };
  1835.  
  1836. drm_edp: drm_edp@5720000 {
  1837. compatible = "allwinner,drm-edp";
  1838. reg = <0x0 0x05720000 0x0 0x4000>;
  1839. interrupt-parent = <&gic>;
  1840. interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
  1841. clocks = <&clk_edp>, <&clk_edp_24m>;
  1842. clock-names = "clk_edp", "clk_24m_edp";
  1843. //FIXME
  1844. status = "disabled";
  1845. ports {
  1846. #address-cells = <1>;
  1847. #size-cells = <0>;
  1848. edp_in: port@0 {
  1849. #address-cells = <1>;
  1850. #size-cells = <0>;
  1851. reg = <0>;
  1852. edp_in_tcon3: endpoint@0 {
  1853. reg = <0>;
  1854. remote-endpoint = <&tcon3_out_edp>;
  1855. };
  1856. };
  1857. edp_out: port@1 {
  1858. #address-cells = <1>;
  1859. #size-cells = <0>;
  1860. reg = <1>;
  1861. edp_out_panel: endpoint@0 {
  1862. reg = <0>;
  1863. };
  1864. };
  1865. };
  1866. };
  1867.  
  1868. disp: disp@5000000 {
  1869. compatible = "allwinner,sunxi-disp";
  1870. reg = <0x0 0x05000000 0x0 0x400000>, /*de*/
  1871. <0x0 0x05500000 0x0 0x1000>, /* display_if_top */
  1872. <0x0 0x05501000 0x0 0x1000>, /* tcon_lcd0 */
  1873. <0x0 0x05502000 0x0 0x1000>, /* tcon_lcd1 */
  1874. <0x0 0x05503000 0x0 0x1000>, /* tcon_tv0 */
  1875. <0x0 0x05504000 0x0 0x1000>, /* tcon_tv1 */
  1876. <0x0 0x05731000 0x0 0x1000>, /* tcon_lcd2 */
  1877. <0x0 0x05506000 0x0 0x1fff>, /* dsi0 */
  1878. <0x0 0x05508000 0x0 0x1fff>; /* dsi1 */
  1879. interrupt-parent = <&gic>;
  1880. interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, /* DE */
  1881. <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, /* tcon_lcd0 */
  1882. <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, /* tcon_lcd1 */
  1883. <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, /* tcon_tv0 */
  1884. <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* tcon_tv1 */
  1885. <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, /* tcon_lcd2 */
  1886. <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, /* dsi0 */
  1887. <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; /* dsi1 */
  1888. clocks = <&clk_de0>,
  1889. // <&clk_de1>,
  1890. <&clk_dpss_top0>,
  1891. <&clk_tcon_lcd0>, /* tcon lcd */
  1892. <&clk_tcon_lcd1>,
  1893. <&clk_tcon_tv0>, /* tcon tv */
  1894. <&clk_tcon_tv1>,
  1895. <&clk_tcon_lcd2>,
  1896. <&clk_lvds0>,
  1897. <&clk_lvds1>,
  1898. <&clk_mipi_dsi0>,
  1899. <&clk_mipi_dsi1>,
  1900. <&clk_mipi_dsi_combphy0>,
  1901. <&clk_mipi_dsi_combphy1>;
  1902. // interrupt-parent = <&gic>;
  1903. boot_disp = <0>;
  1904. boot_disp1 = <0>;
  1905. boot_disp2 = <0>;
  1906. fb_base = <0>;
  1907. status = "okay";
  1908. };
  1909.  
  1910. hdmi: hdmi@5520000 {
  1911. compatible = "allwinner,sunxi-hdmi";
  1912. reg = <0x0 0x05520000 0x0 0x100000>;
  1913. clocks = <&clk_tcon_tv0>, <&clk_hdmi>, <&clk_hdmi_24m>,
  1914. <&clk_hdmi_sub>;
  1915. clock-names = "clk_tcon_tv",
  1916. "clk_hdmi",
  1917. "clk_hdmi_24M",
  1918. "rst_main";
  1919. status = "okay";
  1920. ports {
  1921. #address-cells = <1>;
  1922. #size-cells = <0>;
  1923. hdmi_in: port@0 {
  1924. #address-cells = <1>;
  1925. #size-cells = <0>;
  1926. reg = <0>;
  1927. hdmi_in_tcon2: endpoint@0 {
  1928. reg = <0>;
  1929. remote-endpoint = <&tcon2_out_hdmi>;
  1930. };
  1931. };
  1932. };
  1933.  
  1934. };
  1935.  
  1936. codec:codec@7110000 {
  1937. #address-cells = <2>;
  1938. #size-cells = <2>;
  1939. ranges;
  1940. compatible = "allwinner,sunxi-internal-codec";
  1941. reg = <0x0 0x07110000 0x0 0x2C0>,
  1942. <0x0 0x07110300 0x0 0x048>;
  1943. lineout_vol =<0x1F>;
  1944. /* Pa enabled about */
  1945. pa_level =<0x01>;
  1946. pa_pwr_level =<0x01>;
  1947. gpio-spk = <&pio PH 6 GPIO_ACTIVE_HIGH>;
  1948. status = "okay";
  1949. };
  1950.  
  1951. boottone:boottone {
  1952. device_type = "boottone";
  1953. status = "okay";
  1954. };
  1955.  
  1956. edp0: edp0@5720000 {
  1957. compatible = "allwinner,sunxi-edp0";
  1958. reg = <0x0 0x05720000 0x0 0x4000>;
  1959. interrupt-parent = <&gic>;
  1960. interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
  1961. clocks = <&clk_edp>, <&clk_edp_24m>;
  1962. reset-names = "rst_bus_edp";
  1963. status = "okay";
  1964. };
  1965.  
  1966. lcd0: lcd0@1c0c000 {
  1967. // #address-cells = <2>;
  1968. // #size-cells = <2>;
  1969. compatible = "allwinner,sunxi-lcd0";
  1970. // reg = <0x0 0x1c0c000 0x0 0x0>; /* Fake registers to avoid dtc compiling warnings */
  1971. pinctrl-names = "active","sleep";
  1972. status = "okay";
  1973. };
  1974. lcd0_1: lcd0_1@1c0c000 {
  1975. };
  1976.  
  1977. lcd1: lcd1@0 {
  1978. compatible = "allwinner,sunxi-lcd1";
  1979. // reg = <0x0 0x1c0c000 0x0 0x0>; /* Fake registers to avoid dtc compiling warnings */
  1980. pinctrl-names = "active","sleep";
  1981. status = "okay";
  1982. };
  1983.  
  1984. lcd1_1: lcd1_1@1 {
  1985. };
  1986.  
  1987. lcd1_2: lcd1_2@2 {
  1988. };
  1989.  
  1990. lcd2: lcd2@1c0c000 {
  1991. compatible = "allwinner,sunxi-lcd2";
  1992. /* Fake registers to avoid dtc compiling warnings */
  1993. // reg = <0x0 0x1c0c000 0x0 0x0>;
  1994. pinctrl-names = "active","sleep";
  1995. status = "okay";
  1996. };
  1997. eink: eink@6400000 {
  1998. compatible = "allwinner,sunxi-eink";
  1999. pinctrl-names = "active","sleep";
  2000. reg = <0x0 0x06400000 0x0 0x01ffff>,/* eink */
  2001. <0x0 0x06000000 0x0 0x3fffff>;/* de */
  2002. interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, /* eink */
  2003. <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; /* de */
  2004. clocks = <&clk_de0>,
  2005. <&clk_ee>,
  2006. <&clk_panel>;
  2007. /* iommus = <&mmu_aw 6 1>; */
  2008. interrupt-parent = <&gic>;
  2009. status = "okay";
  2010. };
  2011.  
  2012. s_cir0: s_cir@07040000 {
  2013. compatible = "allwinner,s_cir";
  2014. };
  2015.  
  2016. clk_test: clk_test@0x12345 {
  2017. clocks = <&clk_sdmmc0_mod>,
  2018. <&clk_sdmmc0_rst>,
  2019. <&clk_sdmmc0_bus>,
  2020. <&clk_sdmmc2_mod>,
  2021. <&clk_sdmmc2_rst>,
  2022. <&clk_sdmmc2_bus>;
  2023. status = "okay";
  2024. };
  2025. combophy: phy@4f00000 {
  2026. compatible = "allwinner,inno-combphy";
  2027. reg = <0x0 0x04f00000 0x0 0x80000>, /* Sub-System Application Registers */
  2028. <0x0 0x04f80000 0x0 0x80000>; /* Combo INNO PHY Registers */
  2029. reg-names = "phy-ctl", "phy-clk";
  2030. #phy-cells = <1>;
  2031. status = "disabled";
  2032. };
  2033.  
  2034. gma340_pcie: gma340-pcie {
  2035. compatible = "regulator-fixed";
  2036. regulator-name = "gma340-pcie";
  2037. regulator-min-microvolt = <3300000>;
  2038. regulator-max-microvolt = <3300000>;
  2039. regulator-always-on;
  2040. regulator-boot-on;
  2041. gpio = <&pio PB 6 GPIO_ACTIVE_HIGH>;
  2042. enable-active-high;
  2043. };
  2044.  
  2045. pcie_pwren_reg: pcie-pwren {
  2046. compatible = "regulator-fixed";
  2047. regulator-name = "pcie-pwren";
  2048. regulator-min-microvolt = <3300000>;
  2049. regulator-max-microvolt = <3300000>;
  2050. gpio = <&r_pio 11 0>; // PL11, GPIO_ACTIVE_HIGH
  2051. enable-active-high;
  2052. regulator-always-on;
  2053. regulator-boot-on;
  2054. pinctrl-names = "default";
  2055. pinctrl-0 = <&pcie_pwren_pins>;
  2056. };
  2057.  
  2058. pcie: pcie@4800000 {
  2059. compatible = "allwinner,sunxi-pcie-v210-rc";
  2060. #address-cells = <3>;
  2061. #size-cells = <2>;
  2062. bus-range = <0x0 0xff>;
  2063. reg = <0 0x04800000 0 0x480000>;
  2064. reg-names = "dbi";
  2065. device_type = "pci";
  2066. ranges = <0x00000800 0 0x20000000 0x0 0x20000000 0 0x01000000
  2067. 0x81000000 0 0x21000000 0x0 0x21000000 0 0x01000000
  2068. 0x82000000 0 0x22000000 0x0 0x22000000 0 0x0e000000>;
  2069. num-lanes = <1>;
  2070. phys = <&combophy PHY_TYPE_PCIE>;
  2071. phy-names = "pcie-phy";
  2072. #interrupt-cells = <1>;
  2073. num-edma = <4>;
  2074. max-link-speed = <2>;
  2075. num-ib-windows = <8>;
  2076. num-ob-windows = <8>;
  2077. linux,pci-domain = <0>;
  2078. clocks = <&ccu 0x1a>, <&ccu 0x94>; // "hosc", "pclk_aux"
  2079. clock-names = "hosc", "pclk_aux";
  2080. reset-gpios = <&pio 7 11 GPIO_ACTIVE_LOW>; // PH11, PCIE0-PERST#
  2081. wake-gpios = <&pio 7 12 GPIO_ACTIVE_LOW>; // PH12, PCIE0-WAKE#
  2082. power-domains = <&pck 0x07>;
  2083. gma340-pcie-supply = <&gma340_pcie>;
  2084. status = "okay";
  2085. };
  2086. };
  2087.  
  2088. gic: interrupt-controller@3020000 {
  2089. compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
  2090. #interrupt-cells = <3>;
  2091. #address-cells = <0>;
  2092. device_type = "gic";
  2093. interrupt-controller;
  2094. reg = <0x0 0x03021000 0 0x1000>, /* GIC Dist */
  2095. <0x0 0x03022000 0 0x2000>, /* GIC CPU */
  2096. <0x0 0x03024000 0 0x2000>, /* GIC VCPU Control */
  2097. <0x0 0x03026000 0 0x2000>; /* GIC VCPU */
  2098. interrupts = <GIC_PPI 9 0xf04>; /* GIC Maintenence IRQ */
  2099. interrupt-parent = <&gic>;
  2100. };
  2101. };
  2102.  
  2103. #include "sun55iw3p1-clk.dtsi"
  2104. #include ".board-uboot.dts"
Tags: Radxa
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