module cnt ( clk , clrn , ena , out) ;
    input clk , clrn , ena;
    output logic [3:0] out;
    enum logic [0:3] {s0,s1,s2,s3,s4,s5,s6,s7} state, next_state;

    always_ff @ (posedge clk or negedge clrn) begin
        if (!clrn) state <= s0;
        else state <= next_state;
    end

    always_comb begin
    case (state)
        s0: next_state = s5;
        s1: next_state = s6;
        s2: next_state = s7;
        s3: next_state = s0;
        s4: next_state = s1;
        s5: next_state = s2;
        s6: next_state = s3;
        s7: next_state = s4;
    endcase
    end

    always @ (state) begin
        case (state)
            s0: out = 3'b000;
            s1: out = 3'b001;
            s2: out = 3'b010;
            s3: out = 3'b011;
            s4: out = 3'b100;
            s5: out = 3'b101;
            s6: out = 3'b110;
            s7: out = 3'b111;
            default: out= 3'b000;
        endcase
    end
endmodule