library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SIPO is
port
(clk,x: in std_logic;
    q : out std_logic_vector(3 downto 0)
);
end SIPO;

architecture Behavioral of SIPO is
signal q1: std_logic_vector(3 downto 0):="0000";

begin
process(clk)
begin
if clk'event and clk='1' then
q1(3)<=q1(2);
q1(2)<=q1(1);
q1(1)<=q1(0);
q1(0)<=x;
end if;
end process;
q<=q1;
end Behavioral;