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- synth_ice40 -abc9
- === axilxbar ===
- Number of wires: 5920
- Number of wire bits: 12443
- Number of public wires: 356
- Number of public wire bits: 5182
- Number of memories: 0
- Number of memory bits: 0
- Number of processes: 0
- Number of cells: 9092
- SB_CARRY 108
- SB_DFFE 44
- SB_DFFESR 1784
- SB_DFFESS 32
- SB_DFFSR 40
- SB_LUT4 7084
- Lofty notes: even though this looks worse area-wise, ABC9 is delay-based, so this will likely be faster than normal ABC.
- synth_ice40
- === axilxbar ===
- Number of wires: 7196
- Number of wire bits: 12166
- Number of public wires: 380
- Number of public wire bits: 5206
- Number of memories: 0
- Number of memory bits: 0
- Number of processes: 0
- Number of cells: 8800
- SB_CARRY 100
- SB_DFFE 44
- SB_DFFESR 1784
- SB_DFFESS 32
- SB_DFFSR 40
- SB_LUT4 6800
- Lofty notes: ABC by itself uses a unit delay model, so it's effectively optimising purely for area here.
- synth_ice40 -noabc
- === axilxbar ===
- Number of wires: 5314
- Number of wire bits: 22644
- Number of public wires: 466
- Number of public wire bits: 5762
- Number of memories: 0
- Number of memory bits: 0
- Number of processes: 0
- Number of cells: 10097
- SB_CARRY 100
- SB_DFFE 44
- SB_DFFESR 1784
- SB_DFFESS 32
- SB_DFFSR 40
- SB_LUT4 8097
- Lofty notes: Here, Yosys is just techmapping gates to LUTs, and then trying to pack them together. It's pretty naive.
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