`timescale 1ns / 1ps
module Drive_74595(Clock, Data_In, Shift, Latch, Data_Out);
//----------------------------CONTROL SIGNALS-----------------------------------
input Clock;
input [7:0] Data_In; // 8-bit input data
output Shift; // Register CLK, pushes the FIFO data to the driver outputs
output Latch; // Positive Edge Triggered Shift Register CLK
output Data_Out; // The serial data output
reg [7:0] Clk_Count;
reg R_Shift, R_Latch, R_DataO;
//=====================================================
always @ ( posedge Clock )
begin
Clk_Count <= Clk_Count + 1;
if( Clk_Count > 20 ) begin
Clk_Count <= 0;
end
//----------------------------------------------
if(Clk_Count == 0) begin
R_Shift <= 0;
R_Latch <= 0;
R_DataO <= Data_In[0];
end
if(Clk_Count == 1) begin
R_Shift <= 1;
R_Latch <= 0;
R_DataO <= Data_In[0];
end
//----------------------------------------------
if(Clk_Count == 2) begin
R_Shift <= 0;
R_Latch <= 0;
R_DataO <= Data_In[1];
end
if(Clk_Count == 3) begin
R_Shift <= 1;
R_Latch <= 0;
R_DataO <= Data_In[1];
end
//----------------------------------------------
if(Clk_Count == 4) begin
R_Shift <= 0;
R_Latch <= 0;
R_DataO <= Data_In[2];
end
if(Clk_Count == 5) begin
R_Shift <= 1;
R_Latch <= 0;
R_DataO <= Data_In[2];
end
//----------------------------------------------
if(Clk_Count == 6) begin
R_Shift <= 0;
R_Latch <= 0;
R_DataO <= Data_In[3];
end
if(Clk_Count == 7) begin
R_Shift <= 1;
R_Latch <= 0;
R_DataO <= Data_In[3];
end
//----------------------------------------------
if(Clk_Count == 8) begin
R_Shift <= 0;
R_Latch <= 0;
R_DataO <= Data_In[4];
end
if(Clk_Count == 9) begin
R_Shift <= 1;
R_Latch <= 0;
R_DataO <= Data_In[4];
end
//----------------------------------------------
if(Clk_Count == 10) begin
R_Shift <= 0;
R_Latch <= 0;
R_DataO <= Data_In[5];
end
if(Clk_Count == 11) begin
R_Shift <= 1;
R_Latch <= 0;
R_DataO <= Data_In[5];
end
//----------------------------------------------
if(Clk_Count == 12) begin
R_Shift <= 0;
R_Latch <= 0;
R_DataO <= Data_In[6];
end
if(Clk_Count == 13) begin
R_Shift <= 1;
R_Latch <= 0;
R_DataO <= Data_In[6];
end
//----------------------------------------------
if(Clk_Count == 14) begin
R_Shift <= 0;
R_Latch <= 0;
R_DataO <= Data_In[7];
end
if(Clk_Count == 15) begin
R_Shift <= 1;
R_Latch <= 0;
R_DataO <= Data_In[7];
end
//----------------------------------------------
if(Clk_Count == 16) begin
R_Shift <= 0;
R_Latch <= 0;
R_DataO <= 0;
end
if(Clk_Count == 17) begin
R_Shift <= 0;
R_Latch <= 1;
R_DataO <= 0;
end
//----------------------------------------------
end
assign Shift = R_Shift;
assign Latch = R_Latch;
assign Data_Out = R_DataO;
endmodule