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  1. From 37fa9ca7adccd4cc34e4916a36ed9e6d1db51c34 Mon Sep 17 00:00:00 2001
  2. From: "Alex L. White" <space.monkey.delivers@gmail.com>
  3. Date: Tue, 17 May 2016 13:13:15 +0300
  4. Subject: [PATCH] Introducing 4 state branch predictor
  5.  
  6. ---
  7.  rtl/verilog/mor1kx_branch_prediction.v | 74 ++++++++++++++++++++++++++++------
  8.  rtl/verilog/mor1kx_cpu_cappuccino.v    |  7 +++-
  9.  2 files changed, 66 insertions(+), 15 deletions(-)
  10.  
  11. diff --git a/rtl/verilog/mor1kx_branch_prediction.v b/rtl/verilog/mor1kx_branch_prediction.v
  12. index a82c1f9..e903a84 100644
  13. --- a/rtl/verilog/mor1kx_branch_prediction.v
  14. +++ b/rtl/verilog/mor1kx_branch_prediction.v
  15. @@ -18,35 +18,83 @@
  16.  
  17.  module mor1kx_branch_prediction
  18.    #(
  19. -    parameter OPTION_OPERAND_WIDTH = 32
  20. +    parameter OPTION_OPERAND_WIDTH = 32,
  21. +    parameter FEATURE_4_STATE_PREDICTOR = "NONE"
  22.      )
  23.     (
  24. -    input  clk,
  25. -    input  rst,
  26. +    input clk,
  27. +    input rst,
  28.  
  29.      // Signals belonging to the stage where the branch is predicted.
  30. -    input  op_bf_i,
  31. -    input  op_bnf_i,
  32. -    input [9:0] immjbr_upper_i,
  33. -    output     predicted_flag_o,
  34. +    input op_bf_i,               // branch if flag
  35. +    input op_bnf_i,              // branch if not flag
  36. +    input [9:0] immjbr_upper_i,  // branch offset
  37. +    output predicted_flag_o,     //result of predictor
  38.  
  39.      // Signals belonging to the stage where the branch is resolved.
  40. -    input  prev_op_brcond_i,
  41. -    input  prev_predicted_flag_i,
  42. -    input  flag_i,
  43. +    input prev_op_brcond_i,      // prev op was cond brn
  44. +    input prev_predicted_flag_i, // prev insn predicated flag
  45. +    input flag_i,                // prev insn real flag
  46.  
  47.      // Branch misprediction indicator
  48. -    output     branch_mispredict_o
  49. +    output branch_mispredict_o   // result of prediction
  50.      );
  51.  
  52.     // Compare the real flag with the previously predicted flag and signal a
  53.     // misprediction in case of a mismatch.
  54.     assign branch_mispredict_o = prev_op_brcond_i &
  55. -               (flag_i != prev_predicted_flag_i);
  56. +                                (flag_i != prev_predicted_flag_i);
  57. +  
  58. +generate
  59. +if (FEATURE_4_STATE_PREDICTOR!="NONE") begin : branch_predictor_gen
  60. +   localparam [1:0]
  61. +      STATE_STRONGLY_NOT_TAKEN = 2'b00,
  62. +      STATE_WEAKLY_NOT_TAKEN   = 2'b01,
  63. +      STATE_WEAKLY_TAKEN       = 2'b10,
  64. +      STATE_STRONGLY_TAKEN     = 2'b11;
  65.  
  66. +   reg [1:0] state = STATE_WEAKLY_TAKEN;
  67. +
  68. +   assign predicted_flag_o = state[1];
  69. +
  70. +   always @(posedge clk) begin
  71. +      if (rst) begin
  72. +         // set default state to STATE_WEAKLY_TAKEN
  73. +         state <= STATE_WEAKLY_TAKEN;
  74. +      end else begin
  75. +         // if prev insn was a branch
  76. +         if (prev_op_brcond_i) begin
  77. +            // if it was mispredicted
  78. +            if (branch_mispredict_o) begin
  79. +               // change fsm state:
  80. +               //   STATE_STRONGLY_TAKEN -> STATE_WEAKLY_TAKEN
  81. +               //   STATE_WEAKLY_TAKEN -> STATE_WEAKLY_NOT_TAKEN
  82. +               //   STATE_WEAKLY_NOT_TAKEN -> STATE_STRONGLY_NOT_TAKEN
  83. +               //   STATE_STRONGLY_NOT_TAKEN -> STATE_STRONGLY_NOT_TAKEN
  84. +               state <= (state == STATE_STRONGLY_TAKEN) ? STATE_WEAKLY_TAKEN :
  85. +                        (state == STATE_WEAKLY_TAKEN)   ? STATE_WEAKLY_NOT_TAKEN
  86. +                                                        : STATE_STRONGLY_NOT_TAKEN;
  87. +            // if prev insn was predicted correctly                                        
  88. +            end else begin
  89. +               // change fsm state:
  90. +               //   STATE_STRONGLY_NOT_TAKEN -> STATE_WEAKLY_NOT_TAKEN
  91. +               //   STATE_WEAKLY_NOT_TAKEN -> STATE_WEAKLY_TAKEN
  92. +               //   STATE_WEAKLY_TAKEN -> STATE_STRONGLY_TAKEN
  93. +               //   STATE_STRONGLY_TAKEN -> STATE_STRONGLY_TAKEN
  94. +               state <= (state == STATE_STRONGLY_NOT_TAKEN) ? STATE_WEAKLY_NOT_TAKEN :
  95. +                        (state == STATE_WEAKLY_NOT_TAKEN)   ? STATE_WEAKLY_TAKEN
  96. +                                                            : STATE_STRONGLY_TAKEN;
  97. +            end
  98. +         end
  99. +      end
  100. +   end
  101. +  
  102. +end else begin
  103.     // Static branch prediction - backward branches are predicted as taken,
  104.     // forward branches as not taken.
  105.     assign predicted_flag_o = op_bf_i & immjbr_upper_i[9] |
  106. -                op_bnf_i & !immjbr_upper_i[9];
  107. +                             op_bnf_i & !immjbr_upper_i[9];
  108. +end
  109. +endgenerate
  110.  
  111.  endmodule
  112. diff --git a/rtl/verilog/mor1kx_cpu_cappuccino.v b/rtl/verilog/mor1kx_cpu_cappuccino.v
  113. index f282374..2af018e 100644
  114. --- a/rtl/verilog/mor1kx_cpu_cappuccino.v
  115. +++ b/rtl/verilog/mor1kx_cpu_cappuccino.v
  116. @@ -96,7 +96,9 @@ module mor1kx_cpu_cappuccino
  117.  
  118.      parameter FEATURE_MULTICORE = "NONE",
  119.  
  120. -    parameter FEATURE_TRACEPORT_EXEC = "NONE"
  121. +    parameter FEATURE_TRACEPORT_EXEC = "NONE",
  122. +    
  123. +    parameter FEATURE_4_STATE_PREDICTOR = "NONE"
  124.      )
  125.     (
  126.      input                clk,
  127. @@ -752,7 +754,8 @@ module mor1kx_cpu_cappuccino
  128.      );*/
  129.     mor1kx_branch_prediction
  130.       #(
  131. -       .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH)
  132. +       .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH),
  133. +       .FEATURE_4_STATE_PREDICTOR(FEATURE_4_STATE_PREDICTOR)
  134.         )
  135.     mor1kx_branch_prediction
  136.       (/*AUTOINST*/
  137. --
  138. 1.9.1
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