----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    15:03:39 12/13/2018
-- Design Name:
-- Module Name:    TOP1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TOP1 is
    Port ( inSTOP : in  STD_LOGIC;
           inRL : in  STD_LOGIC;
           inRR : in  STD_LOGIC;
           inBLINK : in  STD_LOGIC;
           iCLK : in  STD_LOGIC;
           inRST : in  STD_LOGIC;
	    	  oLED : out  STD_LOGIC_VECTOR (7 downto 0));
end TOP1;

architecture Behavioral of TOP1 is

	component LEDShow is
    Port ( inSTOP : in  STD_LOGIC;
           inRL : in  STD_LOGIC;
           inRR : in  STD_LOGIC;
           inBLINK : in  STD_LOGIC;
           oLED : out  STD_LOGIC_VECTOR (7 downto 0);
           iCLK : in  STD_LOGIC;
           inRST : in  STD_LOGIC);
end component;

	component Modul2 is
    Port ( iDATA : in  STD_LOGIC_VECTOR (7 downto 0);
           iCLK : in  STD_LOGIC;
           inRST : in  STD_LOGIC;
           oDATA : out  STD_LOGIC_VECTOR (7 downto 0));
	end component;

	signal S : std_logic_vector (7 downto 0);

begin

	iCOMP1 : LEDShow port map (
		inSTOP => inSTOP,
		inRL => inRL,
		inRR => inRR,
		inBLINK => inBLINK,
		iCLK => iCLK,
		inRST => inRST,
		oLED => S
		);

	iCOMP2 : Modul2 port map (
		iDATA => S,
		iCLK => iCLK,
		inRST => inRST,
		oDATA => oLED
		);



end Behavioral;