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- cpuid
- CPU 0:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0x5 (5)
- stepping id = 0x7 (7)
- extended family = 0x0 (0)
- extended model = 0x5 (5)
- (family synth) = 0x6 (6)
- (model synth) = 0x55 (85)
- (simple synth) = Intel Core (unknown type) (Skylake / Skylake-X / Cascade Lake / Cascade Lake-X) {Skylake}, 14nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x0 (0)
- maximum IDs for CPUs in pkg = 0x0 (0)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = false
- ACPI: thermal monitor and clock ctrl = false
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = false
- TM: therm. monitor = false
- IA64 = false
- PBE: pending break event = false
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = false
- MONITOR/MWAIT = false
- CPL-qualified debug store = false
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = false
- Enhanced Intel SpeedStep Technology = false
- TM2: thermal monitor 2 = false
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = true
- CMPXCHG16B instruction = true
- xTPR disable = false
- PDCM: perfmon and debug = false
- PCID: process context identifiers = true
- DCA: direct cache access = false
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = true
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = true
- cache and TLB information (2):
- 0x4d: L3 cache: 16M, 16-way, 64 byte lines
- 0x7d: L2 cache: 2M, 8-way, 64 byte lines
- 0x30: L1 cache: 32K, 8-way, 64 byte lines
- 0x2c: L1 data cache: 32K, 8-way, 64 byte lines
- processor serial number = 0005-0657-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x0 (0)
- maximum IDs for cores in pkg = 0x0 (0)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = true
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x0 (0)
- maximum IDs for cores in pkg = 0x0 (0)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = true
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x0 (0)
- maximum IDs for cores in pkg = 0x0 (0)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x10 (16)
- number of sets = 0x1000 (4096)
- WBINVD/INVD acts on lower caches = true
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 4096
- (size synth) = 4194304 (4 MB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x0 (0)
- maximum IDs for cores in pkg = 0x0 (0)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x10 (16)
- number of sets = 0x4000 (16384)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 16384
- (size synth) = 16777216 (16 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x0 (0)
- largest monitor-line size (bytes) = 0x0 (0)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x0 (0)
- number of C2 sub C-states using MWAIT = 0x0 (0)
- number of C3 sub C-states using MWAIT = 0x0 (0)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = false
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = false
- ECMD extended clock modulation duty = false
- PTM package thermal management = false
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x0 (0)
- hardware coordination feedback = false
- ACNT2 available = false
- performance-energy bias capability = false
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = true
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = true
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = true
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = true
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = true
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = true
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = true
- AVX512DQ: double & quadword instructions = true
- RDSEED instruction = true
- ADX instructions = true
- SMAP: supervisor mode access prevention = true
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = true
- CLWB instruction = true
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = true
- SHA instructions = false
- AVX512BW: byte & word instructions = true
- AVX512VL: vector length = true
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = true
- PKU protection keys for user-mode = true
- OSPKE CR4.PKE and RDPKRU/WRPKRU = true
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = true
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = true
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = true
- STIBP: 1 thr indirect branch predictor = true
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = true
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = true
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 0
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x2 (2)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 0
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x0 (0)
- number of logical processors at level = 0x1 (1)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x0 (0)
- number of logical processors at level = 0x1 (1)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x000002ff
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = true
- XCR0 supported: MPX BNDCSR = true
- XCR0 supported: AVX-512 opmask = true
- XCR0 supported: AVX-512 ZMM_Hi256 = true
- XCR0 supported: AVX-512 Hi16_ZMM = true
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = true
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000a88 (2696)
- bytes required by XSAVE/XRSTOR area = 0x00000a88 (2696)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = true
- XGETBV instruction = true
- XSAVES/XRSTORS instructions = true
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000a08 (2568)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- MPX BNDREGS features (0xd/3):
- MPX BNDREGS save state byte size = 0x00000040 (64)
- MPX BNDREGS save state byte offset = 0x000003c0 (960)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- MPX BNDCSR features (0xd/4):
- MPX BNDCSR save state byte size = 0x00000040 (64)
- MPX BNDCSR save state byte offset = 0x00000400 (1024)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- AVX-512 opmask features (0xd/5):
- AVX-512 opmask save state byte size = 0x00000040 (64)
- AVX-512 opmask save state byte offset = 0x00000440 (1088)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- AVX-512 ZMM_Hi256 features (0xd/6):
- AVX-512 ZMM_Hi256 save state byte size = 0x00000200 (512)
- AVX-512 ZMM_Hi256 save state byte offset = 0x00000480 (1152)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- AVX-512 Hi16_ZMM features (0xd/7):
- AVX-512 Hi16_ZMM save state byte size = 0x00000400 (1024)
- AVX-512 Hi16_ZMM save state byte offset = 0x00000680 (1664)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- PKRU features (0xd/9):
- PKRU save state byte size = 0x00000008 (8)
- PKRU save state byte offset = 0x00000a80 (2688)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- Quality of Service Monitoring Resource Type (0xf/0):
- Maximum range of RMID = 0
- supports L3 cache QoS monitoring = false
- Resource Director Technology Allocation (0x10/0):
- L3 cache allocation technology supported = false
- L2 cache allocation technology supported = false
- memory bandwidth allocation supported = false
- 0x00000011 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
- Software Guard Extensions (SGX) capability (0x12/0):
- SGX1 supported = false
- SGX2 supported = false
- SGX ENCLV E*VIRTCHILD, ESETCONTEXT = false
- SGX ENCLS ETRACKC, ERDINFO, ELDBC, ELDUC = false
- MISCSELECT.EXINFO supported: #PF & #GP = false
- MISCSELECT.CPINFO supported: #CP = false
- MaxEnclaveSize_Not64 (log2) = 0x0 (0)
- MaxEnclaveSize_64 (log2) = 0x0 (0)
- 0x00000013 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
- Intel Processor Trace (0x14):
- IA32_RTIT_CR3_MATCH is accessible = false
- configurable PSB & cycle-accurate = false
- IP & TraceStop filtering; PT preserve = false
- MTC timing packet; suppress COFI-based = false
- PTWRITE support = false
- power event trace support = false
- ToPA output scheme support = false
- ToPA can hold many output entries = false
- single-range output scheme support = false
- output to trace transport = false
- IP payloads have LIP values & CS = false
- Time Stamp Counter/Core Crystal Clock Information (0x15):
- TSC/clock ratio = 0/0
- nominal core crystal clock = 0 Hz
- Processor Frequency Information (0x16):
- Core Base Frequency (MHz) = 0x0 (0)
- Core Maximum Frequency (MHz) = 0x0 (0)
- Bus (Reference) Frequency (MHz) = 0x0 (0)
- hypervisor_id = "KVMKVMKVM "
- hypervisor features (0x40000001/eax):
- kvmclock available at MSR 0x11 = true
- delays unnecessary for PIO ops = true
- mmu_op = false
- kvmclock available at MSR 0x4b564d00 = true
- async pf enable available by MSR = true
- steal clock supported = true
- guest EOI optimization enabled = true
- guest spinlock optimization enabled = true
- guest TLB flush optimization enabled = true
- async PF VM exit enable available by MSR = false
- guest send IPI optimization enabled = true
- host HLT poll disable at MSR 0x4b564d05 = true
- guest sched yield optimization enabled = true
- guest uses intrs for page ready APF evs = false
- stable: no guest per-cpu warps expected = true
- hypervisor features (0x40000001/edx):
- realtime hint: no unbound preemption = true
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = true
- 3DNow! PREFETCH/PREFETCHW instructions = true
- brand = "Intel(R) Xeon(R) Platinum 8275CL CPU @ 3.00GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0xff (255)
- instruction associativity = 0x1 (1)
- data # entries = 0xff (255)
- data associativity = 0x1 (1)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0xff (255)
- instruction associativity = 0x1 (1)
- data # entries = 0xff (255)
- data associativity = 0x1 (1)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x1 (1)
- associativity = 0x2 (2)
- size (KB) = 0x40 (64)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x1 (1)
- associativity = 0x2 (2)
- size (KB) = 0x40 (64)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x200 (512)
- instruction associativity = 4-way (4)
- data # entries = 0x200 (512)
- data associativity = 4-way (4)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x1 (1)
- associativity = 16-way (8)
- size (KB) = 0x200 (512)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x1 (1)
- associativity = 16-way (8)
- size (in 512KB units) = 0x20 (32)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = false
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = true
- IBRS: indirect branch restr speculation = true
- STIBP: 1 thr indirect branch predictor = true
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = true
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = none
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=0 SMT_width=0
- (APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=0
- (uarch synth) = Intel Cascade Lake {Skylake}, 14nm
- (synth) = Intel Scalable (2nd Gen) Bronze/Silver/Gold/Platinum (Cascade Lake B1/L1/R1) {Skylake}, 14nm
- CPU 1:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0x5 (5)
- stepping id = 0x7 (7)
- extended family = 0x0 (0)
- extended model = 0x5 (5)
- (family synth) = 0x6 (6)
- (model synth) = 0x55 (85)
- (simple synth) = Intel Core (unknown type) (Skylake / Skylake-X / Cascade Lake / Cascade Lake-X) {Skylake}, 14nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x1 (1)
- maximum IDs for CPUs in pkg = 0x0 (0)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = false
- ACPI: thermal monitor and clock ctrl = false
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = false
- TM: therm. monitor = false
- IA64 = false
- PBE: pending break event = false
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = false
- MONITOR/MWAIT = false
- CPL-qualified debug store = false
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = false
- Enhanced Intel SpeedStep Technology = false
- TM2: thermal monitor 2 = false
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = true
- CMPXCHG16B instruction = true
- xTPR disable = false
- PDCM: perfmon and debug = false
- PCID: process context identifiers = true
- DCA: direct cache access = false
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = true
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = true
- cache and TLB information (2):
- 0x4d: L3 cache: 16M, 16-way, 64 byte lines
- 0x7d: L2 cache: 2M, 8-way, 64 byte lines
- 0x30: L1 cache: 32K, 8-way, 64 byte lines
- 0x2c: L1 data cache: 32K, 8-way, 64 byte lines
- processor serial number = 0005-0657-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x0 (0)
- maximum IDs for cores in pkg = 0x0 (0)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = true
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x0 (0)
- maximum IDs for cores in pkg = 0x0 (0)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = true
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x0 (0)
- maximum IDs for cores in pkg = 0x0 (0)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x10 (16)
- number of sets = 0x1000 (4096)
- WBINVD/INVD acts on lower caches = true
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 4096
- (size synth) = 4194304 (4 MB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x0 (0)
- maximum IDs for cores in pkg = 0x0 (0)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x10 (16)
- number of sets = 0x4000 (16384)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 16384
- (size synth) = 16777216 (16 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x0 (0)
- largest monitor-line size (bytes) = 0x0 (0)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x0 (0)
- number of C2 sub C-states using MWAIT = 0x0 (0)
- number of C3 sub C-states using MWAIT = 0x0 (0)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = false
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = false
- ECMD extended clock modulation duty = false
- PTM package thermal management = false
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x0 (0)
- hardware coordination feedback = false
- ACNT2 available = false
- performance-energy bias capability = false
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = true
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = true
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = true
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = true
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = true
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = true
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = true
- AVX512DQ: double & quadword instructions = true
- RDSEED instruction = true
- ADX instructions = true
- SMAP: supervisor mode access prevention = true
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = true
- CLWB instruction = true
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = true
- SHA instructions = false
- AVX512BW: byte & word instructions = true
- AVX512VL: vector length = true
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = true
- PKU protection keys for user-mode = true
- OSPKE CR4.PKE and RDPKRU/WRPKRU = true
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = true
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = true
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = true
- STIBP: 1 thr indirect branch predictor = true
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = true
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = true
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 0
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x2 (2)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 1
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x0 (0)
- number of logical processors at level = 0x1 (1)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x0 (0)
- number of logical processors at level = 0x1 (1)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x000002ff
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = true
- XCR0 supported: MPX BNDCSR = true
- XCR0 supported: AVX-512 opmask = true
- XCR0 supported: AVX-512 ZMM_Hi256 = true
- XCR0 supported: AVX-512 Hi16_ZMM = true
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = true
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000a88 (2696)
- bytes required by XSAVE/XRSTOR area = 0x00000a88 (2696)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = true
- XGETBV instruction = true
- XSAVES/XRSTORS instructions = true
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000a08 (2568)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- MPX BNDREGS features (0xd/3):
- MPX BNDREGS save state byte size = 0x00000040 (64)
- MPX BNDREGS save state byte offset = 0x000003c0 (960)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- MPX BNDCSR features (0xd/4):
- MPX BNDCSR save state byte size = 0x00000040 (64)
- MPX BNDCSR save state byte offset = 0x00000400 (1024)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- AVX-512 opmask features (0xd/5):
- AVX-512 opmask save state byte size = 0x00000040 (64)
- AVX-512 opmask save state byte offset = 0x00000440 (1088)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- AVX-512 ZMM_Hi256 features (0xd/6):
- AVX-512 ZMM_Hi256 save state byte size = 0x00000200 (512)
- AVX-512 ZMM_Hi256 save state byte offset = 0x00000480 (1152)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- AVX-512 Hi16_ZMM features (0xd/7):
- AVX-512 Hi16_ZMM save state byte size = 0x00000400 (1024)
- AVX-512 Hi16_ZMM save state byte offset = 0x00000680 (1664)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- PKRU features (0xd/9):
- PKRU save state byte size = 0x00000008 (8)
- PKRU save state byte offset = 0x00000a80 (2688)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- Quality of Service Monitoring Resource Type (0xf/0):
- Maximum range of RMID = 0
- supports L3 cache QoS monitoring = false
- Resource Director Technology Allocation (0x10/0):
- L3 cache allocation technology supported = false
- L2 cache allocation technology supported = false
- memory bandwidth allocation supported = false
- 0x00000011 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
- Software Guard Extensions (SGX) capability (0x12/0):
- SGX1 supported = false
- SGX2 supported = false
- SGX ENCLV E*VIRTCHILD, ESETCONTEXT = false
- SGX ENCLS ETRACKC, ERDINFO, ELDBC, ELDUC = false
- MISCSELECT.EXINFO supported: #PF & #GP = false
- MISCSELECT.CPINFO supported: #CP = false
- MaxEnclaveSize_Not64 (log2) = 0x0 (0)
- MaxEnclaveSize_64 (log2) = 0x0 (0)
- 0x00000013 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
- Intel Processor Trace (0x14):
- IA32_RTIT_CR3_MATCH is accessible = false
- configurable PSB & cycle-accurate = false
- IP & TraceStop filtering; PT preserve = false
- MTC timing packet; suppress COFI-based = false
- PTWRITE support = false
- power event trace support = false
- ToPA output scheme support = false
- ToPA can hold many output entries = false
- single-range output scheme support = false
- output to trace transport = false
- IP payloads have LIP values & CS = false
- Time Stamp Counter/Core Crystal Clock Information (0x15):
- TSC/clock ratio = 0/0
- nominal core crystal clock = 0 Hz
- Processor Frequency Information (0x16):
- Core Base Frequency (MHz) = 0x0 (0)
- Core Maximum Frequency (MHz) = 0x0 (0)
- Bus (Reference) Frequency (MHz) = 0x0 (0)
- hypervisor_id = "KVMKVMKVM "
- hypervisor features (0x40000001/eax):
- kvmclock available at MSR 0x11 = true
- delays unnecessary for PIO ops = true
- mmu_op = false
- kvmclock available at MSR 0x4b564d00 = true
- async pf enable available by MSR = true
- steal clock supported = true
- guest EOI optimization enabled = true
- guest spinlock optimization enabled = true
- guest TLB flush optimization enabled = true
- async PF VM exit enable available by MSR = false
- guest send IPI optimization enabled = true
- host HLT poll disable at MSR 0x4b564d05 = true
- guest sched yield optimization enabled = true
- guest uses intrs for page ready APF evs = false
- stable: no guest per-cpu warps expected = true
- hypervisor features (0x40000001/edx):
- realtime hint: no unbound preemption = true
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = true
- 3DNow! PREFETCH/PREFETCHW instructions = true
- brand = "Intel(R) Xeon(R) Platinum 8275CL CPU @ 3.00GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0xff (255)
- instruction associativity = 0x1 (1)
- data # entries = 0xff (255)
- data associativity = 0x1 (1)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0xff (255)
- instruction associativity = 0x1 (1)
- data # entries = 0xff (255)
- data associativity = 0x1 (1)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x1 (1)
- associativity = 0x2 (2)
- size (KB) = 0x40 (64)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x1 (1)
- associativity = 0x2 (2)
- size (KB) = 0x40 (64)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x200 (512)
- instruction associativity = 4-way (4)
- data # entries = 0x200 (512)
- data associativity = 4-way (4)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x1 (1)
- associativity = 16-way (8)
- size (KB) = 0x200 (512)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x1 (1)
- associativity = 16-way (8)
- size (in 512KB units) = 0x20 (32)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = false
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = true
- IBRS: indirect branch restr speculation = true
- STIBP: 1 thr indirect branch predictor = true
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = true
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = none
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=0 SMT_width=0
- (APIC synth): PKG_ID=1 CORE_ID=0 SMT_ID=0
- (uarch synth) = Intel Cascade Lake {Skylake}, 14nm
- (synth) = Intel Scalable (2nd Gen) Bronze/Silver/Gold/Platinum (Cascade Lake B1/L1/R1) {Skylake}, 14nm
- CPU 2:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0x5 (5)
- stepping id = 0x7 (7)
- extended family = 0x0 (0)
- extended model = 0x5 (5)
- (family synth) = 0x6 (6)
- (model synth) = 0x55 (85)
- (simple synth) = Intel Core (unknown type) (Skylake / Skylake-X / Cascade Lake / Cascade Lake-X) {Skylake}, 14nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x2 (2)
- maximum IDs for CPUs in pkg = 0x0 (0)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = false
- ACPI: thermal monitor and clock ctrl = false
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = false
- TM: therm. monitor = false
- IA64 = false
- PBE: pending break event = false
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = false
- MONITOR/MWAIT = false
- CPL-qualified debug store = false
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = false
- Enhanced Intel SpeedStep Technology = false
- TM2: thermal monitor 2 = false
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = true
- CMPXCHG16B instruction = true
- xTPR disable = false
- PDCM: perfmon and debug = false
- PCID: process context identifiers = true
- DCA: direct cache access = false
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = true
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = true
- cache and TLB information (2):
- 0x4d: L3 cache: 16M, 16-way, 64 byte lines
- 0x7d: L2 cache: 2M, 8-way, 64 byte lines
- 0x30: L1 cache: 32K, 8-way, 64 byte lines
- 0x2c: L1 data cache: 32K, 8-way, 64 byte lines
- processor serial number = 0005-0657-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x0 (0)
- maximum IDs for cores in pkg = 0x0 (0)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = true
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x0 (0)
- maximum IDs for cores in pkg = 0x0 (0)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = true
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x0 (0)
- maximum IDs for cores in pkg = 0x0 (0)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x10 (16)
- number of sets = 0x1000 (4096)
- WBINVD/INVD acts on lower caches = true
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 4096
- (size synth) = 4194304 (4 MB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x0 (0)
- maximum IDs for cores in pkg = 0x0 (0)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x10 (16)
- number of sets = 0x4000 (16384)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 16384
- (size synth) = 16777216 (16 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x0 (0)
- largest monitor-line size (bytes) = 0x0 (0)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x0 (0)
- number of C2 sub C-states using MWAIT = 0x0 (0)
- number of C3 sub C-states using MWAIT = 0x0 (0)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = false
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = false
- ECMD extended clock modulation duty = false
- PTM package thermal management = false
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x0 (0)
- hardware coordination feedback = false
- ACNT2 available = false
- performance-energy bias capability = false
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = true
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = true
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = true
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = true
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = true
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = true
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = true
- AVX512DQ: double & quadword instructions = true
- RDSEED instruction = true
- ADX instructions = true
- SMAP: supervisor mode access prevention = true
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = true
- CLWB instruction = true
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = true
- SHA instructions = false
- AVX512BW: byte & word instructions = true
- AVX512VL: vector length = true
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = true
- PKU protection keys for user-mode = true
- OSPKE CR4.PKE and RDPKRU/WRPKRU = true
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = true
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = true
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = true
- STIBP: 1 thr indirect branch predictor = true
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = true
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = true
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 0
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x2 (2)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 2
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x0 (0)
- number of logical processors at level = 0x1 (1)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x0 (0)
- number of logical processors at level = 0x1 (1)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x000002ff
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = true
- XCR0 supported: MPX BNDCSR = true
- XCR0 supported: AVX-512 opmask = true
- XCR0 supported: AVX-512 ZMM_Hi256 = true
- XCR0 supported: AVX-512 Hi16_ZMM = true
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = true
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000a88 (2696)
- bytes required by XSAVE/XRSTOR area = 0x00000a88 (2696)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = true
- XGETBV instruction = true
- XSAVES/XRSTORS instructions = true
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000a08 (2568)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- MPX BNDREGS features (0xd/3):
- MPX BNDREGS save state byte size = 0x00000040 (64)
- MPX BNDREGS save state byte offset = 0x000003c0 (960)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- MPX BNDCSR features (0xd/4):
- MPX BNDCSR save state byte size = 0x00000040 (64)
- MPX BNDCSR save state byte offset = 0x00000400 (1024)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- AVX-512 opmask features (0xd/5):
- AVX-512 opmask save state byte size = 0x00000040 (64)
- AVX-512 opmask save state byte offset = 0x00000440 (1088)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- AVX-512 ZMM_Hi256 features (0xd/6):
- AVX-512 ZMM_Hi256 save state byte size = 0x00000200 (512)
- AVX-512 ZMM_Hi256 save state byte offset = 0x00000480 (1152)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- AVX-512 Hi16_ZMM features (0xd/7):
- AVX-512 Hi16_ZMM save state byte size = 0x00000400 (1024)
- AVX-512 Hi16_ZMM save state byte offset = 0x00000680 (1664)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- PKRU features (0xd/9):
- PKRU save state byte size = 0x00000008 (8)
- PKRU save state byte offset = 0x00000a80 (2688)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- Quality of Service Monitoring Resource Type (0xf/0):
- Maximum range of RMID = 0
- supports L3 cache QoS monitoring = false
- Resource Director Technology Allocation (0x10/0):
- L3 cache allocation technology supported = false
- L2 cache allocation technology supported = false
- memory bandwidth allocation supported = false
- 0x00000011 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
- Software Guard Extensions (SGX) capability (0x12/0):
- SGX1 supported = false
- SGX2 supported = false
- SGX ENCLV E*VIRTCHILD, ESETCONTEXT = false
- SGX ENCLS ETRACKC, ERDINFO, ELDBC, ELDUC = false
- MISCSELECT.EXINFO supported: #PF & #GP = false
- MISCSELECT.CPINFO supported: #CP = false
- MaxEnclaveSize_Not64 (log2) = 0x0 (0)
- MaxEnclaveSize_64 (log2) = 0x0 (0)
- 0x00000013 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
- Intel Processor Trace (0x14):
- IA32_RTIT_CR3_MATCH is accessible = false
- configurable PSB & cycle-accurate = false
- IP & TraceStop filtering; PT preserve = false
- MTC timing packet; suppress COFI-based = false
- PTWRITE support = false
- power event trace support = false
- ToPA output scheme support = false
- ToPA can hold many output entries = false
- single-range output scheme support = false
- output to trace transport = false
- IP payloads have LIP values & CS = false
- Time Stamp Counter/Core Crystal Clock Information (0x15):
- TSC/clock ratio = 0/0
- nominal core crystal clock = 0 Hz
- Processor Frequency Information (0x16):
- Core Base Frequency (MHz) = 0x0 (0)
- Core Maximum Frequency (MHz) = 0x0 (0)
- Bus (Reference) Frequency (MHz) = 0x0 (0)
- hypervisor_id = "KVMKVMKVM "
- hypervisor features (0x40000001/eax):
- kvmclock available at MSR 0x11 = true
- delays unnecessary for PIO ops = true
- mmu_op = false
- kvmclock available at MSR 0x4b564d00 = true
- async pf enable available by MSR = true
- steal clock supported = true
- guest EOI optimization enabled = true
- guest spinlock optimization enabled = true
- guest TLB flush optimization enabled = true
- async PF VM exit enable available by MSR = false
- guest send IPI optimization enabled = true
- host HLT poll disable at MSR 0x4b564d05 = true
- guest sched yield optimization enabled = true
- guest uses intrs for page ready APF evs = false
- stable: no guest per-cpu warps expected = true
- hypervisor features (0x40000001/edx):
- realtime hint: no unbound preemption = true
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = true
- 3DNow! PREFETCH/PREFETCHW instructions = true
- brand = "Intel(R) Xeon(R) Platinum 8275CL CPU @ 3.00GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0xff (255)
- instruction associativity = 0x1 (1)
- data # entries = 0xff (255)
- data associativity = 0x1 (1)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0xff (255)
- instruction associativity = 0x1 (1)
- data # entries = 0xff (255)
- data associativity = 0x1 (1)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x1 (1)
- associativity = 0x2 (2)
- size (KB) = 0x40 (64)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x1 (1)
- associativity = 0x2 (2)
- size (KB) = 0x40 (64)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x200 (512)
- instruction associativity = 4-way (4)
- data # entries = 0x200 (512)
- data associativity = 4-way (4)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x1 (1)
- associativity = 16-way (8)
- size (KB) = 0x200 (512)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x1 (1)
- associativity = 16-way (8)
- size (in 512KB units) = 0x20 (32)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = false
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = true
- IBRS: indirect branch restr speculation = true
- STIBP: 1 thr indirect branch predictor = true
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = true
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = none
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=0 SMT_width=0
- (APIC synth): PKG_ID=2 CORE_ID=0 SMT_ID=0
- (uarch synth) = Intel Cascade Lake {Skylake}, 14nm
- (synth) = Intel Scalable (2nd Gen) Bronze/Silver/Gold/Platinum (Cascade Lake B1/L1/R1) {Skylake}, 14nm
- CPU 3:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0x5 (5)
- stepping id = 0x7 (7)
- extended family = 0x0 (0)
- extended model = 0x5 (5)
- (family synth) = 0x6 (6)
- (model synth) = 0x55 (85)
- (simple synth) = Intel Core (unknown type) (Skylake / Skylake-X / Cascade Lake / Cascade Lake-X) {Skylake}, 14nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x3 (3)
- maximum IDs for CPUs in pkg = 0x0 (0)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = false
- ACPI: thermal monitor and clock ctrl = false
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = false
- TM: therm. monitor = false
- IA64 = false
- PBE: pending break event = false
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = false
- MONITOR/MWAIT = false
- CPL-qualified debug store = false
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = false
- Enhanced Intel SpeedStep Technology = false
- TM2: thermal monitor 2 = false
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = true
- CMPXCHG16B instruction = true
- xTPR disable = false
- PDCM: perfmon and debug = false
- PCID: process context identifiers = true
- DCA: direct cache access = false
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = true
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = true
- cache and TLB information (2):
- 0x4d: L3 cache: 16M, 16-way, 64 byte lines
- 0x7d: L2 cache: 2M, 8-way, 64 byte lines
- 0x30: L1 cache: 32K, 8-way, 64 byte lines
- 0x2c: L1 data cache: 32K, 8-way, 64 byte lines
- processor serial number = 0005-0657-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x0 (0)
- maximum IDs for cores in pkg = 0x0 (0)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = true
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x0 (0)
- maximum IDs for cores in pkg = 0x0 (0)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = true
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x0 (0)
- maximum IDs for cores in pkg = 0x0 (0)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x10 (16)
- number of sets = 0x1000 (4096)
- WBINVD/INVD acts on lower caches = true
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 4096
- (size synth) = 4194304 (4 MB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x0 (0)
- maximum IDs for cores in pkg = 0x0 (0)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x10 (16)
- number of sets = 0x4000 (16384)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 16384
- (size synth) = 16777216 (16 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x0 (0)
- largest monitor-line size (bytes) = 0x0 (0)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x0 (0)
- number of C2 sub C-states using MWAIT = 0x0 (0)
- number of C3 sub C-states using MWAIT = 0x0 (0)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = false
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = false
- ECMD extended clock modulation duty = false
- PTM package thermal management = false
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x0 (0)
- hardware coordination feedback = false
- ACNT2 available = false
- performance-energy bias capability = false
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = true
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = true
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = true
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = true
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = true
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = true
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = true
- AVX512DQ: double & quadword instructions = true
- RDSEED instruction = true
- ADX instructions = true
- SMAP: supervisor mode access prevention = true
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = true
- CLWB instruction = true
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = true
- SHA instructions = false
- AVX512BW: byte & word instructions = true
- AVX512VL: vector length = true
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = true
- PKU protection keys for user-mode = true
- OSPKE CR4.PKE and RDPKRU/WRPKRU = true
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = true
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = true
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = true
- STIBP: 1 thr indirect branch predictor = true
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = true
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = true
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 0
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x2 (2)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 3
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x0 (0)
- number of logical processors at level = 0x1 (1)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x0 (0)
- number of logical processors at level = 0x1 (1)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x000002ff
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = true
- XCR0 supported: MPX BNDCSR = true
- XCR0 supported: AVX-512 opmask = true
- XCR0 supported: AVX-512 ZMM_Hi256 = true
- XCR0 supported: AVX-512 Hi16_ZMM = true
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = true
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000a88 (2696)
- bytes required by XSAVE/XRSTOR area = 0x00000a88 (2696)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = true
- XGETBV instruction = true
- XSAVES/XRSTORS instructions = true
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000a08 (2568)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- MPX BNDREGS features (0xd/3):
- MPX BNDREGS save state byte size = 0x00000040 (64)
- MPX BNDREGS save state byte offset = 0x000003c0 (960)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- MPX BNDCSR features (0xd/4):
- MPX BNDCSR save state byte size = 0x00000040 (64)
- MPX BNDCSR save state byte offset = 0x00000400 (1024)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- AVX-512 opmask features (0xd/5):
- AVX-512 opmask save state byte size = 0x00000040 (64)
- AVX-512 opmask save state byte offset = 0x00000440 (1088)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- AVX-512 ZMM_Hi256 features (0xd/6):
- AVX-512 ZMM_Hi256 save state byte size = 0x00000200 (512)
- AVX-512 ZMM_Hi256 save state byte offset = 0x00000480 (1152)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- AVX-512 Hi16_ZMM features (0xd/7):
- AVX-512 Hi16_ZMM save state byte size = 0x00000400 (1024)
- AVX-512 Hi16_ZMM save state byte offset = 0x00000680 (1664)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- PKRU features (0xd/9):
- PKRU save state byte size = 0x00000008 (8)
- PKRU save state byte offset = 0x00000a80 (2688)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- Quality of Service Monitoring Resource Type (0xf/0):
- Maximum range of RMID = 0
- supports L3 cache QoS monitoring = false
- Resource Director Technology Allocation (0x10/0):
- L3 cache allocation technology supported = false
- L2 cache allocation technology supported = false
- memory bandwidth allocation supported = false
- 0x00000011 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
- Software Guard Extensions (SGX) capability (0x12/0):
- SGX1 supported = false
- SGX2 supported = false
- SGX ENCLV E*VIRTCHILD, ESETCONTEXT = false
- SGX ENCLS ETRACKC, ERDINFO, ELDBC, ELDUC = false
- MISCSELECT.EXINFO supported: #PF & #GP = false
- MISCSELECT.CPINFO supported: #CP = false
- MaxEnclaveSize_Not64 (log2) = 0x0 (0)
- MaxEnclaveSize_64 (log2) = 0x0 (0)
- 0x00000013 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
- Intel Processor Trace (0x14):
- IA32_RTIT_CR3_MATCH is accessible = false
- configurable PSB & cycle-accurate = false
- IP & TraceStop filtering; PT preserve = false
- MTC timing packet; suppress COFI-based = false
- PTWRITE support = false
- power event trace support = false
- ToPA output scheme support = false
- ToPA can hold many output entries = false
- single-range output scheme support = false
- output to trace transport = false
- IP payloads have LIP values & CS = false
- Time Stamp Counter/Core Crystal Clock Information (0x15):
- TSC/clock ratio = 0/0
- nominal core crystal clock = 0 Hz
- Processor Frequency Information (0x16):
- Core Base Frequency (MHz) = 0x0 (0)
- Core Maximum Frequency (MHz) = 0x0 (0)
- Bus (Reference) Frequency (MHz) = 0x0 (0)
- hypervisor_id = "KVMKVMKVM "
- hypervisor features (0x40000001/eax):
- kvmclock available at MSR 0x11 = true
- delays unnecessary for PIO ops = true
- mmu_op = false
- kvmclock available at MSR 0x4b564d00 = true
- async pf enable available by MSR = true
- steal clock supported = true
- guest EOI optimization enabled = true
- guest spinlock optimization enabled = true
- guest TLB flush optimization enabled = true
- async PF VM exit enable available by MSR = false
- guest send IPI optimization enabled = true
- host HLT poll disable at MSR 0x4b564d05 = true
- guest sched yield optimization enabled = true
- guest uses intrs for page ready APF evs = false
- stable: no guest per-cpu warps expected = true
- hypervisor features (0x40000001/edx):
- realtime hint: no unbound preemption = true
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = true
- 3DNow! PREFETCH/PREFETCHW instructions = true
- brand = "Intel(R) Xeon(R) Platinum 8275CL CPU @ 3.00GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0xff (255)
- instruction associativity = 0x1 (1)
- data # entries = 0xff (255)
- data associativity = 0x1 (1)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0xff (255)
- instruction associativity = 0x1 (1)
- data # entries = 0xff (255)
- data associativity = 0x1 (1)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x1 (1)
- associativity = 0x2 (2)
- size (KB) = 0x40 (64)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x1 (1)
- associativity = 0x2 (2)
- size (KB) = 0x40 (64)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x200 (512)
- instruction associativity = 4-way (4)
- data # entries = 0x200 (512)
- data associativity = 4-way (4)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x1 (1)
- associativity = 16-way (8)
- size (KB) = 0x200 (512)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x1 (1)
- associativity = 16-way (8)
- size (in 512KB units) = 0x20 (32)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = false
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = true
- IBRS: indirect branch restr speculation = true
- STIBP: 1 thr indirect branch predictor = true
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = true
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = none
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=0 SMT_width=0
- (APIC synth): PKG_ID=3 CORE_ID=0 SMT_ID=0
- (uarch synth) = Intel Cascade Lake {Skylake}, 14nm
- (synth) = Intel Scalable (2nd Gen) Bronze/Silver/Gold/Platinum (Cascade Lake B1/L1/R1) {Skylake}, 14nm
- CPU 4:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0x5 (5)
- stepping id = 0x7 (7)
- extended family = 0x0 (0)
- extended model = 0x5 (5)
- (family synth) = 0x6 (6)
- (model synth) = 0x55 (85)
- (simple synth) = Intel Core (unknown type) (Skylake / Skylake-X / Cascade Lake / Cascade Lake-X) {Skylake}, 14nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x4 (4)
- maximum IDs for CPUs in pkg = 0x0 (0)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = false
- ACPI: thermal monitor and clock ctrl = false
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = false
- TM: therm. monitor = false
- IA64 = false
- PBE: pending break event = false
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = false
- MONITOR/MWAIT = false
- CPL-qualified debug store = false
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = false
- Enhanced Intel SpeedStep Technology = false
- TM2: thermal monitor 2 = false
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = true
- CMPXCHG16B instruction = true
- xTPR disable = false
- PDCM: perfmon and debug = false
- PCID: process context identifiers = true
- DCA: direct cache access = false
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = true
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = true
- cache and TLB information (2):
- 0x4d: L3 cache: 16M, 16-way, 64 byte lines
- 0x7d: L2 cache: 2M, 8-way, 64 byte lines
- 0x30: L1 cache: 32K, 8-way, 64 byte lines
- 0x2c: L1 data cache: 32K, 8-way, 64 byte lines
- processor serial number = 0005-0657-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x0 (0)
- maximum IDs for cores in pkg = 0x0 (0)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = true
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x0 (0)
- maximum IDs for cores in pkg = 0x0 (0)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = true
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x0 (0)
- maximum IDs for cores in pkg = 0x0 (0)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x10 (16)
- number of sets = 0x1000 (4096)
- WBINVD/INVD acts on lower caches = true
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 4096
- (size synth) = 4194304 (4 MB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x0 (0)
- maximum IDs for cores in pkg = 0x0 (0)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x10 (16)
- number of sets = 0x4000 (16384)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 16384
- (size synth) = 16777216 (16 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x0 (0)
- largest monitor-line size (bytes) = 0x0 (0)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x0 (0)
- number of C2 sub C-states using MWAIT = 0x0 (0)
- number of C3 sub C-states using MWAIT = 0x0 (0)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = false
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = false
- ECMD extended clock modulation duty = false
- PTM package thermal management = false
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x0 (0)
- hardware coordination feedback = false
- ACNT2 available = false
- performance-energy bias capability = false
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = true
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = true
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = true
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = true
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = true
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = true
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = true
- AVX512DQ: double & quadword instructions = true
- RDSEED instruction = true
- ADX instructions = true
- SMAP: supervisor mode access prevention = true
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = true
- CLWB instruction = true
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = true
- SHA instructions = false
- AVX512BW: byte & word instructions = true
- AVX512VL: vector length = true
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = true
- PKU protection keys for user-mode = true
- OSPKE CR4.PKE and RDPKRU/WRPKRU = true
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = true
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = true
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = true
- STIBP: 1 thr indirect branch predictor = true
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = true
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = true
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 0
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x2 (2)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 4
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x0 (0)
- number of logical processors at level = 0x1 (1)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x0 (0)
- number of logical processors at level = 0x1 (1)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x000002ff
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = true
- XCR0 supported: MPX BNDCSR = true
- XCR0 supported: AVX-512 opmask = true
- XCR0 supported: AVX-512 ZMM_Hi256 = true
- XCR0 supported: AVX-512 Hi16_ZMM = true
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = true
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000a88 (2696)
- bytes required by XSAVE/XRSTOR area = 0x00000a88 (2696)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = true
- XGETBV instruction = true
- XSAVES/XRSTORS instructions = true
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000a08 (2568)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- MPX BNDREGS features (0xd/3):
- MPX BNDREGS save state byte size = 0x00000040 (64)
- MPX BNDREGS save state byte offset = 0x000003c0 (960)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- MPX BNDCSR features (0xd/4):
- MPX BNDCSR save state byte size = 0x00000040 (64)
- MPX BNDCSR save state byte offset = 0x00000400 (1024)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- AVX-512 opmask features (0xd/5):
- AVX-512 opmask save state byte size = 0x00000040 (64)
- AVX-512 opmask save state byte offset = 0x00000440 (1088)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- AVX-512 ZMM_Hi256 features (0xd/6):
- AVX-512 ZMM_Hi256 save state byte size = 0x00000200 (512)
- AVX-512 ZMM_Hi256 save state byte offset = 0x00000480 (1152)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- AVX-512 Hi16_ZMM features (0xd/7):
- AVX-512 Hi16_ZMM save state byte size = 0x00000400 (1024)
- AVX-512 Hi16_ZMM save state byte offset = 0x00000680 (1664)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- PKRU features (0xd/9):
- PKRU save state byte size = 0x00000008 (8)
- PKRU save state byte offset = 0x00000a80 (2688)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- Quality of Service Monitoring Resource Type (0xf/0):
- Maximum range of RMID = 0
- supports L3 cache QoS monitoring = false
- Resource Director Technology Allocation (0x10/0):
- L3 cache allocation technology supported = false
- L2 cache allocation technology supported = false
- memory bandwidth allocation supported = false
- 0x00000011 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
- Software Guard Extensions (SGX) capability (0x12/0):
- SGX1 supported = false
- SGX2 supported = false
- SGX ENCLV E*VIRTCHILD, ESETCONTEXT = false
- SGX ENCLS ETRACKC, ERDINFO, ELDBC, ELDUC = false
- MISCSELECT.EXINFO supported: #PF & #GP = false
- MISCSELECT.CPINFO supported: #CP = false
- MaxEnclaveSize_Not64 (log2) = 0x0 (0)
- MaxEnclaveSize_64 (log2) = 0x0 (0)
- 0x00000013 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
- Intel Processor Trace (0x14):
- IA32_RTIT_CR3_MATCH is accessible = false
- configurable PSB & cycle-accurate = false
- IP & TraceStop filtering; PT preserve = false
- MTC timing packet; suppress COFI-based = false
- PTWRITE support = false
- power event trace support = false
- ToPA output scheme support = false
- ToPA can hold many output entries = false
- single-range output scheme support = false
- output to trace transport = false
- IP payloads have LIP values & CS = false
- Time Stamp Counter/Core Crystal Clock Information (0x15):
- TSC/clock ratio = 0/0
- nominal core crystal clock = 0 Hz
- Processor Frequency Information (0x16):
- Core Base Frequency (MHz) = 0x0 (0)
- Core Maximum Frequency (MHz) = 0x0 (0)
- Bus (Reference) Frequency (MHz) = 0x0 (0)
- hypervisor_id = "KVMKVMKVM "
- hypervisor features (0x40000001/eax):
- kvmclock available at MSR 0x11 = true
- delays unnecessary for PIO ops = true
- mmu_op = false
- kvmclock available at MSR 0x4b564d00 = true
- async pf enable available by MSR = true
- steal clock supported = true
- guest EOI optimization enabled = true
- guest spinlock optimization enabled = true
- guest TLB flush optimization enabled = true
- async PF VM exit enable available by MSR = false
- guest send IPI optimization enabled = true
- host HLT poll disable at MSR 0x4b564d05 = true
- guest sched yield optimization enabled = true
- guest uses intrs for page ready APF evs = false
- stable: no guest per-cpu warps expected = true
- hypervisor features (0x40000001/edx):
- realtime hint: no unbound preemption = true
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = true
- 3DNow! PREFETCH/PREFETCHW instructions = true
- brand = "Intel(R) Xeon(R) Platinum 8275CL CPU @ 3.00GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0xff (255)
- instruction associativity = 0x1 (1)
- data # entries = 0xff (255)
- data associativity = 0x1 (1)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0xff (255)
- instruction associativity = 0x1 (1)
- data # entries = 0xff (255)
- data associativity = 0x1 (1)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x1 (1)
- associativity = 0x2 (2)
- size (KB) = 0x40 (64)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x1 (1)
- associativity = 0x2 (2)
- size (KB) = 0x40 (64)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x200 (512)
- instruction associativity = 4-way (4)
- data # entries = 0x200 (512)
- data associativity = 4-way (4)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x1 (1)
- associativity = 16-way (8)
- size (KB) = 0x200 (512)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x1 (1)
- associativity = 16-way (8)
- size (in 512KB units) = 0x20 (32)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = false
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = true
- IBRS: indirect branch restr speculation = true
- STIBP: 1 thr indirect branch predictor = true
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = true
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = none
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=0 SMT_width=0
- (APIC synth): PKG_ID=4 CORE_ID=0 SMT_ID=0
- (uarch synth) = Intel Cascade Lake {Skylake}, 14nm
- (synth) = Intel Scalable (2nd Gen) Bronze/Silver/Gold/Platinum (Cascade Lake B1/L1/R1) {Skylake}, 14nm
- CPU 5:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0x5 (5)
- stepping id = 0x7 (7)
- extended family = 0x0 (0)
- extended model = 0x5 (5)
- (family synth) = 0x6 (6)
- (model synth) = 0x55 (85)
- (simple synth) = Intel Core (unknown type) (Skylake / Skylake-X / Cascade Lake / Cascade Lake-X) {Skylake}, 14nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x5 (5)
- maximum IDs for CPUs in pkg = 0x0 (0)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = false
- ACPI: thermal monitor and clock ctrl = false
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = false
- TM: therm. monitor = false
- IA64 = false
- PBE: pending break event = false
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = false
- MONITOR/MWAIT = false
- CPL-qualified debug store = false
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = false
- Enhanced Intel SpeedStep Technology = false
- TM2: thermal monitor 2 = false
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = true
- CMPXCHG16B instruction = true
- xTPR disable = false
- PDCM: perfmon and debug = false
- PCID: process context identifiers = true
- DCA: direct cache access = false
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = true
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = true
- cache and TLB information (2):
- 0x4d: L3 cache: 16M, 16-way, 64 byte lines
- 0x7d: L2 cache: 2M, 8-way, 64 byte lines
- 0x30: L1 cache: 32K, 8-way, 64 byte lines
- 0x2c: L1 data cache: 32K, 8-way, 64 byte lines
- processor serial number = 0005-0657-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x0 (0)
- maximum IDs for cores in pkg = 0x0 (0)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = true
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x0 (0)
- maximum IDs for cores in pkg = 0x0 (0)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = true
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x0 (0)
- maximum IDs for cores in pkg = 0x0 (0)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x10 (16)
- number of sets = 0x1000 (4096)
- WBINVD/INVD acts on lower caches = true
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 4096
- (size synth) = 4194304 (4 MB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x0 (0)
- maximum IDs for cores in pkg = 0x0 (0)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x10 (16)
- number of sets = 0x4000 (16384)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 16384
- (size synth) = 16777216 (16 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x0 (0)
- largest monitor-line size (bytes) = 0x0 (0)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x0 (0)
- number of C2 sub C-states using MWAIT = 0x0 (0)
- number of C3 sub C-states using MWAIT = 0x0 (0)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = false
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = false
- ECMD extended clock modulation duty = false
- PTM package thermal management = false
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x0 (0)
- hardware coordination feedback = false
- ACNT2 available = false
- performance-energy bias capability = false
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = true
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = true
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = true
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = true
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = true
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = true
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = true
- AVX512DQ: double & quadword instructions = true
- RDSEED instruction = true
- ADX instructions = true
- SMAP: supervisor mode access prevention = true
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = true
- CLWB instruction = true
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = true
- SHA instructions = false
- AVX512BW: byte & word instructions = true
- AVX512VL: vector length = true
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = true
- PKU protection keys for user-mode = true
- OSPKE CR4.PKE and RDPKRU/WRPKRU = true
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = true
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = true
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = true
- STIBP: 1 thr indirect branch predictor = true
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = true
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = true
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 0
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x2 (2)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 5
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x0 (0)
- number of logical processors at level = 0x1 (1)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x0 (0)
- number of logical processors at level = 0x1 (1)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x000002ff
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = true
- XCR0 supported: MPX BNDCSR = true
- XCR0 supported: AVX-512 opmask = true
- XCR0 supported: AVX-512 ZMM_Hi256 = true
- XCR0 supported: AVX-512 Hi16_ZMM = true
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = true
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000a88 (2696)
- bytes required by XSAVE/XRSTOR area = 0x00000a88 (2696)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = true
- XGETBV instruction = true
- XSAVES/XRSTORS instructions = true
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000a08 (2568)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- MPX BNDREGS features (0xd/3):
- MPX BNDREGS save state byte size = 0x00000040 (64)
- MPX BNDREGS save state byte offset = 0x000003c0 (960)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- MPX BNDCSR features (0xd/4):
- MPX BNDCSR save state byte size = 0x00000040 (64)
- MPX BNDCSR save state byte offset = 0x00000400 (1024)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- AVX-512 opmask features (0xd/5):
- AVX-512 opmask save state byte size = 0x00000040 (64)
- AVX-512 opmask save state byte offset = 0x00000440 (1088)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- AVX-512 ZMM_Hi256 features (0xd/6):
- AVX-512 ZMM_Hi256 save state byte size = 0x00000200 (512)
- AVX-512 ZMM_Hi256 save state byte offset = 0x00000480 (1152)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- AVX-512 Hi16_ZMM features (0xd/7):
- AVX-512 Hi16_ZMM save state byte size = 0x00000400 (1024)
- AVX-512 Hi16_ZMM save state byte offset = 0x00000680 (1664)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- PKRU features (0xd/9):
- PKRU save state byte size = 0x00000008 (8)
- PKRU save state byte offset = 0x00000a80 (2688)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- Quality of Service Monitoring Resource Type (0xf/0):
- Maximum range of RMID = 0
- supports L3 cache QoS monitoring = false
- Resource Director Technology Allocation (0x10/0):
- L3 cache allocation technology supported = false
- L2 cache allocation technology supported = false
- memory bandwidth allocation supported = false
- 0x00000011 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
- Software Guard Extensions (SGX) capability (0x12/0):
- SGX1 supported = false
- SGX2 supported = false
- SGX ENCLV E*VIRTCHILD, ESETCONTEXT = false
- SGX ENCLS ETRACKC, ERDINFO, ELDBC, ELDUC = false
- MISCSELECT.EXINFO supported: #PF & #GP = false
- MISCSELECT.CPINFO supported: #CP = false
- MaxEnclaveSize_Not64 (log2) = 0x0 (0)
- MaxEnclaveSize_64 (log2) = 0x0 (0)
- 0x00000013 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
- Intel Processor Trace (0x14):
- IA32_RTIT_CR3_MATCH is accessible = false
- configurable PSB & cycle-accurate = false
- IP & TraceStop filtering; PT preserve = false
- MTC timing packet; suppress COFI-based = false
- PTWRITE support = false
- power event trace support = false
- ToPA output scheme support = false
- ToPA can hold many output entries = false
- single-range output scheme support = false
- output to trace transport = false
- IP payloads have LIP values & CS = false
- Time Stamp Counter/Core Crystal Clock Information (0x15):
- TSC/clock ratio = 0/0
- nominal core crystal clock = 0 Hz
- Processor Frequency Information (0x16):
- Core Base Frequency (MHz) = 0x0 (0)
- Core Maximum Frequency (MHz) = 0x0 (0)
- Bus (Reference) Frequency (MHz) = 0x0 (0)
- hypervisor_id = "KVMKVMKVM "
- hypervisor features (0x40000001/eax):
- kvmclock available at MSR 0x11 = true
- delays unnecessary for PIO ops = true
- mmu_op = false
- kvmclock available at MSR 0x4b564d00 = true
- async pf enable available by MSR = true
- steal clock supported = true
- guest EOI optimization enabled = true
- guest spinlock optimization enabled = true
- guest TLB flush optimization enabled = true
- async PF VM exit enable available by MSR = false
- guest send IPI optimization enabled = true
- host HLT poll disable at MSR 0x4b564d05 = true
- guest sched yield optimization enabled = true
- guest uses intrs for page ready APF evs = false
- stable: no guest per-cpu warps expected = true
- hypervisor features (0x40000001/edx):
- realtime hint: no unbound preemption = true
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = true
- 3DNow! PREFETCH/PREFETCHW instructions = true
- brand = "Intel(R) Xeon(R) Platinum 8275CL CPU @ 3.00GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0xff (255)
- instruction associativity = 0x1 (1)
- data # entries = 0xff (255)
- data associativity = 0x1 (1)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0xff (255)
- instruction associativity = 0x1 (1)
- data # entries = 0xff (255)
- data associativity = 0x1 (1)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x1 (1)
- associativity = 0x2 (2)
- size (KB) = 0x40 (64)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x1 (1)
- associativity = 0x2 (2)
- size (KB) = 0x40 (64)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x200 (512)
- instruction associativity = 4-way (4)
- data # entries = 0x200 (512)
- data associativity = 4-way (4)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x1 (1)
- associativity = 16-way (8)
- size (KB) = 0x200 (512)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x1 (1)
- associativity = 16-way (8)
- size (in 512KB units) = 0x20 (32)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = false
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = true
- IBRS: indirect branch restr speculation = true
- STIBP: 1 thr indirect branch predictor = true
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = true
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = none
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=0 SMT_width=0
- (APIC synth): PKG_ID=5 CORE_ID=0 SMT_ID=0
- (uarch synth) = Intel Cascade Lake {Skylake}, 14nm
- (synth) = Intel Scalable (2nd Gen) Bronze/Silver/Gold/Platinum (Cascade Lake B1/L1/R1) {Skylake}, 14nm
- CPU 6:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0x5 (5)
- stepping id = 0x7 (7)
- extended family = 0x0 (0)
- extended model = 0x5 (5)
- (family synth) = 0x6 (6)
- (model synth) = 0x55 (85)
- (simple synth) = Intel Core (unknown type) (Skylake / Skylake-X / Cascade Lake / Cascade Lake-X) {Skylake}, 14nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x6 (6)
- maximum IDs for CPUs in pkg = 0x0 (0)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = false
- ACPI: thermal monitor and clock ctrl = false
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = false
- TM: therm. monitor = false
- IA64 = false
- PBE: pending break event = false
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = false
- MONITOR/MWAIT = false
- CPL-qualified debug store = false
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = false
- Enhanced Intel SpeedStep Technology = false
- TM2: thermal monitor 2 = false
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = true
- CMPXCHG16B instruction = true
- xTPR disable = false
- PDCM: perfmon and debug = false
- PCID: process context identifiers = true
- DCA: direct cache access = false
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = true
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = true
- cache and TLB information (2):
- 0x4d: L3 cache: 16M, 16-way, 64 byte lines
- 0x7d: L2 cache: 2M, 8-way, 64 byte lines
- 0x30: L1 cache: 32K, 8-way, 64 byte lines
- 0x2c: L1 data cache: 32K, 8-way, 64 byte lines
- processor serial number = 0005-0657-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x0 (0)
- maximum IDs for cores in pkg = 0x0 (0)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = true
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x0 (0)
- maximum IDs for cores in pkg = 0x0 (0)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = true
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x0 (0)
- maximum IDs for cores in pkg = 0x0 (0)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x10 (16)
- number of sets = 0x1000 (4096)
- WBINVD/INVD acts on lower caches = true
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 4096
- (size synth) = 4194304 (4 MB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x0 (0)
- maximum IDs for cores in pkg = 0x0 (0)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x10 (16)
- number of sets = 0x4000 (16384)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 16384
- (size synth) = 16777216 (16 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x0 (0)
- largest monitor-line size (bytes) = 0x0 (0)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x0 (0)
- number of C2 sub C-states using MWAIT = 0x0 (0)
- number of C3 sub C-states using MWAIT = 0x0 (0)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = false
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = false
- ECMD extended clock modulation duty = false
- PTM package thermal management = false
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x0 (0)
- hardware coordination feedback = false
- ACNT2 available = false
- performance-energy bias capability = false
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = true
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = true
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = true
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = true
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = true
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = true
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = true
- AVX512DQ: double & quadword instructions = true
- RDSEED instruction = true
- ADX instructions = true
- SMAP: supervisor mode access prevention = true
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = true
- CLWB instruction = true
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = true
- SHA instructions = false
- AVX512BW: byte & word instructions = true
- AVX512VL: vector length = true
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = true
- PKU protection keys for user-mode = true
- OSPKE CR4.PKE and RDPKRU/WRPKRU = true
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = true
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = true
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = true
- STIBP: 1 thr indirect branch predictor = true
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = true
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = true
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 0
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x2 (2)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 6
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x0 (0)
- number of logical processors at level = 0x1 (1)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x0 (0)
- number of logical processors at level = 0x1 (1)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x000002ff
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = true
- XCR0 supported: MPX BNDCSR = true
- XCR0 supported: AVX-512 opmask = true
- XCR0 supported: AVX-512 ZMM_Hi256 = true
- XCR0 supported: AVX-512 Hi16_ZMM = true
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = true
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000a88 (2696)
- bytes required by XSAVE/XRSTOR area = 0x00000a88 (2696)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = true
- XGETBV instruction = true
- XSAVES/XRSTORS instructions = true
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000a08 (2568)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- MPX BNDREGS features (0xd/3):
- MPX BNDREGS save state byte size = 0x00000040 (64)
- MPX BNDREGS save state byte offset = 0x000003c0 (960)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- MPX BNDCSR features (0xd/4):
- MPX BNDCSR save state byte size = 0x00000040 (64)
- MPX BNDCSR save state byte offset = 0x00000400 (1024)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- AVX-512 opmask features (0xd/5):
- AVX-512 opmask save state byte size = 0x00000040 (64)
- AVX-512 opmask save state byte offset = 0x00000440 (1088)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- AVX-512 ZMM_Hi256 features (0xd/6):
- AVX-512 ZMM_Hi256 save state byte size = 0x00000200 (512)
- AVX-512 ZMM_Hi256 save state byte offset = 0x00000480 (1152)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- AVX-512 Hi16_ZMM features (0xd/7):
- AVX-512 Hi16_ZMM save state byte size = 0x00000400 (1024)
- AVX-512 Hi16_ZMM save state byte offset = 0x00000680 (1664)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- PKRU features (0xd/9):
- PKRU save state byte size = 0x00000008 (8)
- PKRU save state byte offset = 0x00000a80 (2688)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- Quality of Service Monitoring Resource Type (0xf/0):
- Maximum range of RMID = 0
- supports L3 cache QoS monitoring = false
- Resource Director Technology Allocation (0x10/0):
- L3 cache allocation technology supported = false
- L2 cache allocation technology supported = false
- memory bandwidth allocation supported = false
- 0x00000011 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
- Software Guard Extensions (SGX) capability (0x12/0):
- SGX1 supported = false
- SGX2 supported = false
- SGX ENCLV E*VIRTCHILD, ESETCONTEXT = false
- SGX ENCLS ETRACKC, ERDINFO, ELDBC, ELDUC = false
- MISCSELECT.EXINFO supported: #PF & #GP = false
- MISCSELECT.CPINFO supported: #CP = false
- MaxEnclaveSize_Not64 (log2) = 0x0 (0)
- MaxEnclaveSize_64 (log2) = 0x0 (0)
- 0x00000013 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
- Intel Processor Trace (0x14):
- IA32_RTIT_CR3_MATCH is accessible = false
- configurable PSB & cycle-accurate = false
- IP & TraceStop filtering; PT preserve = false
- MTC timing packet; suppress COFI-based = false
- PTWRITE support = false
- power event trace support = false
- ToPA output scheme support = false
- ToPA can hold many output entries = false
- single-range output scheme support = false
- output to trace transport = false
- IP payloads have LIP values & CS = false
- Time Stamp Counter/Core Crystal Clock Information (0x15):
- TSC/clock ratio = 0/0
- nominal core crystal clock = 0 Hz
- Processor Frequency Information (0x16):
- Core Base Frequency (MHz) = 0x0 (0)
- Core Maximum Frequency (MHz) = 0x0 (0)
- Bus (Reference) Frequency (MHz) = 0x0 (0)
- hypervisor_id = "KVMKVMKVM "
- hypervisor features (0x40000001/eax):
- kvmclock available at MSR 0x11 = true
- delays unnecessary for PIO ops = true
- mmu_op = false
- kvmclock available at MSR 0x4b564d00 = true
- async pf enable available by MSR = true
- steal clock supported = true
- guest EOI optimization enabled = true
- guest spinlock optimization enabled = true
- guest TLB flush optimization enabled = true
- async PF VM exit enable available by MSR = false
- guest send IPI optimization enabled = true
- host HLT poll disable at MSR 0x4b564d05 = true
- guest sched yield optimization enabled = true
- guest uses intrs for page ready APF evs = false
- stable: no guest per-cpu warps expected = true
- hypervisor features (0x40000001/edx):
- realtime hint: no unbound preemption = true
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = true
- 3DNow! PREFETCH/PREFETCHW instructions = true
- brand = "Intel(R) Xeon(R) Platinum 8275CL CPU @ 3.00GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0xff (255)
- instruction associativity = 0x1 (1)
- data # entries = 0xff (255)
- data associativity = 0x1 (1)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0xff (255)
- instruction associativity = 0x1 (1)
- data # entries = 0xff (255)
- data associativity = 0x1 (1)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x1 (1)
- associativity = 0x2 (2)
- size (KB) = 0x40 (64)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x1 (1)
- associativity = 0x2 (2)
- size (KB) = 0x40 (64)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x200 (512)
- instruction associativity = 4-way (4)
- data # entries = 0x200 (512)
- data associativity = 4-way (4)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x1 (1)
- associativity = 16-way (8)
- size (KB) = 0x200 (512)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x1 (1)
- associativity = 16-way (8)
- size (in 512KB units) = 0x20 (32)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = false
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = true
- IBRS: indirect branch restr speculation = true
- STIBP: 1 thr indirect branch predictor = true
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = true
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = none
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=0 SMT_width=0
- (APIC synth): PKG_ID=6 CORE_ID=0 SMT_ID=0
- (uarch synth) = Intel Cascade Lake {Skylake}, 14nm
- (synth) = Intel Scalable (2nd Gen) Bronze/Silver/Gold/Platinum (Cascade Lake B1/L1/R1) {Skylake}, 14nm
- CPU 7:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0x5 (5)
- stepping id = 0x7 (7)
- extended family = 0x0 (0)
- extended model = 0x5 (5)
- (family synth) = 0x6 (6)
- (model synth) = 0x55 (85)
- (simple synth) = Intel Core (unknown type) (Skylake / Skylake-X / Cascade Lake / Cascade Lake-X) {Skylake}, 14nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x7 (7)
- maximum IDs for CPUs in pkg = 0x0 (0)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = false
- ACPI: thermal monitor and clock ctrl = false
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = false
- TM: therm. monitor = false
- IA64 = false
- PBE: pending break event = false
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = false
- MONITOR/MWAIT = false
- CPL-qualified debug store = false
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = false
- Enhanced Intel SpeedStep Technology = false
- TM2: thermal monitor 2 = false
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = true
- CMPXCHG16B instruction = true
- xTPR disable = false
- PDCM: perfmon and debug = false
- PCID: process context identifiers = true
- DCA: direct cache access = false
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = true
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = true
- cache and TLB information (2):
- 0x4d: L3 cache: 16M, 16-way, 64 byte lines
- 0x7d: L2 cache: 2M, 8-way, 64 byte lines
- 0x30: L1 cache: 32K, 8-way, 64 byte lines
- 0x2c: L1 data cache: 32K, 8-way, 64 byte lines
- processor serial number = 0005-0657-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x0 (0)
- maximum IDs for cores in pkg = 0x0 (0)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = true
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x0 (0)
- maximum IDs for cores in pkg = 0x0 (0)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = true
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x0 (0)
- maximum IDs for cores in pkg = 0x0 (0)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x10 (16)
- number of sets = 0x1000 (4096)
- WBINVD/INVD acts on lower caches = true
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 4096
- (size synth) = 4194304 (4 MB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x0 (0)
- maximum IDs for cores in pkg = 0x0 (0)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x10 (16)
- number of sets = 0x4000 (16384)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 16384
- (size synth) = 16777216 (16 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x0 (0)
- largest monitor-line size (bytes) = 0x0 (0)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x0 (0)
- number of C2 sub C-states using MWAIT = 0x0 (0)
- number of C3 sub C-states using MWAIT = 0x0 (0)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = false
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = false
- ECMD extended clock modulation duty = false
- PTM package thermal management = false
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x0 (0)
- hardware coordination feedback = false
- ACNT2 available = false
- performance-energy bias capability = false
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = true
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = true
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = true
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = true
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = true
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = true
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = true
- AVX512DQ: double & quadword instructions = true
- RDSEED instruction = true
- ADX instructions = true
- SMAP: supervisor mode access prevention = true
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = true
- CLWB instruction = true
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = true
- SHA instructions = false
- AVX512BW: byte & word instructions = true
- AVX512VL: vector length = true
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = true
- PKU protection keys for user-mode = true
- OSPKE CR4.PKE and RDPKRU/WRPKRU = true
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = true
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = true
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = true
- STIBP: 1 thr indirect branch predictor = true
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = true
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = true
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 0
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x2 (2)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 7
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x0 (0)
- number of logical processors at level = 0x1 (1)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x0 (0)
- number of logical processors at level = 0x1 (1)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x000002ff
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = true
- XCR0 supported: MPX BNDCSR = true
- XCR0 supported: AVX-512 opmask = true
- XCR0 supported: AVX-512 ZMM_Hi256 = true
- XCR0 supported: AVX-512 Hi16_ZMM = true
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = true
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000a88 (2696)
- bytes required by XSAVE/XRSTOR area = 0x00000a88 (2696)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = true
- XGETBV instruction = true
- XSAVES/XRSTORS instructions = true
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000a08 (2568)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- MPX BNDREGS features (0xd/3):
- MPX BNDREGS save state byte size = 0x00000040 (64)
- MPX BNDREGS save state byte offset = 0x000003c0 (960)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- MPX BNDCSR features (0xd/4):
- MPX BNDCSR save state byte size = 0x00000040 (64)
- MPX BNDCSR save state byte offset = 0x00000400 (1024)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- AVX-512 opmask features (0xd/5):
- AVX-512 opmask save state byte size = 0x00000040 (64)
- AVX-512 opmask save state byte offset = 0x00000440 (1088)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- AVX-512 ZMM_Hi256 features (0xd/6):
- AVX-512 ZMM_Hi256 save state byte size = 0x00000200 (512)
- AVX-512 ZMM_Hi256 save state byte offset = 0x00000480 (1152)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- AVX-512 Hi16_ZMM features (0xd/7):
- AVX-512 Hi16_ZMM save state byte size = 0x00000400 (1024)
- AVX-512 Hi16_ZMM save state byte offset = 0x00000680 (1664)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- PKRU features (0xd/9):
- PKRU save state byte size = 0x00000008 (8)
- PKRU save state byte offset = 0x00000a80 (2688)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- Quality of Service Monitoring Resource Type (0xf/0):
- Maximum range of RMID = 0
- supports L3 cache QoS monitoring = false
- Resource Director Technology Allocation (0x10/0):
- L3 cache allocation technology supported = false
- L2 cache allocation technology supported = false
- memory bandwidth allocation supported = false
- 0x00000011 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
- Software Guard Extensions (SGX) capability (0x12/0):
- SGX1 supported = false
- SGX2 supported = false
- SGX ENCLV E*VIRTCHILD, ESETCONTEXT = false
- SGX ENCLS ETRACKC, ERDINFO, ELDBC, ELDUC = false
- MISCSELECT.EXINFO supported: #PF & #GP = false
- MISCSELECT.CPINFO supported: #CP = false
- MaxEnclaveSize_Not64 (log2) = 0x0 (0)
- MaxEnclaveSize_64 (log2) = 0x0 (0)
- 0x00000013 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
- Intel Processor Trace (0x14):
- IA32_RTIT_CR3_MATCH is accessible = false
- configurable PSB & cycle-accurate = false
- IP & TraceStop filtering; PT preserve = false
- MTC timing packet; suppress COFI-based = false
- PTWRITE support = false
- power event trace support = false
- ToPA output scheme support = false
- ToPA can hold many output entries = false
- single-range output scheme support = false
- output to trace transport = false
- IP payloads have LIP values & CS = false
- Time Stamp Counter/Core Crystal Clock Information (0x15):
- TSC/clock ratio = 0/0
- nominal core crystal clock = 0 Hz
- Processor Frequency Information (0x16):
- Core Base Frequency (MHz) = 0x0 (0)
- Core Maximum Frequency (MHz) = 0x0 (0)
- Bus (Reference) Frequency (MHz) = 0x0 (0)
- hypervisor_id = "KVMKVMKVM "
- hypervisor features (0x40000001/eax):
- kvmclock available at MSR 0x11 = true
- delays unnecessary for PIO ops = true
- mmu_op = false
- kvmclock available at MSR 0x4b564d00 = true
- async pf enable available by MSR = true
- steal clock supported = true
- guest EOI optimization enabled = true
- guest spinlock optimization enabled = true
- guest TLB flush optimization enabled = true
- async PF VM exit enable available by MSR = false
- guest send IPI optimization enabled = true
- host HLT poll disable at MSR 0x4b564d05 = true
- guest sched yield optimization enabled = true
- guest uses intrs for page ready APF evs = false
- stable: no guest per-cpu warps expected = true
- hypervisor features (0x40000001/edx):
- realtime hint: no unbound preemption = true
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = true
- 3DNow! PREFETCH/PREFETCHW instructions = true
- brand = "Intel(R) Xeon(R) Platinum 8275CL CPU @ 3.00GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0xff (255)
- instruction associativity = 0x1 (1)
- data # entries = 0xff (255)
- data associativity = 0x1 (1)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0xff (255)
- instruction associativity = 0x1 (1)
- data # entries = 0xff (255)
- data associativity = 0x1 (1)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x1 (1)
- associativity = 0x2 (2)
- size (KB) = 0x40 (64)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x1 (1)
- associativity = 0x2 (2)
- size (KB) = 0x40 (64)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x200 (512)
- instruction associativity = 4-way (4)
- data # entries = 0x200 (512)
- data associativity = 4-way (4)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x1 (1)
- associativity = 16-way (8)
- size (KB) = 0x200 (512)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x1 (1)
- associativity = 16-way (8)
- size (in 512KB units) = 0x20 (32)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = false
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = true
- IBRS: indirect branch restr speculation = true
- STIBP: 1 thr indirect branch predictor = true
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = true
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = none
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=0 SMT_width=0
- (APIC synth): PKG_ID=7 CORE_ID=0 SMT_ID=0
- (uarch synth) = Intel Cascade Lake {Skylake}, 14nm
- (synth) = Intel Scalable (2nd Gen) Bronze/Silver/Gold/Platinum (Cascade Lake B1/L1/R1) {Skylake}, 14nm
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