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Aug 27th, 2021
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  1. cpuid
  2. CPU 0:
  3. vendor_id = "GenuineIntel"
  4. version information (1/eax):
  5. processor type = primary processor (0)
  6. family = 0x6 (6)
  7. model = 0x5 (5)
  8. stepping id = 0x7 (7)
  9. extended family = 0x0 (0)
  10. extended model = 0x5 (5)
  11. (family synth) = 0x6 (6)
  12. (model synth) = 0x55 (85)
  13. (simple synth) = Intel Core (unknown type) (Skylake / Skylake-X / Cascade Lake / Cascade Lake-X) {Skylake}, 14nm
  14. miscellaneous (1/ebx):
  15. process local APIC physical ID = 0x0 (0)
  16. maximum IDs for CPUs in pkg = 0x0 (0)
  17. CLFLUSH line size = 0x8 (8)
  18. brand index = 0x0 (0)
  19. brand id = 0x00 (0): unknown
  20. feature information (1/edx):
  21. x87 FPU on chip = true
  22. VME: virtual-8086 mode enhancement = true
  23. DE: debugging extensions = true
  24. PSE: page size extensions = true
  25. TSC: time stamp counter = true
  26. RDMSR and WRMSR support = true
  27. PAE: physical address extensions = true
  28. MCE: machine check exception = true
  29. CMPXCHG8B inst. = true
  30. APIC on chip = true
  31. SYSENTER and SYSEXIT = true
  32. MTRR: memory type range registers = true
  33. PTE global bit = true
  34. MCA: machine check architecture = true
  35. CMOV: conditional move/compare instr = true
  36. PAT: page attribute table = true
  37. PSE-36: page size extension = true
  38. PSN: processor serial number = false
  39. CLFLUSH instruction = true
  40. DS: debug store = false
  41. ACPI: thermal monitor and clock ctrl = false
  42. MMX Technology = true
  43. FXSAVE/FXRSTOR = true
  44. SSE extensions = true
  45. SSE2 extensions = true
  46. SS: self snoop = true
  47. hyper-threading / multi-core supported = false
  48. TM: therm. monitor = false
  49. IA64 = false
  50. PBE: pending break event = false
  51. feature information (1/ecx):
  52. PNI/SSE3: Prescott New Instructions = true
  53. PCLMULDQ instruction = true
  54. DTES64: 64-bit debug store = false
  55. MONITOR/MWAIT = false
  56. CPL-qualified debug store = false
  57. VMX: virtual machine extensions = true
  58. SMX: safer mode extensions = false
  59. Enhanced Intel SpeedStep Technology = false
  60. TM2: thermal monitor 2 = false
  61. SSSE3 extensions = true
  62. context ID: adaptive or shared L1 data = false
  63. SDBG: IA32_DEBUG_INTERFACE = false
  64. FMA instruction = true
  65. CMPXCHG16B instruction = true
  66. xTPR disable = false
  67. PDCM: perfmon and debug = false
  68. PCID: process context identifiers = true
  69. DCA: direct cache access = false
  70. SSE4.1 extensions = true
  71. SSE4.2 extensions = true
  72. x2APIC: extended xAPIC support = true
  73. MOVBE instruction = true
  74. POPCNT instruction = true
  75. time stamp counter deadline = true
  76. AES instruction = true
  77. XSAVE/XSTOR states = true
  78. OS-enabled XSAVE/XSTOR = true
  79. AVX: advanced vector extensions = true
  80. F16C half-precision convert instruction = true
  81. RDRAND instruction = true
  82. hypervisor guest status = true
  83. cache and TLB information (2):
  84. 0x4d: L3 cache: 16M, 16-way, 64 byte lines
  85. 0x7d: L2 cache: 2M, 8-way, 64 byte lines
  86. 0x30: L1 cache: 32K, 8-way, 64 byte lines
  87. 0x2c: L1 data cache: 32K, 8-way, 64 byte lines
  88. processor serial number = 0005-0657-0000-0000-0000-0000
  89. deterministic cache parameters (4):
  90. --- cache 0 ---
  91. cache type = data cache (1)
  92. cache level = 0x1 (1)
  93. self-initializing cache level = true
  94. fully associative cache = false
  95. maximum IDs for CPUs sharing cache = 0x0 (0)
  96. maximum IDs for cores in pkg = 0x0 (0)
  97. system coherency line size = 0x40 (64)
  98. physical line partitions = 0x1 (1)
  99. ways of associativity = 0x8 (8)
  100. number of sets = 0x40 (64)
  101. WBINVD/INVD acts on lower caches = true
  102. inclusive to lower caches = false
  103. complex cache indexing = false
  104. number of sets (s) = 64
  105. (size synth) = 32768 (32 KB)
  106. --- cache 1 ---
  107. cache type = instruction cache (2)
  108. cache level = 0x1 (1)
  109. self-initializing cache level = true
  110. fully associative cache = false
  111. maximum IDs for CPUs sharing cache = 0x0 (0)
  112. maximum IDs for cores in pkg = 0x0 (0)
  113. system coherency line size = 0x40 (64)
  114. physical line partitions = 0x1 (1)
  115. ways of associativity = 0x8 (8)
  116. number of sets = 0x40 (64)
  117. WBINVD/INVD acts on lower caches = true
  118. inclusive to lower caches = false
  119. complex cache indexing = false
  120. number of sets (s) = 64
  121. (size synth) = 32768 (32 KB)
  122. --- cache 2 ---
  123. cache type = unified cache (3)
  124. cache level = 0x2 (2)
  125. self-initializing cache level = true
  126. fully associative cache = false
  127. maximum IDs for CPUs sharing cache = 0x0 (0)
  128. maximum IDs for cores in pkg = 0x0 (0)
  129. system coherency line size = 0x40 (64)
  130. physical line partitions = 0x1 (1)
  131. ways of associativity = 0x10 (16)
  132. number of sets = 0x1000 (4096)
  133. WBINVD/INVD acts on lower caches = true
  134. inclusive to lower caches = false
  135. complex cache indexing = false
  136. number of sets (s) = 4096
  137. (size synth) = 4194304 (4 MB)
  138. --- cache 3 ---
  139. cache type = unified cache (3)
  140. cache level = 0x3 (3)
  141. self-initializing cache level = true
  142. fully associative cache = false
  143. maximum IDs for CPUs sharing cache = 0x0 (0)
  144. maximum IDs for cores in pkg = 0x0 (0)
  145. system coherency line size = 0x40 (64)
  146. physical line partitions = 0x1 (1)
  147. ways of associativity = 0x10 (16)
  148. number of sets = 0x4000 (16384)
  149. WBINVD/INVD acts on lower caches = false
  150. inclusive to lower caches = true
  151. complex cache indexing = true
  152. number of sets (s) = 16384
  153. (size synth) = 16777216 (16 MB)
  154. MONITOR/MWAIT (5):
  155. smallest monitor-line size (bytes) = 0x0 (0)
  156. largest monitor-line size (bytes) = 0x0 (0)
  157. enum of Monitor-MWAIT exts supported = true
  158. supports intrs as break-event for MWAIT = true
  159. number of C0 sub C-states using MWAIT = 0x0 (0)
  160. number of C1 sub C-states using MWAIT = 0x0 (0)
  161. number of C2 sub C-states using MWAIT = 0x0 (0)
  162. number of C3 sub C-states using MWAIT = 0x0 (0)
  163. number of C4 sub C-states using MWAIT = 0x0 (0)
  164. number of C5 sub C-states using MWAIT = 0x0 (0)
  165. number of C6 sub C-states using MWAIT = 0x0 (0)
  166. number of C7 sub C-states using MWAIT = 0x0 (0)
  167. Thermal and Power Management Features (6):
  168. digital thermometer = false
  169. Intel Turbo Boost Technology = false
  170. ARAT always running APIC timer = true
  171. PLN power limit notification = false
  172. ECMD extended clock modulation duty = false
  173. PTM package thermal management = false
  174. HWP base registers = false
  175. HWP notification = false
  176. HWP activity window = false
  177. HWP energy performance preference = false
  178. HWP package level request = false
  179. HDC base registers = false
  180. Intel Turbo Boost Max Technology 3.0 = false
  181. HWP capabilities = false
  182. HWP PECI override = false
  183. flexible HWP = false
  184. IA32_HWP_REQUEST MSR fast access mode = false
  185. HW_FEEDBACK MSRs supported = false
  186. ignoring idle logical processor HWP req = false
  187. enhanced hardware feedback interface = false
  188. digital thermometer thresholds = 0x0 (0)
  189. hardware coordination feedback = false
  190. ACNT2 available = false
  191. performance-energy bias capability = false
  192. number of enh hardware feedback classes = 0x0 (0)
  193. performance capability reporting = false
  194. energy efficiency capability reporting = false
  195. size of feedback struct (4KB pages) = 0x1 (1)
  196. index of CPU's row in feedback struct = 0x0 (0)
  197. extended feature flags (7):
  198. FSGSBASE instructions = true
  199. IA32_TSC_ADJUST MSR supported = true
  200. SGX: Software Guard Extensions supported = false
  201. BMI1 instructions = true
  202. HLE hardware lock elision = false
  203. AVX2: advanced vector extensions 2 = true
  204. FDP_EXCPTN_ONLY = false
  205. SMEP supervisor mode exec protection = true
  206. BMI2 instructions = true
  207. enhanced REP MOVSB/STOSB = true
  208. INVPCID instruction = true
  209. RTM: restricted transactional memory = false
  210. RDT-CMT/PQoS cache monitoring = false
  211. deprecated FPU CS/DS = false
  212. MPX: intel memory protection extensions = true
  213. RDT-CAT/PQE cache allocation = false
  214. AVX512F: AVX-512 foundation instructions = true
  215. AVX512DQ: double & quadword instructions = true
  216. RDSEED instruction = true
  217. ADX instructions = true
  218. SMAP: supervisor mode access prevention = true
  219. AVX512IFMA: fused multiply add = false
  220. PCOMMIT instruction = false
  221. CLFLUSHOPT instruction = true
  222. CLWB instruction = true
  223. Intel processor trace = false
  224. AVX512PF: prefetch instructions = false
  225. AVX512ER: exponent & reciprocal instrs = false
  226. AVX512CD: conflict detection instrs = true
  227. SHA instructions = false
  228. AVX512BW: byte & word instructions = true
  229. AVX512VL: vector length = true
  230. PREFETCHWT1 = false
  231. AVX512VBMI: vector byte manipulation = false
  232. UMIP: user-mode instruction prevention = true
  233. PKU protection keys for user-mode = true
  234. OSPKE CR4.PKE and RDPKRU/WRPKRU = true
  235. WAITPKG instructions = false
  236. AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
  237. CET_SS: CET shadow stack = false
  238. GFNI: Galois Field New Instructions = false
  239. VAES instructions = false
  240. VPCLMULQDQ instruction = false
  241. AVX512_VNNI: neural network instructions = true
  242. AVX512_BITALG: bit count/shiffle = false
  243. TME: Total Memory Encryption = false
  244. AVX512: VPOPCNTDQ instruction = false
  245. 5-level paging = false
  246. BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
  247. RDPID: read processor D supported = false
  248. KL: key locker = false
  249. CLDEMOTE supports cache line demote = false
  250. MOVDIRI instruction = false
  251. MOVDIR64B instruction = false
  252. ENQCMD instruction = false
  253. SGX_LC: SGX launch config supported = false
  254. PKS: supervisor protection keys = false
  255. AVX512_4VNNIW: neural network instrs = false
  256. AVX512_4FMAPS: multiply acc single prec = false
  257. fast short REP MOV = false
  258. UINTR: user interrupts = false
  259. AVX512_VP2INTERSECT: intersect mask regs = false
  260. SRBDS mitigation MSR available = false
  261. VERW MD_CLEAR microcode support = true
  262. SERIALIZE instruction = false
  263. hybrid part = false
  264. TSXLDTRK: TSX suspend load addr tracking = false
  265. PCONFIG instruction = false
  266. LBR: architectural last branch records = false
  267. CET_IBT: CET indirect branch tracking = false
  268. AMX-BF16: tile bfloat16 support = false
  269. AVX512_FP16: fp16 support = false
  270. AMX-TILE: tile architecture support = false
  271. AMX-INT8: tile 8-bit integer support = false
  272. IBRS/IBPB: indirect branch restrictions = true
  273. STIBP: 1 thr indirect branch predictor = true
  274. L1D_FLUSH: IA32_FLUSH_CMD MSR = false
  275. IA32_ARCH_CAPABILITIES MSR = true
  276. IA32_CORE_CAPABILITIES MSR = false
  277. SSBD: speculative store bypass disable = true
  278. Direct Cache Access Parameters (9):
  279. PLATFORM_DCA_CAP MSR bits = 0
  280. Architecture Performance Monitoring Features (0xa):
  281. version ID = 0x2 (2)
  282. number of counters per logical processor = 0x4 (4)
  283. bit width of counter = 0x30 (48)
  284. length of EBX bit vector = 0x7 (7)
  285. core cycle event not available = false
  286. instruction retired event not available = false
  287. reference cycles event not available = false
  288. last-level cache ref event not available = false
  289. last-level cache miss event not avail = false
  290. branch inst retired event not available = false
  291. branch mispred retired event not avail = false
  292. fixed counter 0 supported = false
  293. fixed counter 1 supported = false
  294. fixed counter 2 supported = false
  295. fixed counter 3 supported = false
  296. fixed counter 4 supported = false
  297. fixed counter 5 supported = false
  298. fixed counter 6 supported = false
  299. fixed counter 7 supported = false
  300. fixed counter 8 supported = false
  301. fixed counter 9 supported = false
  302. fixed counter 10 supported = false
  303. fixed counter 11 supported = false
  304. fixed counter 12 supported = false
  305. fixed counter 13 supported = false
  306. fixed counter 14 supported = false
  307. fixed counter 15 supported = false
  308. fixed counter 16 supported = false
  309. fixed counter 17 supported = false
  310. fixed counter 18 supported = false
  311. fixed counter 19 supported = false
  312. fixed counter 20 supported = false
  313. fixed counter 21 supported = false
  314. fixed counter 22 supported = false
  315. fixed counter 23 supported = false
  316. fixed counter 24 supported = false
  317. fixed counter 25 supported = false
  318. fixed counter 26 supported = false
  319. fixed counter 27 supported = false
  320. fixed counter 28 supported = false
  321. fixed counter 29 supported = false
  322. fixed counter 30 supported = false
  323. fixed counter 31 supported = false
  324. number of fixed counters = 0x3 (3)
  325. bit width of fixed counters = 0x30 (48)
  326. anythread deprecation = false
  327. x2APIC features / processor topology (0xb):
  328. extended APIC ID = 0
  329. --- level 0 ---
  330. level number = 0x0 (0)
  331. level type = thread (1)
  332. bit width of level = 0x0 (0)
  333. number of logical processors at level = 0x1 (1)
  334. --- level 1 ---
  335. level number = 0x1 (1)
  336. level type = core (2)
  337. bit width of level = 0x0 (0)
  338. number of logical processors at level = 0x1 (1)
  339. XSAVE features (0xd/0):
  340. XCR0 lower 32 bits valid bit field mask = 0x000002ff
  341. XCR0 upper 32 bits valid bit field mask = 0x00000000
  342. XCR0 supported: x87 state = true
  343. XCR0 supported: SSE state = true
  344. XCR0 supported: AVX state = true
  345. XCR0 supported: MPX BNDREGS = true
  346. XCR0 supported: MPX BNDCSR = true
  347. XCR0 supported: AVX-512 opmask = true
  348. XCR0 supported: AVX-512 ZMM_Hi256 = true
  349. XCR0 supported: AVX-512 Hi16_ZMM = true
  350. IA32_XSS supported: PT state = false
  351. XCR0 supported: PKRU state = true
  352. XCR0 supported: CET_U state = false
  353. XCR0 supported: CET_S state = false
  354. IA32_XSS supported: HDC state = false
  355. IA32_XSS supported: UINTR state = false
  356. LBR supported = false
  357. IA32_XSS supported: HWP state = false
  358. XTILECFG supported = false
  359. XTILEDATA supported = false
  360. bytes required by fields in XCR0 = 0x00000a88 (2696)
  361. bytes required by XSAVE/XRSTOR area = 0x00000a88 (2696)
  362. XSAVE features (0xd/1):
  363. XSAVEOPT instruction = true
  364. XSAVEC instruction = true
  365. XGETBV instruction = true
  366. XSAVES/XRSTORS instructions = true
  367. XFD: extended feature disable supported = false
  368. SAVE area size in bytes = 0x00000a08 (2568)
  369. IA32_XSS lower 32 bits valid bit field mask = 0x00000000
  370. IA32_XSS upper 32 bits valid bit field mask = 0x00000000
  371. AVX/YMM features (0xd/2):
  372. AVX/YMM save state byte size = 0x00000100 (256)
  373. AVX/YMM save state byte offset = 0x00000240 (576)
  374. supported in IA32_XSS or XCR0 = XCR0 (user state)
  375. 64-byte alignment in compacted XSAVE = false
  376. XFD faulting supported = false
  377. MPX BNDREGS features (0xd/3):
  378. MPX BNDREGS save state byte size = 0x00000040 (64)
  379. MPX BNDREGS save state byte offset = 0x000003c0 (960)
  380. supported in IA32_XSS or XCR0 = XCR0 (user state)
  381. 64-byte alignment in compacted XSAVE = false
  382. XFD faulting supported = false
  383. MPX BNDCSR features (0xd/4):
  384. MPX BNDCSR save state byte size = 0x00000040 (64)
  385. MPX BNDCSR save state byte offset = 0x00000400 (1024)
  386. supported in IA32_XSS or XCR0 = XCR0 (user state)
  387. 64-byte alignment in compacted XSAVE = false
  388. XFD faulting supported = false
  389. AVX-512 opmask features (0xd/5):
  390. AVX-512 opmask save state byte size = 0x00000040 (64)
  391. AVX-512 opmask save state byte offset = 0x00000440 (1088)
  392. supported in IA32_XSS or XCR0 = XCR0 (user state)
  393. 64-byte alignment in compacted XSAVE = false
  394. XFD faulting supported = false
  395. AVX-512 ZMM_Hi256 features (0xd/6):
  396. AVX-512 ZMM_Hi256 save state byte size = 0x00000200 (512)
  397. AVX-512 ZMM_Hi256 save state byte offset = 0x00000480 (1152)
  398. supported in IA32_XSS or XCR0 = XCR0 (user state)
  399. 64-byte alignment in compacted XSAVE = false
  400. XFD faulting supported = false
  401. AVX-512 Hi16_ZMM features (0xd/7):
  402. AVX-512 Hi16_ZMM save state byte size = 0x00000400 (1024)
  403. AVX-512 Hi16_ZMM save state byte offset = 0x00000680 (1664)
  404. supported in IA32_XSS or XCR0 = XCR0 (user state)
  405. 64-byte alignment in compacted XSAVE = false
  406. XFD faulting supported = false
  407. PKRU features (0xd/9):
  408. PKRU save state byte size = 0x00000008 (8)
  409. PKRU save state byte offset = 0x00000a80 (2688)
  410. supported in IA32_XSS or XCR0 = XCR0 (user state)
  411. 64-byte alignment in compacted XSAVE = false
  412. XFD faulting supported = false
  413. Quality of Service Monitoring Resource Type (0xf/0):
  414. Maximum range of RMID = 0
  415. supports L3 cache QoS monitoring = false
  416. Resource Director Technology Allocation (0x10/0):
  417. L3 cache allocation technology supported = false
  418. L2 cache allocation technology supported = false
  419. memory bandwidth allocation supported = false
  420. 0x00000011 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
  421. Software Guard Extensions (SGX) capability (0x12/0):
  422. SGX1 supported = false
  423. SGX2 supported = false
  424. SGX ENCLV E*VIRTCHILD, ESETCONTEXT = false
  425. SGX ENCLS ETRACKC, ERDINFO, ELDBC, ELDUC = false
  426. MISCSELECT.EXINFO supported: #PF & #GP = false
  427. MISCSELECT.CPINFO supported: #CP = false
  428. MaxEnclaveSize_Not64 (log2) = 0x0 (0)
  429. MaxEnclaveSize_64 (log2) = 0x0 (0)
  430. 0x00000013 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
  431. Intel Processor Trace (0x14):
  432. IA32_RTIT_CR3_MATCH is accessible = false
  433. configurable PSB & cycle-accurate = false
  434. IP & TraceStop filtering; PT preserve = false
  435. MTC timing packet; suppress COFI-based = false
  436. PTWRITE support = false
  437. power event trace support = false
  438. ToPA output scheme support = false
  439. ToPA can hold many output entries = false
  440. single-range output scheme support = false
  441. output to trace transport = false
  442. IP payloads have LIP values & CS = false
  443. Time Stamp Counter/Core Crystal Clock Information (0x15):
  444. TSC/clock ratio = 0/0
  445. nominal core crystal clock = 0 Hz
  446. Processor Frequency Information (0x16):
  447. Core Base Frequency (MHz) = 0x0 (0)
  448. Core Maximum Frequency (MHz) = 0x0 (0)
  449. Bus (Reference) Frequency (MHz) = 0x0 (0)
  450. hypervisor_id = "KVMKVMKVM "
  451. hypervisor features (0x40000001/eax):
  452. kvmclock available at MSR 0x11 = true
  453. delays unnecessary for PIO ops = true
  454. mmu_op = false
  455. kvmclock available at MSR 0x4b564d00 = true
  456. async pf enable available by MSR = true
  457. steal clock supported = true
  458. guest EOI optimization enabled = true
  459. guest spinlock optimization enabled = true
  460. guest TLB flush optimization enabled = true
  461. async PF VM exit enable available by MSR = false
  462. guest send IPI optimization enabled = true
  463. host HLT poll disable at MSR 0x4b564d05 = true
  464. guest sched yield optimization enabled = true
  465. guest uses intrs for page ready APF evs = false
  466. stable: no guest per-cpu warps expected = true
  467. hypervisor features (0x40000001/edx):
  468. realtime hint: no unbound preemption = true
  469. extended feature flags (0x80000001/edx):
  470. SYSCALL and SYSRET instructions = true
  471. execution disable = true
  472. 1-GB large page support = true
  473. RDTSCP = true
  474. 64-bit extensions technology available = true
  475. Intel feature flags (0x80000001/ecx):
  476. LAHF/SAHF supported in 64-bit mode = true
  477. LZCNT advanced bit manipulation = true
  478. 3DNow! PREFETCH/PREFETCHW instructions = true
  479. brand = "Intel(R) Xeon(R) Platinum 8275CL CPU @ 3.00GHz"
  480. L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
  481. instruction # entries = 0xff (255)
  482. instruction associativity = 0x1 (1)
  483. data # entries = 0xff (255)
  484. data associativity = 0x1 (1)
  485. L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
  486. instruction # entries = 0xff (255)
  487. instruction associativity = 0x1 (1)
  488. data # entries = 0xff (255)
  489. data associativity = 0x1 (1)
  490. L1 data cache information (0x80000005/ecx):
  491. line size (bytes) = 0x40 (64)
  492. lines per tag = 0x1 (1)
  493. associativity = 0x2 (2)
  494. size (KB) = 0x40 (64)
  495. L1 instruction cache information (0x80000005/edx):
  496. line size (bytes) = 0x40 (64)
  497. lines per tag = 0x1 (1)
  498. associativity = 0x2 (2)
  499. size (KB) = 0x40 (64)
  500. L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
  501. instruction # entries = 0x0 (0)
  502. instruction associativity = L2 off (0)
  503. data # entries = 0x0 (0)
  504. data associativity = L2 off (0)
  505. L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
  506. instruction # entries = 0x200 (512)
  507. instruction associativity = 4-way (4)
  508. data # entries = 0x200 (512)
  509. data associativity = 4-way (4)
  510. L2 unified cache information (0x80000006/ecx):
  511. line size (bytes) = 0x40 (64)
  512. lines per tag = 0x1 (1)
  513. associativity = 16-way (8)
  514. size (KB) = 0x200 (512)
  515. L3 cache information (0x80000006/edx):
  516. line size (bytes) = 0x40 (64)
  517. lines per tag = 0x1 (1)
  518. associativity = 16-way (8)
  519. size (in 512KB units) = 0x20 (32)
  520. RAS Capability (0x80000007/ebx):
  521. MCA overflow recovery support = false
  522. SUCCOR support = false
  523. HWA: hardware assert support = false
  524. scalable MCA support = false
  525. Advanced Power Management Features (0x80000007/ecx):
  526. CmpUnitPwrSampleTimeRatio = 0x0 (0)
  527. Advanced Power Management Features (0x80000007/edx):
  528. TS: temperature sensing diode = false
  529. FID: frequency ID control = false
  530. VID: voltage ID control = false
  531. TTP: thermal trip = false
  532. TM: thermal monitor = false
  533. STC: software thermal control = false
  534. 100 MHz multiplier control = false
  535. hardware P-State control = false
  536. TscInvariant = false
  537. CPB: core performance boost = false
  538. read-only effective frequency interface = false
  539. processor feedback interface = false
  540. APM power reporting = false
  541. connected standby = false
  542. RAPL: running average power limit = false
  543. Physical Address and Linear Address Size (0x80000008/eax):
  544. maximum physical address bits = 0x2e (46)
  545. maximum linear (virtual) address bits = 0x30 (48)
  546. maximum guest physical address bits = 0x0 (0)
  547. Extended Feature Extensions ID (0x80000008/ebx):
  548. CLZERO instruction = false
  549. instructions retired count support = false
  550. always save/restore error pointers = false
  551. RDPRU instruction = false
  552. memory bandwidth enforcement = false
  553. WBNOINVD instruction = false
  554. IBPB: indirect branch prediction barrier = true
  555. IBRS: indirect branch restr speculation = true
  556. STIBP: 1 thr indirect branch predictor = true
  557. STIBP always on preferred mode = false
  558. ppin processor id number supported = false
  559. SSBD: speculative store bypass disable = true
  560. virtualized SSBD = false
  561. SSBD fixed in hardware = false
  562. Size Identifiers (0x80000008/ecx):
  563. number of CPU cores = 0x1 (1)
  564. ApicIdCoreIdSize = 0x0 (0)
  565. performance time-stamp counter size = 0x0 (0)
  566. Feature Extended Size (0x80000008/edx):
  567. RDPRU instruction max input support = 0x0 (0)
  568. (multi-processing synth) = none
  569. (multi-processing method) = Intel leaf 0xb
  570. (APIC widths synth): CORE_width=0 SMT_width=0
  571. (APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=0
  572. (uarch synth) = Intel Cascade Lake {Skylake}, 14nm
  573. (synth) = Intel Scalable (2nd Gen) Bronze/Silver/Gold/Platinum (Cascade Lake B1/L1/R1) {Skylake}, 14nm
  574. CPU 1:
  575. vendor_id = "GenuineIntel"
  576. version information (1/eax):
  577. processor type = primary processor (0)
  578. family = 0x6 (6)
  579. model = 0x5 (5)
  580. stepping id = 0x7 (7)
  581. extended family = 0x0 (0)
  582. extended model = 0x5 (5)
  583. (family synth) = 0x6 (6)
  584. (model synth) = 0x55 (85)
  585. (simple synth) = Intel Core (unknown type) (Skylake / Skylake-X / Cascade Lake / Cascade Lake-X) {Skylake}, 14nm
  586. miscellaneous (1/ebx):
  587. process local APIC physical ID = 0x1 (1)
  588. maximum IDs for CPUs in pkg = 0x0 (0)
  589. CLFLUSH line size = 0x8 (8)
  590. brand index = 0x0 (0)
  591. brand id = 0x00 (0): unknown
  592. feature information (1/edx):
  593. x87 FPU on chip = true
  594. VME: virtual-8086 mode enhancement = true
  595. DE: debugging extensions = true
  596. PSE: page size extensions = true
  597. TSC: time stamp counter = true
  598. RDMSR and WRMSR support = true
  599. PAE: physical address extensions = true
  600. MCE: machine check exception = true
  601. CMPXCHG8B inst. = true
  602. APIC on chip = true
  603. SYSENTER and SYSEXIT = true
  604. MTRR: memory type range registers = true
  605. PTE global bit = true
  606. MCA: machine check architecture = true
  607. CMOV: conditional move/compare instr = true
  608. PAT: page attribute table = true
  609. PSE-36: page size extension = true
  610. PSN: processor serial number = false
  611. CLFLUSH instruction = true
  612. DS: debug store = false
  613. ACPI: thermal monitor and clock ctrl = false
  614. MMX Technology = true
  615. FXSAVE/FXRSTOR = true
  616. SSE extensions = true
  617. SSE2 extensions = true
  618. SS: self snoop = true
  619. hyper-threading / multi-core supported = false
  620. TM: therm. monitor = false
  621. IA64 = false
  622. PBE: pending break event = false
  623. feature information (1/ecx):
  624. PNI/SSE3: Prescott New Instructions = true
  625. PCLMULDQ instruction = true
  626. DTES64: 64-bit debug store = false
  627. MONITOR/MWAIT = false
  628. CPL-qualified debug store = false
  629. VMX: virtual machine extensions = true
  630. SMX: safer mode extensions = false
  631. Enhanced Intel SpeedStep Technology = false
  632. TM2: thermal monitor 2 = false
  633. SSSE3 extensions = true
  634. context ID: adaptive or shared L1 data = false
  635. SDBG: IA32_DEBUG_INTERFACE = false
  636. FMA instruction = true
  637. CMPXCHG16B instruction = true
  638. xTPR disable = false
  639. PDCM: perfmon and debug = false
  640. PCID: process context identifiers = true
  641. DCA: direct cache access = false
  642. SSE4.1 extensions = true
  643. SSE4.2 extensions = true
  644. x2APIC: extended xAPIC support = true
  645. MOVBE instruction = true
  646. POPCNT instruction = true
  647. time stamp counter deadline = true
  648. AES instruction = true
  649. XSAVE/XSTOR states = true
  650. OS-enabled XSAVE/XSTOR = true
  651. AVX: advanced vector extensions = true
  652. F16C half-precision convert instruction = true
  653. RDRAND instruction = true
  654. hypervisor guest status = true
  655. cache and TLB information (2):
  656. 0x4d: L3 cache: 16M, 16-way, 64 byte lines
  657. 0x7d: L2 cache: 2M, 8-way, 64 byte lines
  658. 0x30: L1 cache: 32K, 8-way, 64 byte lines
  659. 0x2c: L1 data cache: 32K, 8-way, 64 byte lines
  660. processor serial number = 0005-0657-0000-0000-0000-0000
  661. deterministic cache parameters (4):
  662. --- cache 0 ---
  663. cache type = data cache (1)
  664. cache level = 0x1 (1)
  665. self-initializing cache level = true
  666. fully associative cache = false
  667. maximum IDs for CPUs sharing cache = 0x0 (0)
  668. maximum IDs for cores in pkg = 0x0 (0)
  669. system coherency line size = 0x40 (64)
  670. physical line partitions = 0x1 (1)
  671. ways of associativity = 0x8 (8)
  672. number of sets = 0x40 (64)
  673. WBINVD/INVD acts on lower caches = true
  674. inclusive to lower caches = false
  675. complex cache indexing = false
  676. number of sets (s) = 64
  677. (size synth) = 32768 (32 KB)
  678. --- cache 1 ---
  679. cache type = instruction cache (2)
  680. cache level = 0x1 (1)
  681. self-initializing cache level = true
  682. fully associative cache = false
  683. maximum IDs for CPUs sharing cache = 0x0 (0)
  684. maximum IDs for cores in pkg = 0x0 (0)
  685. system coherency line size = 0x40 (64)
  686. physical line partitions = 0x1 (1)
  687. ways of associativity = 0x8 (8)
  688. number of sets = 0x40 (64)
  689. WBINVD/INVD acts on lower caches = true
  690. inclusive to lower caches = false
  691. complex cache indexing = false
  692. number of sets (s) = 64
  693. (size synth) = 32768 (32 KB)
  694. --- cache 2 ---
  695. cache type = unified cache (3)
  696. cache level = 0x2 (2)
  697. self-initializing cache level = true
  698. fully associative cache = false
  699. maximum IDs for CPUs sharing cache = 0x0 (0)
  700. maximum IDs for cores in pkg = 0x0 (0)
  701. system coherency line size = 0x40 (64)
  702. physical line partitions = 0x1 (1)
  703. ways of associativity = 0x10 (16)
  704. number of sets = 0x1000 (4096)
  705. WBINVD/INVD acts on lower caches = true
  706. inclusive to lower caches = false
  707. complex cache indexing = false
  708. number of sets (s) = 4096
  709. (size synth) = 4194304 (4 MB)
  710. --- cache 3 ---
  711. cache type = unified cache (3)
  712. cache level = 0x3 (3)
  713. self-initializing cache level = true
  714. fully associative cache = false
  715. maximum IDs for CPUs sharing cache = 0x0 (0)
  716. maximum IDs for cores in pkg = 0x0 (0)
  717. system coherency line size = 0x40 (64)
  718. physical line partitions = 0x1 (1)
  719. ways of associativity = 0x10 (16)
  720. number of sets = 0x4000 (16384)
  721. WBINVD/INVD acts on lower caches = false
  722. inclusive to lower caches = true
  723. complex cache indexing = true
  724. number of sets (s) = 16384
  725. (size synth) = 16777216 (16 MB)
  726. MONITOR/MWAIT (5):
  727. smallest monitor-line size (bytes) = 0x0 (0)
  728. largest monitor-line size (bytes) = 0x0 (0)
  729. enum of Monitor-MWAIT exts supported = true
  730. supports intrs as break-event for MWAIT = true
  731. number of C0 sub C-states using MWAIT = 0x0 (0)
  732. number of C1 sub C-states using MWAIT = 0x0 (0)
  733. number of C2 sub C-states using MWAIT = 0x0 (0)
  734. number of C3 sub C-states using MWAIT = 0x0 (0)
  735. number of C4 sub C-states using MWAIT = 0x0 (0)
  736. number of C5 sub C-states using MWAIT = 0x0 (0)
  737. number of C6 sub C-states using MWAIT = 0x0 (0)
  738. number of C7 sub C-states using MWAIT = 0x0 (0)
  739. Thermal and Power Management Features (6):
  740. digital thermometer = false
  741. Intel Turbo Boost Technology = false
  742. ARAT always running APIC timer = true
  743. PLN power limit notification = false
  744. ECMD extended clock modulation duty = false
  745. PTM package thermal management = false
  746. HWP base registers = false
  747. HWP notification = false
  748. HWP activity window = false
  749. HWP energy performance preference = false
  750. HWP package level request = false
  751. HDC base registers = false
  752. Intel Turbo Boost Max Technology 3.0 = false
  753. HWP capabilities = false
  754. HWP PECI override = false
  755. flexible HWP = false
  756. IA32_HWP_REQUEST MSR fast access mode = false
  757. HW_FEEDBACK MSRs supported = false
  758. ignoring idle logical processor HWP req = false
  759. enhanced hardware feedback interface = false
  760. digital thermometer thresholds = 0x0 (0)
  761. hardware coordination feedback = false
  762. ACNT2 available = false
  763. performance-energy bias capability = false
  764. number of enh hardware feedback classes = 0x0 (0)
  765. performance capability reporting = false
  766. energy efficiency capability reporting = false
  767. size of feedback struct (4KB pages) = 0x1 (1)
  768. index of CPU's row in feedback struct = 0x0 (0)
  769. extended feature flags (7):
  770. FSGSBASE instructions = true
  771. IA32_TSC_ADJUST MSR supported = true
  772. SGX: Software Guard Extensions supported = false
  773. BMI1 instructions = true
  774. HLE hardware lock elision = false
  775. AVX2: advanced vector extensions 2 = true
  776. FDP_EXCPTN_ONLY = false
  777. SMEP supervisor mode exec protection = true
  778. BMI2 instructions = true
  779. enhanced REP MOVSB/STOSB = true
  780. INVPCID instruction = true
  781. RTM: restricted transactional memory = false
  782. RDT-CMT/PQoS cache monitoring = false
  783. deprecated FPU CS/DS = false
  784. MPX: intel memory protection extensions = true
  785. RDT-CAT/PQE cache allocation = false
  786. AVX512F: AVX-512 foundation instructions = true
  787. AVX512DQ: double & quadword instructions = true
  788. RDSEED instruction = true
  789. ADX instructions = true
  790. SMAP: supervisor mode access prevention = true
  791. AVX512IFMA: fused multiply add = false
  792. PCOMMIT instruction = false
  793. CLFLUSHOPT instruction = true
  794. CLWB instruction = true
  795. Intel processor trace = false
  796. AVX512PF: prefetch instructions = false
  797. AVX512ER: exponent & reciprocal instrs = false
  798. AVX512CD: conflict detection instrs = true
  799. SHA instructions = false
  800. AVX512BW: byte & word instructions = true
  801. AVX512VL: vector length = true
  802. PREFETCHWT1 = false
  803. AVX512VBMI: vector byte manipulation = false
  804. UMIP: user-mode instruction prevention = true
  805. PKU protection keys for user-mode = true
  806. OSPKE CR4.PKE and RDPKRU/WRPKRU = true
  807. WAITPKG instructions = false
  808. AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
  809. CET_SS: CET shadow stack = false
  810. GFNI: Galois Field New Instructions = false
  811. VAES instructions = false
  812. VPCLMULQDQ instruction = false
  813. AVX512_VNNI: neural network instructions = true
  814. AVX512_BITALG: bit count/shiffle = false
  815. TME: Total Memory Encryption = false
  816. AVX512: VPOPCNTDQ instruction = false
  817. 5-level paging = false
  818. BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
  819. RDPID: read processor D supported = false
  820. KL: key locker = false
  821. CLDEMOTE supports cache line demote = false
  822. MOVDIRI instruction = false
  823. MOVDIR64B instruction = false
  824. ENQCMD instruction = false
  825. SGX_LC: SGX launch config supported = false
  826. PKS: supervisor protection keys = false
  827. AVX512_4VNNIW: neural network instrs = false
  828. AVX512_4FMAPS: multiply acc single prec = false
  829. fast short REP MOV = false
  830. UINTR: user interrupts = false
  831. AVX512_VP2INTERSECT: intersect mask regs = false
  832. SRBDS mitigation MSR available = false
  833. VERW MD_CLEAR microcode support = true
  834. SERIALIZE instruction = false
  835. hybrid part = false
  836. TSXLDTRK: TSX suspend load addr tracking = false
  837. PCONFIG instruction = false
  838. LBR: architectural last branch records = false
  839. CET_IBT: CET indirect branch tracking = false
  840. AMX-BF16: tile bfloat16 support = false
  841. AVX512_FP16: fp16 support = false
  842. AMX-TILE: tile architecture support = false
  843. AMX-INT8: tile 8-bit integer support = false
  844. IBRS/IBPB: indirect branch restrictions = true
  845. STIBP: 1 thr indirect branch predictor = true
  846. L1D_FLUSH: IA32_FLUSH_CMD MSR = false
  847. IA32_ARCH_CAPABILITIES MSR = true
  848. IA32_CORE_CAPABILITIES MSR = false
  849. SSBD: speculative store bypass disable = true
  850. Direct Cache Access Parameters (9):
  851. PLATFORM_DCA_CAP MSR bits = 0
  852. Architecture Performance Monitoring Features (0xa):
  853. version ID = 0x2 (2)
  854. number of counters per logical processor = 0x4 (4)
  855. bit width of counter = 0x30 (48)
  856. length of EBX bit vector = 0x7 (7)
  857. core cycle event not available = false
  858. instruction retired event not available = false
  859. reference cycles event not available = false
  860. last-level cache ref event not available = false
  861. last-level cache miss event not avail = false
  862. branch inst retired event not available = false
  863. branch mispred retired event not avail = false
  864. fixed counter 0 supported = false
  865. fixed counter 1 supported = false
  866. fixed counter 2 supported = false
  867. fixed counter 3 supported = false
  868. fixed counter 4 supported = false
  869. fixed counter 5 supported = false
  870. fixed counter 6 supported = false
  871. fixed counter 7 supported = false
  872. fixed counter 8 supported = false
  873. fixed counter 9 supported = false
  874. fixed counter 10 supported = false
  875. fixed counter 11 supported = false
  876. fixed counter 12 supported = false
  877. fixed counter 13 supported = false
  878. fixed counter 14 supported = false
  879. fixed counter 15 supported = false
  880. fixed counter 16 supported = false
  881. fixed counter 17 supported = false
  882. fixed counter 18 supported = false
  883. fixed counter 19 supported = false
  884. fixed counter 20 supported = false
  885. fixed counter 21 supported = false
  886. fixed counter 22 supported = false
  887. fixed counter 23 supported = false
  888. fixed counter 24 supported = false
  889. fixed counter 25 supported = false
  890. fixed counter 26 supported = false
  891. fixed counter 27 supported = false
  892. fixed counter 28 supported = false
  893. fixed counter 29 supported = false
  894. fixed counter 30 supported = false
  895. fixed counter 31 supported = false
  896. number of fixed counters = 0x3 (3)
  897. bit width of fixed counters = 0x30 (48)
  898. anythread deprecation = false
  899. x2APIC features / processor topology (0xb):
  900. extended APIC ID = 1
  901. --- level 0 ---
  902. level number = 0x0 (0)
  903. level type = thread (1)
  904. bit width of level = 0x0 (0)
  905. number of logical processors at level = 0x1 (1)
  906. --- level 1 ---
  907. level number = 0x1 (1)
  908. level type = core (2)
  909. bit width of level = 0x0 (0)
  910. number of logical processors at level = 0x1 (1)
  911. XSAVE features (0xd/0):
  912. XCR0 lower 32 bits valid bit field mask = 0x000002ff
  913. XCR0 upper 32 bits valid bit field mask = 0x00000000
  914. XCR0 supported: x87 state = true
  915. XCR0 supported: SSE state = true
  916. XCR0 supported: AVX state = true
  917. XCR0 supported: MPX BNDREGS = true
  918. XCR0 supported: MPX BNDCSR = true
  919. XCR0 supported: AVX-512 opmask = true
  920. XCR0 supported: AVX-512 ZMM_Hi256 = true
  921. XCR0 supported: AVX-512 Hi16_ZMM = true
  922. IA32_XSS supported: PT state = false
  923. XCR0 supported: PKRU state = true
  924. XCR0 supported: CET_U state = false
  925. XCR0 supported: CET_S state = false
  926. IA32_XSS supported: HDC state = false
  927. IA32_XSS supported: UINTR state = false
  928. LBR supported = false
  929. IA32_XSS supported: HWP state = false
  930. XTILECFG supported = false
  931. XTILEDATA supported = false
  932. bytes required by fields in XCR0 = 0x00000a88 (2696)
  933. bytes required by XSAVE/XRSTOR area = 0x00000a88 (2696)
  934. XSAVE features (0xd/1):
  935. XSAVEOPT instruction = true
  936. XSAVEC instruction = true
  937. XGETBV instruction = true
  938. XSAVES/XRSTORS instructions = true
  939. XFD: extended feature disable supported = false
  940. SAVE area size in bytes = 0x00000a08 (2568)
  941. IA32_XSS lower 32 bits valid bit field mask = 0x00000000
  942. IA32_XSS upper 32 bits valid bit field mask = 0x00000000
  943. AVX/YMM features (0xd/2):
  944. AVX/YMM save state byte size = 0x00000100 (256)
  945. AVX/YMM save state byte offset = 0x00000240 (576)
  946. supported in IA32_XSS or XCR0 = XCR0 (user state)
  947. 64-byte alignment in compacted XSAVE = false
  948. XFD faulting supported = false
  949. MPX BNDREGS features (0xd/3):
  950. MPX BNDREGS save state byte size = 0x00000040 (64)
  951. MPX BNDREGS save state byte offset = 0x000003c0 (960)
  952. supported in IA32_XSS or XCR0 = XCR0 (user state)
  953. 64-byte alignment in compacted XSAVE = false
  954. XFD faulting supported = false
  955. MPX BNDCSR features (0xd/4):
  956. MPX BNDCSR save state byte size = 0x00000040 (64)
  957. MPX BNDCSR save state byte offset = 0x00000400 (1024)
  958. supported in IA32_XSS or XCR0 = XCR0 (user state)
  959. 64-byte alignment in compacted XSAVE = false
  960. XFD faulting supported = false
  961. AVX-512 opmask features (0xd/5):
  962. AVX-512 opmask save state byte size = 0x00000040 (64)
  963. AVX-512 opmask save state byte offset = 0x00000440 (1088)
  964. supported in IA32_XSS or XCR0 = XCR0 (user state)
  965. 64-byte alignment in compacted XSAVE = false
  966. XFD faulting supported = false
  967. AVX-512 ZMM_Hi256 features (0xd/6):
  968. AVX-512 ZMM_Hi256 save state byte size = 0x00000200 (512)
  969. AVX-512 ZMM_Hi256 save state byte offset = 0x00000480 (1152)
  970. supported in IA32_XSS or XCR0 = XCR0 (user state)
  971. 64-byte alignment in compacted XSAVE = false
  972. XFD faulting supported = false
  973. AVX-512 Hi16_ZMM features (0xd/7):
  974. AVX-512 Hi16_ZMM save state byte size = 0x00000400 (1024)
  975. AVX-512 Hi16_ZMM save state byte offset = 0x00000680 (1664)
  976. supported in IA32_XSS or XCR0 = XCR0 (user state)
  977. 64-byte alignment in compacted XSAVE = false
  978. XFD faulting supported = false
  979. PKRU features (0xd/9):
  980. PKRU save state byte size = 0x00000008 (8)
  981. PKRU save state byte offset = 0x00000a80 (2688)
  982. supported in IA32_XSS or XCR0 = XCR0 (user state)
  983. 64-byte alignment in compacted XSAVE = false
  984. XFD faulting supported = false
  985. Quality of Service Monitoring Resource Type (0xf/0):
  986. Maximum range of RMID = 0
  987. supports L3 cache QoS monitoring = false
  988. Resource Director Technology Allocation (0x10/0):
  989. L3 cache allocation technology supported = false
  990. L2 cache allocation technology supported = false
  991. memory bandwidth allocation supported = false
  992. 0x00000011 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
  993. Software Guard Extensions (SGX) capability (0x12/0):
  994. SGX1 supported = false
  995. SGX2 supported = false
  996. SGX ENCLV E*VIRTCHILD, ESETCONTEXT = false
  997. SGX ENCLS ETRACKC, ERDINFO, ELDBC, ELDUC = false
  998. MISCSELECT.EXINFO supported: #PF & #GP = false
  999. MISCSELECT.CPINFO supported: #CP = false
  1000. MaxEnclaveSize_Not64 (log2) = 0x0 (0)
  1001. MaxEnclaveSize_64 (log2) = 0x0 (0)
  1002. 0x00000013 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
  1003. Intel Processor Trace (0x14):
  1004. IA32_RTIT_CR3_MATCH is accessible = false
  1005. configurable PSB & cycle-accurate = false
  1006. IP & TraceStop filtering; PT preserve = false
  1007. MTC timing packet; suppress COFI-based = false
  1008. PTWRITE support = false
  1009. power event trace support = false
  1010. ToPA output scheme support = false
  1011. ToPA can hold many output entries = false
  1012. single-range output scheme support = false
  1013. output to trace transport = false
  1014. IP payloads have LIP values & CS = false
  1015. Time Stamp Counter/Core Crystal Clock Information (0x15):
  1016. TSC/clock ratio = 0/0
  1017. nominal core crystal clock = 0 Hz
  1018. Processor Frequency Information (0x16):
  1019. Core Base Frequency (MHz) = 0x0 (0)
  1020. Core Maximum Frequency (MHz) = 0x0 (0)
  1021. Bus (Reference) Frequency (MHz) = 0x0 (0)
  1022. hypervisor_id = "KVMKVMKVM "
  1023. hypervisor features (0x40000001/eax):
  1024. kvmclock available at MSR 0x11 = true
  1025. delays unnecessary for PIO ops = true
  1026. mmu_op = false
  1027. kvmclock available at MSR 0x4b564d00 = true
  1028. async pf enable available by MSR = true
  1029. steal clock supported = true
  1030. guest EOI optimization enabled = true
  1031. guest spinlock optimization enabled = true
  1032. guest TLB flush optimization enabled = true
  1033. async PF VM exit enable available by MSR = false
  1034. guest send IPI optimization enabled = true
  1035. host HLT poll disable at MSR 0x4b564d05 = true
  1036. guest sched yield optimization enabled = true
  1037. guest uses intrs for page ready APF evs = false
  1038. stable: no guest per-cpu warps expected = true
  1039. hypervisor features (0x40000001/edx):
  1040. realtime hint: no unbound preemption = true
  1041. extended feature flags (0x80000001/edx):
  1042. SYSCALL and SYSRET instructions = true
  1043. execution disable = true
  1044. 1-GB large page support = true
  1045. RDTSCP = true
  1046. 64-bit extensions technology available = true
  1047. Intel feature flags (0x80000001/ecx):
  1048. LAHF/SAHF supported in 64-bit mode = true
  1049. LZCNT advanced bit manipulation = true
  1050. 3DNow! PREFETCH/PREFETCHW instructions = true
  1051. brand = "Intel(R) Xeon(R) Platinum 8275CL CPU @ 3.00GHz"
  1052. L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
  1053. instruction # entries = 0xff (255)
  1054. instruction associativity = 0x1 (1)
  1055. data # entries = 0xff (255)
  1056. data associativity = 0x1 (1)
  1057. L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
  1058. instruction # entries = 0xff (255)
  1059. instruction associativity = 0x1 (1)
  1060. data # entries = 0xff (255)
  1061. data associativity = 0x1 (1)
  1062. L1 data cache information (0x80000005/ecx):
  1063. line size (bytes) = 0x40 (64)
  1064. lines per tag = 0x1 (1)
  1065. associativity = 0x2 (2)
  1066. size (KB) = 0x40 (64)
  1067. L1 instruction cache information (0x80000005/edx):
  1068. line size (bytes) = 0x40 (64)
  1069. lines per tag = 0x1 (1)
  1070. associativity = 0x2 (2)
  1071. size (KB) = 0x40 (64)
  1072. L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
  1073. instruction # entries = 0x0 (0)
  1074. instruction associativity = L2 off (0)
  1075. data # entries = 0x0 (0)
  1076. data associativity = L2 off (0)
  1077. L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
  1078. instruction # entries = 0x200 (512)
  1079. instruction associativity = 4-way (4)
  1080. data # entries = 0x200 (512)
  1081. data associativity = 4-way (4)
  1082. L2 unified cache information (0x80000006/ecx):
  1083. line size (bytes) = 0x40 (64)
  1084. lines per tag = 0x1 (1)
  1085. associativity = 16-way (8)
  1086. size (KB) = 0x200 (512)
  1087. L3 cache information (0x80000006/edx):
  1088. line size (bytes) = 0x40 (64)
  1089. lines per tag = 0x1 (1)
  1090. associativity = 16-way (8)
  1091. size (in 512KB units) = 0x20 (32)
  1092. RAS Capability (0x80000007/ebx):
  1093. MCA overflow recovery support = false
  1094. SUCCOR support = false
  1095. HWA: hardware assert support = false
  1096. scalable MCA support = false
  1097. Advanced Power Management Features (0x80000007/ecx):
  1098. CmpUnitPwrSampleTimeRatio = 0x0 (0)
  1099. Advanced Power Management Features (0x80000007/edx):
  1100. TS: temperature sensing diode = false
  1101. FID: frequency ID control = false
  1102. VID: voltage ID control = false
  1103. TTP: thermal trip = false
  1104. TM: thermal monitor = false
  1105. STC: software thermal control = false
  1106. 100 MHz multiplier control = false
  1107. hardware P-State control = false
  1108. TscInvariant = false
  1109. CPB: core performance boost = false
  1110. read-only effective frequency interface = false
  1111. processor feedback interface = false
  1112. APM power reporting = false
  1113. connected standby = false
  1114. RAPL: running average power limit = false
  1115. Physical Address and Linear Address Size (0x80000008/eax):
  1116. maximum physical address bits = 0x2e (46)
  1117. maximum linear (virtual) address bits = 0x30 (48)
  1118. maximum guest physical address bits = 0x0 (0)
  1119. Extended Feature Extensions ID (0x80000008/ebx):
  1120. CLZERO instruction = false
  1121. instructions retired count support = false
  1122. always save/restore error pointers = false
  1123. RDPRU instruction = false
  1124. memory bandwidth enforcement = false
  1125. WBNOINVD instruction = false
  1126. IBPB: indirect branch prediction barrier = true
  1127. IBRS: indirect branch restr speculation = true
  1128. STIBP: 1 thr indirect branch predictor = true
  1129. STIBP always on preferred mode = false
  1130. ppin processor id number supported = false
  1131. SSBD: speculative store bypass disable = true
  1132. virtualized SSBD = false
  1133. SSBD fixed in hardware = false
  1134. Size Identifiers (0x80000008/ecx):
  1135. number of CPU cores = 0x1 (1)
  1136. ApicIdCoreIdSize = 0x0 (0)
  1137. performance time-stamp counter size = 0x0 (0)
  1138. Feature Extended Size (0x80000008/edx):
  1139. RDPRU instruction max input support = 0x0 (0)
  1140. (multi-processing synth) = none
  1141. (multi-processing method) = Intel leaf 0xb
  1142. (APIC widths synth): CORE_width=0 SMT_width=0
  1143. (APIC synth): PKG_ID=1 CORE_ID=0 SMT_ID=0
  1144. (uarch synth) = Intel Cascade Lake {Skylake}, 14nm
  1145. (synth) = Intel Scalable (2nd Gen) Bronze/Silver/Gold/Platinum (Cascade Lake B1/L1/R1) {Skylake}, 14nm
  1146. CPU 2:
  1147. vendor_id = "GenuineIntel"
  1148. version information (1/eax):
  1149. processor type = primary processor (0)
  1150. family = 0x6 (6)
  1151. model = 0x5 (5)
  1152. stepping id = 0x7 (7)
  1153. extended family = 0x0 (0)
  1154. extended model = 0x5 (5)
  1155. (family synth) = 0x6 (6)
  1156. (model synth) = 0x55 (85)
  1157. (simple synth) = Intel Core (unknown type) (Skylake / Skylake-X / Cascade Lake / Cascade Lake-X) {Skylake}, 14nm
  1158. miscellaneous (1/ebx):
  1159. process local APIC physical ID = 0x2 (2)
  1160. maximum IDs for CPUs in pkg = 0x0 (0)
  1161. CLFLUSH line size = 0x8 (8)
  1162. brand index = 0x0 (0)
  1163. brand id = 0x00 (0): unknown
  1164. feature information (1/edx):
  1165. x87 FPU on chip = true
  1166. VME: virtual-8086 mode enhancement = true
  1167. DE: debugging extensions = true
  1168. PSE: page size extensions = true
  1169. TSC: time stamp counter = true
  1170. RDMSR and WRMSR support = true
  1171. PAE: physical address extensions = true
  1172. MCE: machine check exception = true
  1173. CMPXCHG8B inst. = true
  1174. APIC on chip = true
  1175. SYSENTER and SYSEXIT = true
  1176. MTRR: memory type range registers = true
  1177. PTE global bit = true
  1178. MCA: machine check architecture = true
  1179. CMOV: conditional move/compare instr = true
  1180. PAT: page attribute table = true
  1181. PSE-36: page size extension = true
  1182. PSN: processor serial number = false
  1183. CLFLUSH instruction = true
  1184. DS: debug store = false
  1185. ACPI: thermal monitor and clock ctrl = false
  1186. MMX Technology = true
  1187. FXSAVE/FXRSTOR = true
  1188. SSE extensions = true
  1189. SSE2 extensions = true
  1190. SS: self snoop = true
  1191. hyper-threading / multi-core supported = false
  1192. TM: therm. monitor = false
  1193. IA64 = false
  1194. PBE: pending break event = false
  1195. feature information (1/ecx):
  1196. PNI/SSE3: Prescott New Instructions = true
  1197. PCLMULDQ instruction = true
  1198. DTES64: 64-bit debug store = false
  1199. MONITOR/MWAIT = false
  1200. CPL-qualified debug store = false
  1201. VMX: virtual machine extensions = true
  1202. SMX: safer mode extensions = false
  1203. Enhanced Intel SpeedStep Technology = false
  1204. TM2: thermal monitor 2 = false
  1205. SSSE3 extensions = true
  1206. context ID: adaptive or shared L1 data = false
  1207. SDBG: IA32_DEBUG_INTERFACE = false
  1208. FMA instruction = true
  1209. CMPXCHG16B instruction = true
  1210. xTPR disable = false
  1211. PDCM: perfmon and debug = false
  1212. PCID: process context identifiers = true
  1213. DCA: direct cache access = false
  1214. SSE4.1 extensions = true
  1215. SSE4.2 extensions = true
  1216. x2APIC: extended xAPIC support = true
  1217. MOVBE instruction = true
  1218. POPCNT instruction = true
  1219. time stamp counter deadline = true
  1220. AES instruction = true
  1221. XSAVE/XSTOR states = true
  1222. OS-enabled XSAVE/XSTOR = true
  1223. AVX: advanced vector extensions = true
  1224. F16C half-precision convert instruction = true
  1225. RDRAND instruction = true
  1226. hypervisor guest status = true
  1227. cache and TLB information (2):
  1228. 0x4d: L3 cache: 16M, 16-way, 64 byte lines
  1229. 0x7d: L2 cache: 2M, 8-way, 64 byte lines
  1230. 0x30: L1 cache: 32K, 8-way, 64 byte lines
  1231. 0x2c: L1 data cache: 32K, 8-way, 64 byte lines
  1232. processor serial number = 0005-0657-0000-0000-0000-0000
  1233. deterministic cache parameters (4):
  1234. --- cache 0 ---
  1235. cache type = data cache (1)
  1236. cache level = 0x1 (1)
  1237. self-initializing cache level = true
  1238. fully associative cache = false
  1239. maximum IDs for CPUs sharing cache = 0x0 (0)
  1240. maximum IDs for cores in pkg = 0x0 (0)
  1241. system coherency line size = 0x40 (64)
  1242. physical line partitions = 0x1 (1)
  1243. ways of associativity = 0x8 (8)
  1244. number of sets = 0x40 (64)
  1245. WBINVD/INVD acts on lower caches = true
  1246. inclusive to lower caches = false
  1247. complex cache indexing = false
  1248. number of sets (s) = 64
  1249. (size synth) = 32768 (32 KB)
  1250. --- cache 1 ---
  1251. cache type = instruction cache (2)
  1252. cache level = 0x1 (1)
  1253. self-initializing cache level = true
  1254. fully associative cache = false
  1255. maximum IDs for CPUs sharing cache = 0x0 (0)
  1256. maximum IDs for cores in pkg = 0x0 (0)
  1257. system coherency line size = 0x40 (64)
  1258. physical line partitions = 0x1 (1)
  1259. ways of associativity = 0x8 (8)
  1260. number of sets = 0x40 (64)
  1261. WBINVD/INVD acts on lower caches = true
  1262. inclusive to lower caches = false
  1263. complex cache indexing = false
  1264. number of sets (s) = 64
  1265. (size synth) = 32768 (32 KB)
  1266. --- cache 2 ---
  1267. cache type = unified cache (3)
  1268. cache level = 0x2 (2)
  1269. self-initializing cache level = true
  1270. fully associative cache = false
  1271. maximum IDs for CPUs sharing cache = 0x0 (0)
  1272. maximum IDs for cores in pkg = 0x0 (0)
  1273. system coherency line size = 0x40 (64)
  1274. physical line partitions = 0x1 (1)
  1275. ways of associativity = 0x10 (16)
  1276. number of sets = 0x1000 (4096)
  1277. WBINVD/INVD acts on lower caches = true
  1278. inclusive to lower caches = false
  1279. complex cache indexing = false
  1280. number of sets (s) = 4096
  1281. (size synth) = 4194304 (4 MB)
  1282. --- cache 3 ---
  1283. cache type = unified cache (3)
  1284. cache level = 0x3 (3)
  1285. self-initializing cache level = true
  1286. fully associative cache = false
  1287. maximum IDs for CPUs sharing cache = 0x0 (0)
  1288. maximum IDs for cores in pkg = 0x0 (0)
  1289. system coherency line size = 0x40 (64)
  1290. physical line partitions = 0x1 (1)
  1291. ways of associativity = 0x10 (16)
  1292. number of sets = 0x4000 (16384)
  1293. WBINVD/INVD acts on lower caches = false
  1294. inclusive to lower caches = true
  1295. complex cache indexing = true
  1296. number of sets (s) = 16384
  1297. (size synth) = 16777216 (16 MB)
  1298. MONITOR/MWAIT (5):
  1299. smallest monitor-line size (bytes) = 0x0 (0)
  1300. largest monitor-line size (bytes) = 0x0 (0)
  1301. enum of Monitor-MWAIT exts supported = true
  1302. supports intrs as break-event for MWAIT = true
  1303. number of C0 sub C-states using MWAIT = 0x0 (0)
  1304. number of C1 sub C-states using MWAIT = 0x0 (0)
  1305. number of C2 sub C-states using MWAIT = 0x0 (0)
  1306. number of C3 sub C-states using MWAIT = 0x0 (0)
  1307. number of C4 sub C-states using MWAIT = 0x0 (0)
  1308. number of C5 sub C-states using MWAIT = 0x0 (0)
  1309. number of C6 sub C-states using MWAIT = 0x0 (0)
  1310. number of C7 sub C-states using MWAIT = 0x0 (0)
  1311. Thermal and Power Management Features (6):
  1312. digital thermometer = false
  1313. Intel Turbo Boost Technology = false
  1314. ARAT always running APIC timer = true
  1315. PLN power limit notification = false
  1316. ECMD extended clock modulation duty = false
  1317. PTM package thermal management = false
  1318. HWP base registers = false
  1319. HWP notification = false
  1320. HWP activity window = false
  1321. HWP energy performance preference = false
  1322. HWP package level request = false
  1323. HDC base registers = false
  1324. Intel Turbo Boost Max Technology 3.0 = false
  1325. HWP capabilities = false
  1326. HWP PECI override = false
  1327. flexible HWP = false
  1328. IA32_HWP_REQUEST MSR fast access mode = false
  1329. HW_FEEDBACK MSRs supported = false
  1330. ignoring idle logical processor HWP req = false
  1331. enhanced hardware feedback interface = false
  1332. digital thermometer thresholds = 0x0 (0)
  1333. hardware coordination feedback = false
  1334. ACNT2 available = false
  1335. performance-energy bias capability = false
  1336. number of enh hardware feedback classes = 0x0 (0)
  1337. performance capability reporting = false
  1338. energy efficiency capability reporting = false
  1339. size of feedback struct (4KB pages) = 0x1 (1)
  1340. index of CPU's row in feedback struct = 0x0 (0)
  1341. extended feature flags (7):
  1342. FSGSBASE instructions = true
  1343. IA32_TSC_ADJUST MSR supported = true
  1344. SGX: Software Guard Extensions supported = false
  1345. BMI1 instructions = true
  1346. HLE hardware lock elision = false
  1347. AVX2: advanced vector extensions 2 = true
  1348. FDP_EXCPTN_ONLY = false
  1349. SMEP supervisor mode exec protection = true
  1350. BMI2 instructions = true
  1351. enhanced REP MOVSB/STOSB = true
  1352. INVPCID instruction = true
  1353. RTM: restricted transactional memory = false
  1354. RDT-CMT/PQoS cache monitoring = false
  1355. deprecated FPU CS/DS = false
  1356. MPX: intel memory protection extensions = true
  1357. RDT-CAT/PQE cache allocation = false
  1358. AVX512F: AVX-512 foundation instructions = true
  1359. AVX512DQ: double & quadword instructions = true
  1360. RDSEED instruction = true
  1361. ADX instructions = true
  1362. SMAP: supervisor mode access prevention = true
  1363. AVX512IFMA: fused multiply add = false
  1364. PCOMMIT instruction = false
  1365. CLFLUSHOPT instruction = true
  1366. CLWB instruction = true
  1367. Intel processor trace = false
  1368. AVX512PF: prefetch instructions = false
  1369. AVX512ER: exponent & reciprocal instrs = false
  1370. AVX512CD: conflict detection instrs = true
  1371. SHA instructions = false
  1372. AVX512BW: byte & word instructions = true
  1373. AVX512VL: vector length = true
  1374. PREFETCHWT1 = false
  1375. AVX512VBMI: vector byte manipulation = false
  1376. UMIP: user-mode instruction prevention = true
  1377. PKU protection keys for user-mode = true
  1378. OSPKE CR4.PKE and RDPKRU/WRPKRU = true
  1379. WAITPKG instructions = false
  1380. AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
  1381. CET_SS: CET shadow stack = false
  1382. GFNI: Galois Field New Instructions = false
  1383. VAES instructions = false
  1384. VPCLMULQDQ instruction = false
  1385. AVX512_VNNI: neural network instructions = true
  1386. AVX512_BITALG: bit count/shiffle = false
  1387. TME: Total Memory Encryption = false
  1388. AVX512: VPOPCNTDQ instruction = false
  1389. 5-level paging = false
  1390. BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
  1391. RDPID: read processor D supported = false
  1392. KL: key locker = false
  1393. CLDEMOTE supports cache line demote = false
  1394. MOVDIRI instruction = false
  1395. MOVDIR64B instruction = false
  1396. ENQCMD instruction = false
  1397. SGX_LC: SGX launch config supported = false
  1398. PKS: supervisor protection keys = false
  1399. AVX512_4VNNIW: neural network instrs = false
  1400. AVX512_4FMAPS: multiply acc single prec = false
  1401. fast short REP MOV = false
  1402. UINTR: user interrupts = false
  1403. AVX512_VP2INTERSECT: intersect mask regs = false
  1404. SRBDS mitigation MSR available = false
  1405. VERW MD_CLEAR microcode support = true
  1406. SERIALIZE instruction = false
  1407. hybrid part = false
  1408. TSXLDTRK: TSX suspend load addr tracking = false
  1409. PCONFIG instruction = false
  1410. LBR: architectural last branch records = false
  1411. CET_IBT: CET indirect branch tracking = false
  1412. AMX-BF16: tile bfloat16 support = false
  1413. AVX512_FP16: fp16 support = false
  1414. AMX-TILE: tile architecture support = false
  1415. AMX-INT8: tile 8-bit integer support = false
  1416. IBRS/IBPB: indirect branch restrictions = true
  1417. STIBP: 1 thr indirect branch predictor = true
  1418. L1D_FLUSH: IA32_FLUSH_CMD MSR = false
  1419. IA32_ARCH_CAPABILITIES MSR = true
  1420. IA32_CORE_CAPABILITIES MSR = false
  1421. SSBD: speculative store bypass disable = true
  1422. Direct Cache Access Parameters (9):
  1423. PLATFORM_DCA_CAP MSR bits = 0
  1424. Architecture Performance Monitoring Features (0xa):
  1425. version ID = 0x2 (2)
  1426. number of counters per logical processor = 0x4 (4)
  1427. bit width of counter = 0x30 (48)
  1428. length of EBX bit vector = 0x7 (7)
  1429. core cycle event not available = false
  1430. instruction retired event not available = false
  1431. reference cycles event not available = false
  1432. last-level cache ref event not available = false
  1433. last-level cache miss event not avail = false
  1434. branch inst retired event not available = false
  1435. branch mispred retired event not avail = false
  1436. fixed counter 0 supported = false
  1437. fixed counter 1 supported = false
  1438. fixed counter 2 supported = false
  1439. fixed counter 3 supported = false
  1440. fixed counter 4 supported = false
  1441. fixed counter 5 supported = false
  1442. fixed counter 6 supported = false
  1443. fixed counter 7 supported = false
  1444. fixed counter 8 supported = false
  1445. fixed counter 9 supported = false
  1446. fixed counter 10 supported = false
  1447. fixed counter 11 supported = false
  1448. fixed counter 12 supported = false
  1449. fixed counter 13 supported = false
  1450. fixed counter 14 supported = false
  1451. fixed counter 15 supported = false
  1452. fixed counter 16 supported = false
  1453. fixed counter 17 supported = false
  1454. fixed counter 18 supported = false
  1455. fixed counter 19 supported = false
  1456. fixed counter 20 supported = false
  1457. fixed counter 21 supported = false
  1458. fixed counter 22 supported = false
  1459. fixed counter 23 supported = false
  1460. fixed counter 24 supported = false
  1461. fixed counter 25 supported = false
  1462. fixed counter 26 supported = false
  1463. fixed counter 27 supported = false
  1464. fixed counter 28 supported = false
  1465. fixed counter 29 supported = false
  1466. fixed counter 30 supported = false
  1467. fixed counter 31 supported = false
  1468. number of fixed counters = 0x3 (3)
  1469. bit width of fixed counters = 0x30 (48)
  1470. anythread deprecation = false
  1471. x2APIC features / processor topology (0xb):
  1472. extended APIC ID = 2
  1473. --- level 0 ---
  1474. level number = 0x0 (0)
  1475. level type = thread (1)
  1476. bit width of level = 0x0 (0)
  1477. number of logical processors at level = 0x1 (1)
  1478. --- level 1 ---
  1479. level number = 0x1 (1)
  1480. level type = core (2)
  1481. bit width of level = 0x0 (0)
  1482. number of logical processors at level = 0x1 (1)
  1483. XSAVE features (0xd/0):
  1484. XCR0 lower 32 bits valid bit field mask = 0x000002ff
  1485. XCR0 upper 32 bits valid bit field mask = 0x00000000
  1486. XCR0 supported: x87 state = true
  1487. XCR0 supported: SSE state = true
  1488. XCR0 supported: AVX state = true
  1489. XCR0 supported: MPX BNDREGS = true
  1490. XCR0 supported: MPX BNDCSR = true
  1491. XCR0 supported: AVX-512 opmask = true
  1492. XCR0 supported: AVX-512 ZMM_Hi256 = true
  1493. XCR0 supported: AVX-512 Hi16_ZMM = true
  1494. IA32_XSS supported: PT state = false
  1495. XCR0 supported: PKRU state = true
  1496. XCR0 supported: CET_U state = false
  1497. XCR0 supported: CET_S state = false
  1498. IA32_XSS supported: HDC state = false
  1499. IA32_XSS supported: UINTR state = false
  1500. LBR supported = false
  1501. IA32_XSS supported: HWP state = false
  1502. XTILECFG supported = false
  1503. XTILEDATA supported = false
  1504. bytes required by fields in XCR0 = 0x00000a88 (2696)
  1505. bytes required by XSAVE/XRSTOR area = 0x00000a88 (2696)
  1506. XSAVE features (0xd/1):
  1507. XSAVEOPT instruction = true
  1508. XSAVEC instruction = true
  1509. XGETBV instruction = true
  1510. XSAVES/XRSTORS instructions = true
  1511. XFD: extended feature disable supported = false
  1512. SAVE area size in bytes = 0x00000a08 (2568)
  1513. IA32_XSS lower 32 bits valid bit field mask = 0x00000000
  1514. IA32_XSS upper 32 bits valid bit field mask = 0x00000000
  1515. AVX/YMM features (0xd/2):
  1516. AVX/YMM save state byte size = 0x00000100 (256)
  1517. AVX/YMM save state byte offset = 0x00000240 (576)
  1518. supported in IA32_XSS or XCR0 = XCR0 (user state)
  1519. 64-byte alignment in compacted XSAVE = false
  1520. XFD faulting supported = false
  1521. MPX BNDREGS features (0xd/3):
  1522. MPX BNDREGS save state byte size = 0x00000040 (64)
  1523. MPX BNDREGS save state byte offset = 0x000003c0 (960)
  1524. supported in IA32_XSS or XCR0 = XCR0 (user state)
  1525. 64-byte alignment in compacted XSAVE = false
  1526. XFD faulting supported = false
  1527. MPX BNDCSR features (0xd/4):
  1528. MPX BNDCSR save state byte size = 0x00000040 (64)
  1529. MPX BNDCSR save state byte offset = 0x00000400 (1024)
  1530. supported in IA32_XSS or XCR0 = XCR0 (user state)
  1531. 64-byte alignment in compacted XSAVE = false
  1532. XFD faulting supported = false
  1533. AVX-512 opmask features (0xd/5):
  1534. AVX-512 opmask save state byte size = 0x00000040 (64)
  1535. AVX-512 opmask save state byte offset = 0x00000440 (1088)
  1536. supported in IA32_XSS or XCR0 = XCR0 (user state)
  1537. 64-byte alignment in compacted XSAVE = false
  1538. XFD faulting supported = false
  1539. AVX-512 ZMM_Hi256 features (0xd/6):
  1540. AVX-512 ZMM_Hi256 save state byte size = 0x00000200 (512)
  1541. AVX-512 ZMM_Hi256 save state byte offset = 0x00000480 (1152)
  1542. supported in IA32_XSS or XCR0 = XCR0 (user state)
  1543. 64-byte alignment in compacted XSAVE = false
  1544. XFD faulting supported = false
  1545. AVX-512 Hi16_ZMM features (0xd/7):
  1546. AVX-512 Hi16_ZMM save state byte size = 0x00000400 (1024)
  1547. AVX-512 Hi16_ZMM save state byte offset = 0x00000680 (1664)
  1548. supported in IA32_XSS or XCR0 = XCR0 (user state)
  1549. 64-byte alignment in compacted XSAVE = false
  1550. XFD faulting supported = false
  1551. PKRU features (0xd/9):
  1552. PKRU save state byte size = 0x00000008 (8)
  1553. PKRU save state byte offset = 0x00000a80 (2688)
  1554. supported in IA32_XSS or XCR0 = XCR0 (user state)
  1555. 64-byte alignment in compacted XSAVE = false
  1556. XFD faulting supported = false
  1557. Quality of Service Monitoring Resource Type (0xf/0):
  1558. Maximum range of RMID = 0
  1559. supports L3 cache QoS monitoring = false
  1560. Resource Director Technology Allocation (0x10/0):
  1561. L3 cache allocation technology supported = false
  1562. L2 cache allocation technology supported = false
  1563. memory bandwidth allocation supported = false
  1564. 0x00000011 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
  1565. Software Guard Extensions (SGX) capability (0x12/0):
  1566. SGX1 supported = false
  1567. SGX2 supported = false
  1568. SGX ENCLV E*VIRTCHILD, ESETCONTEXT = false
  1569. SGX ENCLS ETRACKC, ERDINFO, ELDBC, ELDUC = false
  1570. MISCSELECT.EXINFO supported: #PF & #GP = false
  1571. MISCSELECT.CPINFO supported: #CP = false
  1572. MaxEnclaveSize_Not64 (log2) = 0x0 (0)
  1573. MaxEnclaveSize_64 (log2) = 0x0 (0)
  1574. 0x00000013 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
  1575. Intel Processor Trace (0x14):
  1576. IA32_RTIT_CR3_MATCH is accessible = false
  1577. configurable PSB & cycle-accurate = false
  1578. IP & TraceStop filtering; PT preserve = false
  1579. MTC timing packet; suppress COFI-based = false
  1580. PTWRITE support = false
  1581. power event trace support = false
  1582. ToPA output scheme support = false
  1583. ToPA can hold many output entries = false
  1584. single-range output scheme support = false
  1585. output to trace transport = false
  1586. IP payloads have LIP values & CS = false
  1587. Time Stamp Counter/Core Crystal Clock Information (0x15):
  1588. TSC/clock ratio = 0/0
  1589. nominal core crystal clock = 0 Hz
  1590. Processor Frequency Information (0x16):
  1591. Core Base Frequency (MHz) = 0x0 (0)
  1592. Core Maximum Frequency (MHz) = 0x0 (0)
  1593. Bus (Reference) Frequency (MHz) = 0x0 (0)
  1594. hypervisor_id = "KVMKVMKVM "
  1595. hypervisor features (0x40000001/eax):
  1596. kvmclock available at MSR 0x11 = true
  1597. delays unnecessary for PIO ops = true
  1598. mmu_op = false
  1599. kvmclock available at MSR 0x4b564d00 = true
  1600. async pf enable available by MSR = true
  1601. steal clock supported = true
  1602. guest EOI optimization enabled = true
  1603. guest spinlock optimization enabled = true
  1604. guest TLB flush optimization enabled = true
  1605. async PF VM exit enable available by MSR = false
  1606. guest send IPI optimization enabled = true
  1607. host HLT poll disable at MSR 0x4b564d05 = true
  1608. guest sched yield optimization enabled = true
  1609. guest uses intrs for page ready APF evs = false
  1610. stable: no guest per-cpu warps expected = true
  1611. hypervisor features (0x40000001/edx):
  1612. realtime hint: no unbound preemption = true
  1613. extended feature flags (0x80000001/edx):
  1614. SYSCALL and SYSRET instructions = true
  1615. execution disable = true
  1616. 1-GB large page support = true
  1617. RDTSCP = true
  1618. 64-bit extensions technology available = true
  1619. Intel feature flags (0x80000001/ecx):
  1620. LAHF/SAHF supported in 64-bit mode = true
  1621. LZCNT advanced bit manipulation = true
  1622. 3DNow! PREFETCH/PREFETCHW instructions = true
  1623. brand = "Intel(R) Xeon(R) Platinum 8275CL CPU @ 3.00GHz"
  1624. L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
  1625. instruction # entries = 0xff (255)
  1626. instruction associativity = 0x1 (1)
  1627. data # entries = 0xff (255)
  1628. data associativity = 0x1 (1)
  1629. L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
  1630. instruction # entries = 0xff (255)
  1631. instruction associativity = 0x1 (1)
  1632. data # entries = 0xff (255)
  1633. data associativity = 0x1 (1)
  1634. L1 data cache information (0x80000005/ecx):
  1635. line size (bytes) = 0x40 (64)
  1636. lines per tag = 0x1 (1)
  1637. associativity = 0x2 (2)
  1638. size (KB) = 0x40 (64)
  1639. L1 instruction cache information (0x80000005/edx):
  1640. line size (bytes) = 0x40 (64)
  1641. lines per tag = 0x1 (1)
  1642. associativity = 0x2 (2)
  1643. size (KB) = 0x40 (64)
  1644. L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
  1645. instruction # entries = 0x0 (0)
  1646. instruction associativity = L2 off (0)
  1647. data # entries = 0x0 (0)
  1648. data associativity = L2 off (0)
  1649. L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
  1650. instruction # entries = 0x200 (512)
  1651. instruction associativity = 4-way (4)
  1652. data # entries = 0x200 (512)
  1653. data associativity = 4-way (4)
  1654. L2 unified cache information (0x80000006/ecx):
  1655. line size (bytes) = 0x40 (64)
  1656. lines per tag = 0x1 (1)
  1657. associativity = 16-way (8)
  1658. size (KB) = 0x200 (512)
  1659. L3 cache information (0x80000006/edx):
  1660. line size (bytes) = 0x40 (64)
  1661. lines per tag = 0x1 (1)
  1662. associativity = 16-way (8)
  1663. size (in 512KB units) = 0x20 (32)
  1664. RAS Capability (0x80000007/ebx):
  1665. MCA overflow recovery support = false
  1666. SUCCOR support = false
  1667. HWA: hardware assert support = false
  1668. scalable MCA support = false
  1669. Advanced Power Management Features (0x80000007/ecx):
  1670. CmpUnitPwrSampleTimeRatio = 0x0 (0)
  1671. Advanced Power Management Features (0x80000007/edx):
  1672. TS: temperature sensing diode = false
  1673. FID: frequency ID control = false
  1674. VID: voltage ID control = false
  1675. TTP: thermal trip = false
  1676. TM: thermal monitor = false
  1677. STC: software thermal control = false
  1678. 100 MHz multiplier control = false
  1679. hardware P-State control = false
  1680. TscInvariant = false
  1681. CPB: core performance boost = false
  1682. read-only effective frequency interface = false
  1683. processor feedback interface = false
  1684. APM power reporting = false
  1685. connected standby = false
  1686. RAPL: running average power limit = false
  1687. Physical Address and Linear Address Size (0x80000008/eax):
  1688. maximum physical address bits = 0x2e (46)
  1689. maximum linear (virtual) address bits = 0x30 (48)
  1690. maximum guest physical address bits = 0x0 (0)
  1691. Extended Feature Extensions ID (0x80000008/ebx):
  1692. CLZERO instruction = false
  1693. instructions retired count support = false
  1694. always save/restore error pointers = false
  1695. RDPRU instruction = false
  1696. memory bandwidth enforcement = false
  1697. WBNOINVD instruction = false
  1698. IBPB: indirect branch prediction barrier = true
  1699. IBRS: indirect branch restr speculation = true
  1700. STIBP: 1 thr indirect branch predictor = true
  1701. STIBP always on preferred mode = false
  1702. ppin processor id number supported = false
  1703. SSBD: speculative store bypass disable = true
  1704. virtualized SSBD = false
  1705. SSBD fixed in hardware = false
  1706. Size Identifiers (0x80000008/ecx):
  1707. number of CPU cores = 0x1 (1)
  1708. ApicIdCoreIdSize = 0x0 (0)
  1709. performance time-stamp counter size = 0x0 (0)
  1710. Feature Extended Size (0x80000008/edx):
  1711. RDPRU instruction max input support = 0x0 (0)
  1712. (multi-processing synth) = none
  1713. (multi-processing method) = Intel leaf 0xb
  1714. (APIC widths synth): CORE_width=0 SMT_width=0
  1715. (APIC synth): PKG_ID=2 CORE_ID=0 SMT_ID=0
  1716. (uarch synth) = Intel Cascade Lake {Skylake}, 14nm
  1717. (synth) = Intel Scalable (2nd Gen) Bronze/Silver/Gold/Platinum (Cascade Lake B1/L1/R1) {Skylake}, 14nm
  1718. CPU 3:
  1719. vendor_id = "GenuineIntel"
  1720. version information (1/eax):
  1721. processor type = primary processor (0)
  1722. family = 0x6 (6)
  1723. model = 0x5 (5)
  1724. stepping id = 0x7 (7)
  1725. extended family = 0x0 (0)
  1726. extended model = 0x5 (5)
  1727. (family synth) = 0x6 (6)
  1728. (model synth) = 0x55 (85)
  1729. (simple synth) = Intel Core (unknown type) (Skylake / Skylake-X / Cascade Lake / Cascade Lake-X) {Skylake}, 14nm
  1730. miscellaneous (1/ebx):
  1731. process local APIC physical ID = 0x3 (3)
  1732. maximum IDs for CPUs in pkg = 0x0 (0)
  1733. CLFLUSH line size = 0x8 (8)
  1734. brand index = 0x0 (0)
  1735. brand id = 0x00 (0): unknown
  1736. feature information (1/edx):
  1737. x87 FPU on chip = true
  1738. VME: virtual-8086 mode enhancement = true
  1739. DE: debugging extensions = true
  1740. PSE: page size extensions = true
  1741. TSC: time stamp counter = true
  1742. RDMSR and WRMSR support = true
  1743. PAE: physical address extensions = true
  1744. MCE: machine check exception = true
  1745. CMPXCHG8B inst. = true
  1746. APIC on chip = true
  1747. SYSENTER and SYSEXIT = true
  1748. MTRR: memory type range registers = true
  1749. PTE global bit = true
  1750. MCA: machine check architecture = true
  1751. CMOV: conditional move/compare instr = true
  1752. PAT: page attribute table = true
  1753. PSE-36: page size extension = true
  1754. PSN: processor serial number = false
  1755. CLFLUSH instruction = true
  1756. DS: debug store = false
  1757. ACPI: thermal monitor and clock ctrl = false
  1758. MMX Technology = true
  1759. FXSAVE/FXRSTOR = true
  1760. SSE extensions = true
  1761. SSE2 extensions = true
  1762. SS: self snoop = true
  1763. hyper-threading / multi-core supported = false
  1764. TM: therm. monitor = false
  1765. IA64 = false
  1766. PBE: pending break event = false
  1767. feature information (1/ecx):
  1768. PNI/SSE3: Prescott New Instructions = true
  1769. PCLMULDQ instruction = true
  1770. DTES64: 64-bit debug store = false
  1771. MONITOR/MWAIT = false
  1772. CPL-qualified debug store = false
  1773. VMX: virtual machine extensions = true
  1774. SMX: safer mode extensions = false
  1775. Enhanced Intel SpeedStep Technology = false
  1776. TM2: thermal monitor 2 = false
  1777. SSSE3 extensions = true
  1778. context ID: adaptive or shared L1 data = false
  1779. SDBG: IA32_DEBUG_INTERFACE = false
  1780. FMA instruction = true
  1781. CMPXCHG16B instruction = true
  1782. xTPR disable = false
  1783. PDCM: perfmon and debug = false
  1784. PCID: process context identifiers = true
  1785. DCA: direct cache access = false
  1786. SSE4.1 extensions = true
  1787. SSE4.2 extensions = true
  1788. x2APIC: extended xAPIC support = true
  1789. MOVBE instruction = true
  1790. POPCNT instruction = true
  1791. time stamp counter deadline = true
  1792. AES instruction = true
  1793. XSAVE/XSTOR states = true
  1794. OS-enabled XSAVE/XSTOR = true
  1795. AVX: advanced vector extensions = true
  1796. F16C half-precision convert instruction = true
  1797. RDRAND instruction = true
  1798. hypervisor guest status = true
  1799. cache and TLB information (2):
  1800. 0x4d: L3 cache: 16M, 16-way, 64 byte lines
  1801. 0x7d: L2 cache: 2M, 8-way, 64 byte lines
  1802. 0x30: L1 cache: 32K, 8-way, 64 byte lines
  1803. 0x2c: L1 data cache: 32K, 8-way, 64 byte lines
  1804. processor serial number = 0005-0657-0000-0000-0000-0000
  1805. deterministic cache parameters (4):
  1806. --- cache 0 ---
  1807. cache type = data cache (1)
  1808. cache level = 0x1 (1)
  1809. self-initializing cache level = true
  1810. fully associative cache = false
  1811. maximum IDs for CPUs sharing cache = 0x0 (0)
  1812. maximum IDs for cores in pkg = 0x0 (0)
  1813. system coherency line size = 0x40 (64)
  1814. physical line partitions = 0x1 (1)
  1815. ways of associativity = 0x8 (8)
  1816. number of sets = 0x40 (64)
  1817. WBINVD/INVD acts on lower caches = true
  1818. inclusive to lower caches = false
  1819. complex cache indexing = false
  1820. number of sets (s) = 64
  1821. (size synth) = 32768 (32 KB)
  1822. --- cache 1 ---
  1823. cache type = instruction cache (2)
  1824. cache level = 0x1 (1)
  1825. self-initializing cache level = true
  1826. fully associative cache = false
  1827. maximum IDs for CPUs sharing cache = 0x0 (0)
  1828. maximum IDs for cores in pkg = 0x0 (0)
  1829. system coherency line size = 0x40 (64)
  1830. physical line partitions = 0x1 (1)
  1831. ways of associativity = 0x8 (8)
  1832. number of sets = 0x40 (64)
  1833. WBINVD/INVD acts on lower caches = true
  1834. inclusive to lower caches = false
  1835. complex cache indexing = false
  1836. number of sets (s) = 64
  1837. (size synth) = 32768 (32 KB)
  1838. --- cache 2 ---
  1839. cache type = unified cache (3)
  1840. cache level = 0x2 (2)
  1841. self-initializing cache level = true
  1842. fully associative cache = false
  1843. maximum IDs for CPUs sharing cache = 0x0 (0)
  1844. maximum IDs for cores in pkg = 0x0 (0)
  1845. system coherency line size = 0x40 (64)
  1846. physical line partitions = 0x1 (1)
  1847. ways of associativity = 0x10 (16)
  1848. number of sets = 0x1000 (4096)
  1849. WBINVD/INVD acts on lower caches = true
  1850. inclusive to lower caches = false
  1851. complex cache indexing = false
  1852. number of sets (s) = 4096
  1853. (size synth) = 4194304 (4 MB)
  1854. --- cache 3 ---
  1855. cache type = unified cache (3)
  1856. cache level = 0x3 (3)
  1857. self-initializing cache level = true
  1858. fully associative cache = false
  1859. maximum IDs for CPUs sharing cache = 0x0 (0)
  1860. maximum IDs for cores in pkg = 0x0 (0)
  1861. system coherency line size = 0x40 (64)
  1862. physical line partitions = 0x1 (1)
  1863. ways of associativity = 0x10 (16)
  1864. number of sets = 0x4000 (16384)
  1865. WBINVD/INVD acts on lower caches = false
  1866. inclusive to lower caches = true
  1867. complex cache indexing = true
  1868. number of sets (s) = 16384
  1869. (size synth) = 16777216 (16 MB)
  1870. MONITOR/MWAIT (5):
  1871. smallest monitor-line size (bytes) = 0x0 (0)
  1872. largest monitor-line size (bytes) = 0x0 (0)
  1873. enum of Monitor-MWAIT exts supported = true
  1874. supports intrs as break-event for MWAIT = true
  1875. number of C0 sub C-states using MWAIT = 0x0 (0)
  1876. number of C1 sub C-states using MWAIT = 0x0 (0)
  1877. number of C2 sub C-states using MWAIT = 0x0 (0)
  1878. number of C3 sub C-states using MWAIT = 0x0 (0)
  1879. number of C4 sub C-states using MWAIT = 0x0 (0)
  1880. number of C5 sub C-states using MWAIT = 0x0 (0)
  1881. number of C6 sub C-states using MWAIT = 0x0 (0)
  1882. number of C7 sub C-states using MWAIT = 0x0 (0)
  1883. Thermal and Power Management Features (6):
  1884. digital thermometer = false
  1885. Intel Turbo Boost Technology = false
  1886. ARAT always running APIC timer = true
  1887. PLN power limit notification = false
  1888. ECMD extended clock modulation duty = false
  1889. PTM package thermal management = false
  1890. HWP base registers = false
  1891. HWP notification = false
  1892. HWP activity window = false
  1893. HWP energy performance preference = false
  1894. HWP package level request = false
  1895. HDC base registers = false
  1896. Intel Turbo Boost Max Technology 3.0 = false
  1897. HWP capabilities = false
  1898. HWP PECI override = false
  1899. flexible HWP = false
  1900. IA32_HWP_REQUEST MSR fast access mode = false
  1901. HW_FEEDBACK MSRs supported = false
  1902. ignoring idle logical processor HWP req = false
  1903. enhanced hardware feedback interface = false
  1904. digital thermometer thresholds = 0x0 (0)
  1905. hardware coordination feedback = false
  1906. ACNT2 available = false
  1907. performance-energy bias capability = false
  1908. number of enh hardware feedback classes = 0x0 (0)
  1909. performance capability reporting = false
  1910. energy efficiency capability reporting = false
  1911. size of feedback struct (4KB pages) = 0x1 (1)
  1912. index of CPU's row in feedback struct = 0x0 (0)
  1913. extended feature flags (7):
  1914. FSGSBASE instructions = true
  1915. IA32_TSC_ADJUST MSR supported = true
  1916. SGX: Software Guard Extensions supported = false
  1917. BMI1 instructions = true
  1918. HLE hardware lock elision = false
  1919. AVX2: advanced vector extensions 2 = true
  1920. FDP_EXCPTN_ONLY = false
  1921. SMEP supervisor mode exec protection = true
  1922. BMI2 instructions = true
  1923. enhanced REP MOVSB/STOSB = true
  1924. INVPCID instruction = true
  1925. RTM: restricted transactional memory = false
  1926. RDT-CMT/PQoS cache monitoring = false
  1927. deprecated FPU CS/DS = false
  1928. MPX: intel memory protection extensions = true
  1929. RDT-CAT/PQE cache allocation = false
  1930. AVX512F: AVX-512 foundation instructions = true
  1931. AVX512DQ: double & quadword instructions = true
  1932. RDSEED instruction = true
  1933. ADX instructions = true
  1934. SMAP: supervisor mode access prevention = true
  1935. AVX512IFMA: fused multiply add = false
  1936. PCOMMIT instruction = false
  1937. CLFLUSHOPT instruction = true
  1938. CLWB instruction = true
  1939. Intel processor trace = false
  1940. AVX512PF: prefetch instructions = false
  1941. AVX512ER: exponent & reciprocal instrs = false
  1942. AVX512CD: conflict detection instrs = true
  1943. SHA instructions = false
  1944. AVX512BW: byte & word instructions = true
  1945. AVX512VL: vector length = true
  1946. PREFETCHWT1 = false
  1947. AVX512VBMI: vector byte manipulation = false
  1948. UMIP: user-mode instruction prevention = true
  1949. PKU protection keys for user-mode = true
  1950. OSPKE CR4.PKE and RDPKRU/WRPKRU = true
  1951. WAITPKG instructions = false
  1952. AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
  1953. CET_SS: CET shadow stack = false
  1954. GFNI: Galois Field New Instructions = false
  1955. VAES instructions = false
  1956. VPCLMULQDQ instruction = false
  1957. AVX512_VNNI: neural network instructions = true
  1958. AVX512_BITALG: bit count/shiffle = false
  1959. TME: Total Memory Encryption = false
  1960. AVX512: VPOPCNTDQ instruction = false
  1961. 5-level paging = false
  1962. BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
  1963. RDPID: read processor D supported = false
  1964. KL: key locker = false
  1965. CLDEMOTE supports cache line demote = false
  1966. MOVDIRI instruction = false
  1967. MOVDIR64B instruction = false
  1968. ENQCMD instruction = false
  1969. SGX_LC: SGX launch config supported = false
  1970. PKS: supervisor protection keys = false
  1971. AVX512_4VNNIW: neural network instrs = false
  1972. AVX512_4FMAPS: multiply acc single prec = false
  1973. fast short REP MOV = false
  1974. UINTR: user interrupts = false
  1975. AVX512_VP2INTERSECT: intersect mask regs = false
  1976. SRBDS mitigation MSR available = false
  1977. VERW MD_CLEAR microcode support = true
  1978. SERIALIZE instruction = false
  1979. hybrid part = false
  1980. TSXLDTRK: TSX suspend load addr tracking = false
  1981. PCONFIG instruction = false
  1982. LBR: architectural last branch records = false
  1983. CET_IBT: CET indirect branch tracking = false
  1984. AMX-BF16: tile bfloat16 support = false
  1985. AVX512_FP16: fp16 support = false
  1986. AMX-TILE: tile architecture support = false
  1987. AMX-INT8: tile 8-bit integer support = false
  1988. IBRS/IBPB: indirect branch restrictions = true
  1989. STIBP: 1 thr indirect branch predictor = true
  1990. L1D_FLUSH: IA32_FLUSH_CMD MSR = false
  1991. IA32_ARCH_CAPABILITIES MSR = true
  1992. IA32_CORE_CAPABILITIES MSR = false
  1993. SSBD: speculative store bypass disable = true
  1994. Direct Cache Access Parameters (9):
  1995. PLATFORM_DCA_CAP MSR bits = 0
  1996. Architecture Performance Monitoring Features (0xa):
  1997. version ID = 0x2 (2)
  1998. number of counters per logical processor = 0x4 (4)
  1999. bit width of counter = 0x30 (48)
  2000. length of EBX bit vector = 0x7 (7)
  2001. core cycle event not available = false
  2002. instruction retired event not available = false
  2003. reference cycles event not available = false
  2004. last-level cache ref event not available = false
  2005. last-level cache miss event not avail = false
  2006. branch inst retired event not available = false
  2007. branch mispred retired event not avail = false
  2008. fixed counter 0 supported = false
  2009. fixed counter 1 supported = false
  2010. fixed counter 2 supported = false
  2011. fixed counter 3 supported = false
  2012. fixed counter 4 supported = false
  2013. fixed counter 5 supported = false
  2014. fixed counter 6 supported = false
  2015. fixed counter 7 supported = false
  2016. fixed counter 8 supported = false
  2017. fixed counter 9 supported = false
  2018. fixed counter 10 supported = false
  2019. fixed counter 11 supported = false
  2020. fixed counter 12 supported = false
  2021. fixed counter 13 supported = false
  2022. fixed counter 14 supported = false
  2023. fixed counter 15 supported = false
  2024. fixed counter 16 supported = false
  2025. fixed counter 17 supported = false
  2026. fixed counter 18 supported = false
  2027. fixed counter 19 supported = false
  2028. fixed counter 20 supported = false
  2029. fixed counter 21 supported = false
  2030. fixed counter 22 supported = false
  2031. fixed counter 23 supported = false
  2032. fixed counter 24 supported = false
  2033. fixed counter 25 supported = false
  2034. fixed counter 26 supported = false
  2035. fixed counter 27 supported = false
  2036. fixed counter 28 supported = false
  2037. fixed counter 29 supported = false
  2038. fixed counter 30 supported = false
  2039. fixed counter 31 supported = false
  2040. number of fixed counters = 0x3 (3)
  2041. bit width of fixed counters = 0x30 (48)
  2042. anythread deprecation = false
  2043. x2APIC features / processor topology (0xb):
  2044. extended APIC ID = 3
  2045. --- level 0 ---
  2046. level number = 0x0 (0)
  2047. level type = thread (1)
  2048. bit width of level = 0x0 (0)
  2049. number of logical processors at level = 0x1 (1)
  2050. --- level 1 ---
  2051. level number = 0x1 (1)
  2052. level type = core (2)
  2053. bit width of level = 0x0 (0)
  2054. number of logical processors at level = 0x1 (1)
  2055. XSAVE features (0xd/0):
  2056. XCR0 lower 32 bits valid bit field mask = 0x000002ff
  2057. XCR0 upper 32 bits valid bit field mask = 0x00000000
  2058. XCR0 supported: x87 state = true
  2059. XCR0 supported: SSE state = true
  2060. XCR0 supported: AVX state = true
  2061. XCR0 supported: MPX BNDREGS = true
  2062. XCR0 supported: MPX BNDCSR = true
  2063. XCR0 supported: AVX-512 opmask = true
  2064. XCR0 supported: AVX-512 ZMM_Hi256 = true
  2065. XCR0 supported: AVX-512 Hi16_ZMM = true
  2066. IA32_XSS supported: PT state = false
  2067. XCR0 supported: PKRU state = true
  2068. XCR0 supported: CET_U state = false
  2069. XCR0 supported: CET_S state = false
  2070. IA32_XSS supported: HDC state = false
  2071. IA32_XSS supported: UINTR state = false
  2072. LBR supported = false
  2073. IA32_XSS supported: HWP state = false
  2074. XTILECFG supported = false
  2075. XTILEDATA supported = false
  2076. bytes required by fields in XCR0 = 0x00000a88 (2696)
  2077. bytes required by XSAVE/XRSTOR area = 0x00000a88 (2696)
  2078. XSAVE features (0xd/1):
  2079. XSAVEOPT instruction = true
  2080. XSAVEC instruction = true
  2081. XGETBV instruction = true
  2082. XSAVES/XRSTORS instructions = true
  2083. XFD: extended feature disable supported = false
  2084. SAVE area size in bytes = 0x00000a08 (2568)
  2085. IA32_XSS lower 32 bits valid bit field mask = 0x00000000
  2086. IA32_XSS upper 32 bits valid bit field mask = 0x00000000
  2087. AVX/YMM features (0xd/2):
  2088. AVX/YMM save state byte size = 0x00000100 (256)
  2089. AVX/YMM save state byte offset = 0x00000240 (576)
  2090. supported in IA32_XSS or XCR0 = XCR0 (user state)
  2091. 64-byte alignment in compacted XSAVE = false
  2092. XFD faulting supported = false
  2093. MPX BNDREGS features (0xd/3):
  2094. MPX BNDREGS save state byte size = 0x00000040 (64)
  2095. MPX BNDREGS save state byte offset = 0x000003c0 (960)
  2096. supported in IA32_XSS or XCR0 = XCR0 (user state)
  2097. 64-byte alignment in compacted XSAVE = false
  2098. XFD faulting supported = false
  2099. MPX BNDCSR features (0xd/4):
  2100. MPX BNDCSR save state byte size = 0x00000040 (64)
  2101. MPX BNDCSR save state byte offset = 0x00000400 (1024)
  2102. supported in IA32_XSS or XCR0 = XCR0 (user state)
  2103. 64-byte alignment in compacted XSAVE = false
  2104. XFD faulting supported = false
  2105. AVX-512 opmask features (0xd/5):
  2106. AVX-512 opmask save state byte size = 0x00000040 (64)
  2107. AVX-512 opmask save state byte offset = 0x00000440 (1088)
  2108. supported in IA32_XSS or XCR0 = XCR0 (user state)
  2109. 64-byte alignment in compacted XSAVE = false
  2110. XFD faulting supported = false
  2111. AVX-512 ZMM_Hi256 features (0xd/6):
  2112. AVX-512 ZMM_Hi256 save state byte size = 0x00000200 (512)
  2113. AVX-512 ZMM_Hi256 save state byte offset = 0x00000480 (1152)
  2114. supported in IA32_XSS or XCR0 = XCR0 (user state)
  2115. 64-byte alignment in compacted XSAVE = false
  2116. XFD faulting supported = false
  2117. AVX-512 Hi16_ZMM features (0xd/7):
  2118. AVX-512 Hi16_ZMM save state byte size = 0x00000400 (1024)
  2119. AVX-512 Hi16_ZMM save state byte offset = 0x00000680 (1664)
  2120. supported in IA32_XSS or XCR0 = XCR0 (user state)
  2121. 64-byte alignment in compacted XSAVE = false
  2122. XFD faulting supported = false
  2123. PKRU features (0xd/9):
  2124. PKRU save state byte size = 0x00000008 (8)
  2125. PKRU save state byte offset = 0x00000a80 (2688)
  2126. supported in IA32_XSS or XCR0 = XCR0 (user state)
  2127. 64-byte alignment in compacted XSAVE = false
  2128. XFD faulting supported = false
  2129. Quality of Service Monitoring Resource Type (0xf/0):
  2130. Maximum range of RMID = 0
  2131. supports L3 cache QoS monitoring = false
  2132. Resource Director Technology Allocation (0x10/0):
  2133. L3 cache allocation technology supported = false
  2134. L2 cache allocation technology supported = false
  2135. memory bandwidth allocation supported = false
  2136. 0x00000011 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
  2137. Software Guard Extensions (SGX) capability (0x12/0):
  2138. SGX1 supported = false
  2139. SGX2 supported = false
  2140. SGX ENCLV E*VIRTCHILD, ESETCONTEXT = false
  2141. SGX ENCLS ETRACKC, ERDINFO, ELDBC, ELDUC = false
  2142. MISCSELECT.EXINFO supported: #PF & #GP = false
  2143. MISCSELECT.CPINFO supported: #CP = false
  2144. MaxEnclaveSize_Not64 (log2) = 0x0 (0)
  2145. MaxEnclaveSize_64 (log2) = 0x0 (0)
  2146. 0x00000013 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
  2147. Intel Processor Trace (0x14):
  2148. IA32_RTIT_CR3_MATCH is accessible = false
  2149. configurable PSB & cycle-accurate = false
  2150. IP & TraceStop filtering; PT preserve = false
  2151. MTC timing packet; suppress COFI-based = false
  2152. PTWRITE support = false
  2153. power event trace support = false
  2154. ToPA output scheme support = false
  2155. ToPA can hold many output entries = false
  2156. single-range output scheme support = false
  2157. output to trace transport = false
  2158. IP payloads have LIP values & CS = false
  2159. Time Stamp Counter/Core Crystal Clock Information (0x15):
  2160. TSC/clock ratio = 0/0
  2161. nominal core crystal clock = 0 Hz
  2162. Processor Frequency Information (0x16):
  2163. Core Base Frequency (MHz) = 0x0 (0)
  2164. Core Maximum Frequency (MHz) = 0x0 (0)
  2165. Bus (Reference) Frequency (MHz) = 0x0 (0)
  2166. hypervisor_id = "KVMKVMKVM "
  2167. hypervisor features (0x40000001/eax):
  2168. kvmclock available at MSR 0x11 = true
  2169. delays unnecessary for PIO ops = true
  2170. mmu_op = false
  2171. kvmclock available at MSR 0x4b564d00 = true
  2172. async pf enable available by MSR = true
  2173. steal clock supported = true
  2174. guest EOI optimization enabled = true
  2175. guest spinlock optimization enabled = true
  2176. guest TLB flush optimization enabled = true
  2177. async PF VM exit enable available by MSR = false
  2178. guest send IPI optimization enabled = true
  2179. host HLT poll disable at MSR 0x4b564d05 = true
  2180. guest sched yield optimization enabled = true
  2181. guest uses intrs for page ready APF evs = false
  2182. stable: no guest per-cpu warps expected = true
  2183. hypervisor features (0x40000001/edx):
  2184. realtime hint: no unbound preemption = true
  2185. extended feature flags (0x80000001/edx):
  2186. SYSCALL and SYSRET instructions = true
  2187. execution disable = true
  2188. 1-GB large page support = true
  2189. RDTSCP = true
  2190. 64-bit extensions technology available = true
  2191. Intel feature flags (0x80000001/ecx):
  2192. LAHF/SAHF supported in 64-bit mode = true
  2193. LZCNT advanced bit manipulation = true
  2194. 3DNow! PREFETCH/PREFETCHW instructions = true
  2195. brand = "Intel(R) Xeon(R) Platinum 8275CL CPU @ 3.00GHz"
  2196. L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
  2197. instruction # entries = 0xff (255)
  2198. instruction associativity = 0x1 (1)
  2199. data # entries = 0xff (255)
  2200. data associativity = 0x1 (1)
  2201. L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
  2202. instruction # entries = 0xff (255)
  2203. instruction associativity = 0x1 (1)
  2204. data # entries = 0xff (255)
  2205. data associativity = 0x1 (1)
  2206. L1 data cache information (0x80000005/ecx):
  2207. line size (bytes) = 0x40 (64)
  2208. lines per tag = 0x1 (1)
  2209. associativity = 0x2 (2)
  2210. size (KB) = 0x40 (64)
  2211. L1 instruction cache information (0x80000005/edx):
  2212. line size (bytes) = 0x40 (64)
  2213. lines per tag = 0x1 (1)
  2214. associativity = 0x2 (2)
  2215. size (KB) = 0x40 (64)
  2216. L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
  2217. instruction # entries = 0x0 (0)
  2218. instruction associativity = L2 off (0)
  2219. data # entries = 0x0 (0)
  2220. data associativity = L2 off (0)
  2221. L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
  2222. instruction # entries = 0x200 (512)
  2223. instruction associativity = 4-way (4)
  2224. data # entries = 0x200 (512)
  2225. data associativity = 4-way (4)
  2226. L2 unified cache information (0x80000006/ecx):
  2227. line size (bytes) = 0x40 (64)
  2228. lines per tag = 0x1 (1)
  2229. associativity = 16-way (8)
  2230. size (KB) = 0x200 (512)
  2231. L3 cache information (0x80000006/edx):
  2232. line size (bytes) = 0x40 (64)
  2233. lines per tag = 0x1 (1)
  2234. associativity = 16-way (8)
  2235. size (in 512KB units) = 0x20 (32)
  2236. RAS Capability (0x80000007/ebx):
  2237. MCA overflow recovery support = false
  2238. SUCCOR support = false
  2239. HWA: hardware assert support = false
  2240. scalable MCA support = false
  2241. Advanced Power Management Features (0x80000007/ecx):
  2242. CmpUnitPwrSampleTimeRatio = 0x0 (0)
  2243. Advanced Power Management Features (0x80000007/edx):
  2244. TS: temperature sensing diode = false
  2245. FID: frequency ID control = false
  2246. VID: voltage ID control = false
  2247. TTP: thermal trip = false
  2248. TM: thermal monitor = false
  2249. STC: software thermal control = false
  2250. 100 MHz multiplier control = false
  2251. hardware P-State control = false
  2252. TscInvariant = false
  2253. CPB: core performance boost = false
  2254. read-only effective frequency interface = false
  2255. processor feedback interface = false
  2256. APM power reporting = false
  2257. connected standby = false
  2258. RAPL: running average power limit = false
  2259. Physical Address and Linear Address Size (0x80000008/eax):
  2260. maximum physical address bits = 0x2e (46)
  2261. maximum linear (virtual) address bits = 0x30 (48)
  2262. maximum guest physical address bits = 0x0 (0)
  2263. Extended Feature Extensions ID (0x80000008/ebx):
  2264. CLZERO instruction = false
  2265. instructions retired count support = false
  2266. always save/restore error pointers = false
  2267. RDPRU instruction = false
  2268. memory bandwidth enforcement = false
  2269. WBNOINVD instruction = false
  2270. IBPB: indirect branch prediction barrier = true
  2271. IBRS: indirect branch restr speculation = true
  2272. STIBP: 1 thr indirect branch predictor = true
  2273. STIBP always on preferred mode = false
  2274. ppin processor id number supported = false
  2275. SSBD: speculative store bypass disable = true
  2276. virtualized SSBD = false
  2277. SSBD fixed in hardware = false
  2278. Size Identifiers (0x80000008/ecx):
  2279. number of CPU cores = 0x1 (1)
  2280. ApicIdCoreIdSize = 0x0 (0)
  2281. performance time-stamp counter size = 0x0 (0)
  2282. Feature Extended Size (0x80000008/edx):
  2283. RDPRU instruction max input support = 0x0 (0)
  2284. (multi-processing synth) = none
  2285. (multi-processing method) = Intel leaf 0xb
  2286. (APIC widths synth): CORE_width=0 SMT_width=0
  2287. (APIC synth): PKG_ID=3 CORE_ID=0 SMT_ID=0
  2288. (uarch synth) = Intel Cascade Lake {Skylake}, 14nm
  2289. (synth) = Intel Scalable (2nd Gen) Bronze/Silver/Gold/Platinum (Cascade Lake B1/L1/R1) {Skylake}, 14nm
  2290. CPU 4:
  2291. vendor_id = "GenuineIntel"
  2292. version information (1/eax):
  2293. processor type = primary processor (0)
  2294. family = 0x6 (6)
  2295. model = 0x5 (5)
  2296. stepping id = 0x7 (7)
  2297. extended family = 0x0 (0)
  2298. extended model = 0x5 (5)
  2299. (family synth) = 0x6 (6)
  2300. (model synth) = 0x55 (85)
  2301. (simple synth) = Intel Core (unknown type) (Skylake / Skylake-X / Cascade Lake / Cascade Lake-X) {Skylake}, 14nm
  2302. miscellaneous (1/ebx):
  2303. process local APIC physical ID = 0x4 (4)
  2304. maximum IDs for CPUs in pkg = 0x0 (0)
  2305. CLFLUSH line size = 0x8 (8)
  2306. brand index = 0x0 (0)
  2307. brand id = 0x00 (0): unknown
  2308. feature information (1/edx):
  2309. x87 FPU on chip = true
  2310. VME: virtual-8086 mode enhancement = true
  2311. DE: debugging extensions = true
  2312. PSE: page size extensions = true
  2313. TSC: time stamp counter = true
  2314. RDMSR and WRMSR support = true
  2315. PAE: physical address extensions = true
  2316. MCE: machine check exception = true
  2317. CMPXCHG8B inst. = true
  2318. APIC on chip = true
  2319. SYSENTER and SYSEXIT = true
  2320. MTRR: memory type range registers = true
  2321. PTE global bit = true
  2322. MCA: machine check architecture = true
  2323. CMOV: conditional move/compare instr = true
  2324. PAT: page attribute table = true
  2325. PSE-36: page size extension = true
  2326. PSN: processor serial number = false
  2327. CLFLUSH instruction = true
  2328. DS: debug store = false
  2329. ACPI: thermal monitor and clock ctrl = false
  2330. MMX Technology = true
  2331. FXSAVE/FXRSTOR = true
  2332. SSE extensions = true
  2333. SSE2 extensions = true
  2334. SS: self snoop = true
  2335. hyper-threading / multi-core supported = false
  2336. TM: therm. monitor = false
  2337. IA64 = false
  2338. PBE: pending break event = false
  2339. feature information (1/ecx):
  2340. PNI/SSE3: Prescott New Instructions = true
  2341. PCLMULDQ instruction = true
  2342. DTES64: 64-bit debug store = false
  2343. MONITOR/MWAIT = false
  2344. CPL-qualified debug store = false
  2345. VMX: virtual machine extensions = true
  2346. SMX: safer mode extensions = false
  2347. Enhanced Intel SpeedStep Technology = false
  2348. TM2: thermal monitor 2 = false
  2349. SSSE3 extensions = true
  2350. context ID: adaptive or shared L1 data = false
  2351. SDBG: IA32_DEBUG_INTERFACE = false
  2352. FMA instruction = true
  2353. CMPXCHG16B instruction = true
  2354. xTPR disable = false
  2355. PDCM: perfmon and debug = false
  2356. PCID: process context identifiers = true
  2357. DCA: direct cache access = false
  2358. SSE4.1 extensions = true
  2359. SSE4.2 extensions = true
  2360. x2APIC: extended xAPIC support = true
  2361. MOVBE instruction = true
  2362. POPCNT instruction = true
  2363. time stamp counter deadline = true
  2364. AES instruction = true
  2365. XSAVE/XSTOR states = true
  2366. OS-enabled XSAVE/XSTOR = true
  2367. AVX: advanced vector extensions = true
  2368. F16C half-precision convert instruction = true
  2369. RDRAND instruction = true
  2370. hypervisor guest status = true
  2371. cache and TLB information (2):
  2372. 0x4d: L3 cache: 16M, 16-way, 64 byte lines
  2373. 0x7d: L2 cache: 2M, 8-way, 64 byte lines
  2374. 0x30: L1 cache: 32K, 8-way, 64 byte lines
  2375. 0x2c: L1 data cache: 32K, 8-way, 64 byte lines
  2376. processor serial number = 0005-0657-0000-0000-0000-0000
  2377. deterministic cache parameters (4):
  2378. --- cache 0 ---
  2379. cache type = data cache (1)
  2380. cache level = 0x1 (1)
  2381. self-initializing cache level = true
  2382. fully associative cache = false
  2383. maximum IDs for CPUs sharing cache = 0x0 (0)
  2384. maximum IDs for cores in pkg = 0x0 (0)
  2385. system coherency line size = 0x40 (64)
  2386. physical line partitions = 0x1 (1)
  2387. ways of associativity = 0x8 (8)
  2388. number of sets = 0x40 (64)
  2389. WBINVD/INVD acts on lower caches = true
  2390. inclusive to lower caches = false
  2391. complex cache indexing = false
  2392. number of sets (s) = 64
  2393. (size synth) = 32768 (32 KB)
  2394. --- cache 1 ---
  2395. cache type = instruction cache (2)
  2396. cache level = 0x1 (1)
  2397. self-initializing cache level = true
  2398. fully associative cache = false
  2399. maximum IDs for CPUs sharing cache = 0x0 (0)
  2400. maximum IDs for cores in pkg = 0x0 (0)
  2401. system coherency line size = 0x40 (64)
  2402. physical line partitions = 0x1 (1)
  2403. ways of associativity = 0x8 (8)
  2404. number of sets = 0x40 (64)
  2405. WBINVD/INVD acts on lower caches = true
  2406. inclusive to lower caches = false
  2407. complex cache indexing = false
  2408. number of sets (s) = 64
  2409. (size synth) = 32768 (32 KB)
  2410. --- cache 2 ---
  2411. cache type = unified cache (3)
  2412. cache level = 0x2 (2)
  2413. self-initializing cache level = true
  2414. fully associative cache = false
  2415. maximum IDs for CPUs sharing cache = 0x0 (0)
  2416. maximum IDs for cores in pkg = 0x0 (0)
  2417. system coherency line size = 0x40 (64)
  2418. physical line partitions = 0x1 (1)
  2419. ways of associativity = 0x10 (16)
  2420. number of sets = 0x1000 (4096)
  2421. WBINVD/INVD acts on lower caches = true
  2422. inclusive to lower caches = false
  2423. complex cache indexing = false
  2424. number of sets (s) = 4096
  2425. (size synth) = 4194304 (4 MB)
  2426. --- cache 3 ---
  2427. cache type = unified cache (3)
  2428. cache level = 0x3 (3)
  2429. self-initializing cache level = true
  2430. fully associative cache = false
  2431. maximum IDs for CPUs sharing cache = 0x0 (0)
  2432. maximum IDs for cores in pkg = 0x0 (0)
  2433. system coherency line size = 0x40 (64)
  2434. physical line partitions = 0x1 (1)
  2435. ways of associativity = 0x10 (16)
  2436. number of sets = 0x4000 (16384)
  2437. WBINVD/INVD acts on lower caches = false
  2438. inclusive to lower caches = true
  2439. complex cache indexing = true
  2440. number of sets (s) = 16384
  2441. (size synth) = 16777216 (16 MB)
  2442. MONITOR/MWAIT (5):
  2443. smallest monitor-line size (bytes) = 0x0 (0)
  2444. largest monitor-line size (bytes) = 0x0 (0)
  2445. enum of Monitor-MWAIT exts supported = true
  2446. supports intrs as break-event for MWAIT = true
  2447. number of C0 sub C-states using MWAIT = 0x0 (0)
  2448. number of C1 sub C-states using MWAIT = 0x0 (0)
  2449. number of C2 sub C-states using MWAIT = 0x0 (0)
  2450. number of C3 sub C-states using MWAIT = 0x0 (0)
  2451. number of C4 sub C-states using MWAIT = 0x0 (0)
  2452. number of C5 sub C-states using MWAIT = 0x0 (0)
  2453. number of C6 sub C-states using MWAIT = 0x0 (0)
  2454. number of C7 sub C-states using MWAIT = 0x0 (0)
  2455. Thermal and Power Management Features (6):
  2456. digital thermometer = false
  2457. Intel Turbo Boost Technology = false
  2458. ARAT always running APIC timer = true
  2459. PLN power limit notification = false
  2460. ECMD extended clock modulation duty = false
  2461. PTM package thermal management = false
  2462. HWP base registers = false
  2463. HWP notification = false
  2464. HWP activity window = false
  2465. HWP energy performance preference = false
  2466. HWP package level request = false
  2467. HDC base registers = false
  2468. Intel Turbo Boost Max Technology 3.0 = false
  2469. HWP capabilities = false
  2470. HWP PECI override = false
  2471. flexible HWP = false
  2472. IA32_HWP_REQUEST MSR fast access mode = false
  2473. HW_FEEDBACK MSRs supported = false
  2474. ignoring idle logical processor HWP req = false
  2475. enhanced hardware feedback interface = false
  2476. digital thermometer thresholds = 0x0 (0)
  2477. hardware coordination feedback = false
  2478. ACNT2 available = false
  2479. performance-energy bias capability = false
  2480. number of enh hardware feedback classes = 0x0 (0)
  2481. performance capability reporting = false
  2482. energy efficiency capability reporting = false
  2483. size of feedback struct (4KB pages) = 0x1 (1)
  2484. index of CPU's row in feedback struct = 0x0 (0)
  2485. extended feature flags (7):
  2486. FSGSBASE instructions = true
  2487. IA32_TSC_ADJUST MSR supported = true
  2488. SGX: Software Guard Extensions supported = false
  2489. BMI1 instructions = true
  2490. HLE hardware lock elision = false
  2491. AVX2: advanced vector extensions 2 = true
  2492. FDP_EXCPTN_ONLY = false
  2493. SMEP supervisor mode exec protection = true
  2494. BMI2 instructions = true
  2495. enhanced REP MOVSB/STOSB = true
  2496. INVPCID instruction = true
  2497. RTM: restricted transactional memory = false
  2498. RDT-CMT/PQoS cache monitoring = false
  2499. deprecated FPU CS/DS = false
  2500. MPX: intel memory protection extensions = true
  2501. RDT-CAT/PQE cache allocation = false
  2502. AVX512F: AVX-512 foundation instructions = true
  2503. AVX512DQ: double & quadword instructions = true
  2504. RDSEED instruction = true
  2505. ADX instructions = true
  2506. SMAP: supervisor mode access prevention = true
  2507. AVX512IFMA: fused multiply add = false
  2508. PCOMMIT instruction = false
  2509. CLFLUSHOPT instruction = true
  2510. CLWB instruction = true
  2511. Intel processor trace = false
  2512. AVX512PF: prefetch instructions = false
  2513. AVX512ER: exponent & reciprocal instrs = false
  2514. AVX512CD: conflict detection instrs = true
  2515. SHA instructions = false
  2516. AVX512BW: byte & word instructions = true
  2517. AVX512VL: vector length = true
  2518. PREFETCHWT1 = false
  2519. AVX512VBMI: vector byte manipulation = false
  2520. UMIP: user-mode instruction prevention = true
  2521. PKU protection keys for user-mode = true
  2522. OSPKE CR4.PKE and RDPKRU/WRPKRU = true
  2523. WAITPKG instructions = false
  2524. AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
  2525. CET_SS: CET shadow stack = false
  2526. GFNI: Galois Field New Instructions = false
  2527. VAES instructions = false
  2528. VPCLMULQDQ instruction = false
  2529. AVX512_VNNI: neural network instructions = true
  2530. AVX512_BITALG: bit count/shiffle = false
  2531. TME: Total Memory Encryption = false
  2532. AVX512: VPOPCNTDQ instruction = false
  2533. 5-level paging = false
  2534. BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
  2535. RDPID: read processor D supported = false
  2536. KL: key locker = false
  2537. CLDEMOTE supports cache line demote = false
  2538. MOVDIRI instruction = false
  2539. MOVDIR64B instruction = false
  2540. ENQCMD instruction = false
  2541. SGX_LC: SGX launch config supported = false
  2542. PKS: supervisor protection keys = false
  2543. AVX512_4VNNIW: neural network instrs = false
  2544. AVX512_4FMAPS: multiply acc single prec = false
  2545. fast short REP MOV = false
  2546. UINTR: user interrupts = false
  2547. AVX512_VP2INTERSECT: intersect mask regs = false
  2548. SRBDS mitigation MSR available = false
  2549. VERW MD_CLEAR microcode support = true
  2550. SERIALIZE instruction = false
  2551. hybrid part = false
  2552. TSXLDTRK: TSX suspend load addr tracking = false
  2553. PCONFIG instruction = false
  2554. LBR: architectural last branch records = false
  2555. CET_IBT: CET indirect branch tracking = false
  2556. AMX-BF16: tile bfloat16 support = false
  2557. AVX512_FP16: fp16 support = false
  2558. AMX-TILE: tile architecture support = false
  2559. AMX-INT8: tile 8-bit integer support = false
  2560. IBRS/IBPB: indirect branch restrictions = true
  2561. STIBP: 1 thr indirect branch predictor = true
  2562. L1D_FLUSH: IA32_FLUSH_CMD MSR = false
  2563. IA32_ARCH_CAPABILITIES MSR = true
  2564. IA32_CORE_CAPABILITIES MSR = false
  2565. SSBD: speculative store bypass disable = true
  2566. Direct Cache Access Parameters (9):
  2567. PLATFORM_DCA_CAP MSR bits = 0
  2568. Architecture Performance Monitoring Features (0xa):
  2569. version ID = 0x2 (2)
  2570. number of counters per logical processor = 0x4 (4)
  2571. bit width of counter = 0x30 (48)
  2572. length of EBX bit vector = 0x7 (7)
  2573. core cycle event not available = false
  2574. instruction retired event not available = false
  2575. reference cycles event not available = false
  2576. last-level cache ref event not available = false
  2577. last-level cache miss event not avail = false
  2578. branch inst retired event not available = false
  2579. branch mispred retired event not avail = false
  2580. fixed counter 0 supported = false
  2581. fixed counter 1 supported = false
  2582. fixed counter 2 supported = false
  2583. fixed counter 3 supported = false
  2584. fixed counter 4 supported = false
  2585. fixed counter 5 supported = false
  2586. fixed counter 6 supported = false
  2587. fixed counter 7 supported = false
  2588. fixed counter 8 supported = false
  2589. fixed counter 9 supported = false
  2590. fixed counter 10 supported = false
  2591. fixed counter 11 supported = false
  2592. fixed counter 12 supported = false
  2593. fixed counter 13 supported = false
  2594. fixed counter 14 supported = false
  2595. fixed counter 15 supported = false
  2596. fixed counter 16 supported = false
  2597. fixed counter 17 supported = false
  2598. fixed counter 18 supported = false
  2599. fixed counter 19 supported = false
  2600. fixed counter 20 supported = false
  2601. fixed counter 21 supported = false
  2602. fixed counter 22 supported = false
  2603. fixed counter 23 supported = false
  2604. fixed counter 24 supported = false
  2605. fixed counter 25 supported = false
  2606. fixed counter 26 supported = false
  2607. fixed counter 27 supported = false
  2608. fixed counter 28 supported = false
  2609. fixed counter 29 supported = false
  2610. fixed counter 30 supported = false
  2611. fixed counter 31 supported = false
  2612. number of fixed counters = 0x3 (3)
  2613. bit width of fixed counters = 0x30 (48)
  2614. anythread deprecation = false
  2615. x2APIC features / processor topology (0xb):
  2616. extended APIC ID = 4
  2617. --- level 0 ---
  2618. level number = 0x0 (0)
  2619. level type = thread (1)
  2620. bit width of level = 0x0 (0)
  2621. number of logical processors at level = 0x1 (1)
  2622. --- level 1 ---
  2623. level number = 0x1 (1)
  2624. level type = core (2)
  2625. bit width of level = 0x0 (0)
  2626. number of logical processors at level = 0x1 (1)
  2627. XSAVE features (0xd/0):
  2628. XCR0 lower 32 bits valid bit field mask = 0x000002ff
  2629. XCR0 upper 32 bits valid bit field mask = 0x00000000
  2630. XCR0 supported: x87 state = true
  2631. XCR0 supported: SSE state = true
  2632. XCR0 supported: AVX state = true
  2633. XCR0 supported: MPX BNDREGS = true
  2634. XCR0 supported: MPX BNDCSR = true
  2635. XCR0 supported: AVX-512 opmask = true
  2636. XCR0 supported: AVX-512 ZMM_Hi256 = true
  2637. XCR0 supported: AVX-512 Hi16_ZMM = true
  2638. IA32_XSS supported: PT state = false
  2639. XCR0 supported: PKRU state = true
  2640. XCR0 supported: CET_U state = false
  2641. XCR0 supported: CET_S state = false
  2642. IA32_XSS supported: HDC state = false
  2643. IA32_XSS supported: UINTR state = false
  2644. LBR supported = false
  2645. IA32_XSS supported: HWP state = false
  2646. XTILECFG supported = false
  2647. XTILEDATA supported = false
  2648. bytes required by fields in XCR0 = 0x00000a88 (2696)
  2649. bytes required by XSAVE/XRSTOR area = 0x00000a88 (2696)
  2650. XSAVE features (0xd/1):
  2651. XSAVEOPT instruction = true
  2652. XSAVEC instruction = true
  2653. XGETBV instruction = true
  2654. XSAVES/XRSTORS instructions = true
  2655. XFD: extended feature disable supported = false
  2656. SAVE area size in bytes = 0x00000a08 (2568)
  2657. IA32_XSS lower 32 bits valid bit field mask = 0x00000000
  2658. IA32_XSS upper 32 bits valid bit field mask = 0x00000000
  2659. AVX/YMM features (0xd/2):
  2660. AVX/YMM save state byte size = 0x00000100 (256)
  2661. AVX/YMM save state byte offset = 0x00000240 (576)
  2662. supported in IA32_XSS or XCR0 = XCR0 (user state)
  2663. 64-byte alignment in compacted XSAVE = false
  2664. XFD faulting supported = false
  2665. MPX BNDREGS features (0xd/3):
  2666. MPX BNDREGS save state byte size = 0x00000040 (64)
  2667. MPX BNDREGS save state byte offset = 0x000003c0 (960)
  2668. supported in IA32_XSS or XCR0 = XCR0 (user state)
  2669. 64-byte alignment in compacted XSAVE = false
  2670. XFD faulting supported = false
  2671. MPX BNDCSR features (0xd/4):
  2672. MPX BNDCSR save state byte size = 0x00000040 (64)
  2673. MPX BNDCSR save state byte offset = 0x00000400 (1024)
  2674. supported in IA32_XSS or XCR0 = XCR0 (user state)
  2675. 64-byte alignment in compacted XSAVE = false
  2676. XFD faulting supported = false
  2677. AVX-512 opmask features (0xd/5):
  2678. AVX-512 opmask save state byte size = 0x00000040 (64)
  2679. AVX-512 opmask save state byte offset = 0x00000440 (1088)
  2680. supported in IA32_XSS or XCR0 = XCR0 (user state)
  2681. 64-byte alignment in compacted XSAVE = false
  2682. XFD faulting supported = false
  2683. AVX-512 ZMM_Hi256 features (0xd/6):
  2684. AVX-512 ZMM_Hi256 save state byte size = 0x00000200 (512)
  2685. AVX-512 ZMM_Hi256 save state byte offset = 0x00000480 (1152)
  2686. supported in IA32_XSS or XCR0 = XCR0 (user state)
  2687. 64-byte alignment in compacted XSAVE = false
  2688. XFD faulting supported = false
  2689. AVX-512 Hi16_ZMM features (0xd/7):
  2690. AVX-512 Hi16_ZMM save state byte size = 0x00000400 (1024)
  2691. AVX-512 Hi16_ZMM save state byte offset = 0x00000680 (1664)
  2692. supported in IA32_XSS or XCR0 = XCR0 (user state)
  2693. 64-byte alignment in compacted XSAVE = false
  2694. XFD faulting supported = false
  2695. PKRU features (0xd/9):
  2696. PKRU save state byte size = 0x00000008 (8)
  2697. PKRU save state byte offset = 0x00000a80 (2688)
  2698. supported in IA32_XSS or XCR0 = XCR0 (user state)
  2699. 64-byte alignment in compacted XSAVE = false
  2700. XFD faulting supported = false
  2701. Quality of Service Monitoring Resource Type (0xf/0):
  2702. Maximum range of RMID = 0
  2703. supports L3 cache QoS monitoring = false
  2704. Resource Director Technology Allocation (0x10/0):
  2705. L3 cache allocation technology supported = false
  2706. L2 cache allocation technology supported = false
  2707. memory bandwidth allocation supported = false
  2708. 0x00000011 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
  2709. Software Guard Extensions (SGX) capability (0x12/0):
  2710. SGX1 supported = false
  2711. SGX2 supported = false
  2712. SGX ENCLV E*VIRTCHILD, ESETCONTEXT = false
  2713. SGX ENCLS ETRACKC, ERDINFO, ELDBC, ELDUC = false
  2714. MISCSELECT.EXINFO supported: #PF & #GP = false
  2715. MISCSELECT.CPINFO supported: #CP = false
  2716. MaxEnclaveSize_Not64 (log2) = 0x0 (0)
  2717. MaxEnclaveSize_64 (log2) = 0x0 (0)
  2718. 0x00000013 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
  2719. Intel Processor Trace (0x14):
  2720. IA32_RTIT_CR3_MATCH is accessible = false
  2721. configurable PSB & cycle-accurate = false
  2722. IP & TraceStop filtering; PT preserve = false
  2723. MTC timing packet; suppress COFI-based = false
  2724. PTWRITE support = false
  2725. power event trace support = false
  2726. ToPA output scheme support = false
  2727. ToPA can hold many output entries = false
  2728. single-range output scheme support = false
  2729. output to trace transport = false
  2730. IP payloads have LIP values & CS = false
  2731. Time Stamp Counter/Core Crystal Clock Information (0x15):
  2732. TSC/clock ratio = 0/0
  2733. nominal core crystal clock = 0 Hz
  2734. Processor Frequency Information (0x16):
  2735. Core Base Frequency (MHz) = 0x0 (0)
  2736. Core Maximum Frequency (MHz) = 0x0 (0)
  2737. Bus (Reference) Frequency (MHz) = 0x0 (0)
  2738. hypervisor_id = "KVMKVMKVM "
  2739. hypervisor features (0x40000001/eax):
  2740. kvmclock available at MSR 0x11 = true
  2741. delays unnecessary for PIO ops = true
  2742. mmu_op = false
  2743. kvmclock available at MSR 0x4b564d00 = true
  2744. async pf enable available by MSR = true
  2745. steal clock supported = true
  2746. guest EOI optimization enabled = true
  2747. guest spinlock optimization enabled = true
  2748. guest TLB flush optimization enabled = true
  2749. async PF VM exit enable available by MSR = false
  2750. guest send IPI optimization enabled = true
  2751. host HLT poll disable at MSR 0x4b564d05 = true
  2752. guest sched yield optimization enabled = true
  2753. guest uses intrs for page ready APF evs = false
  2754. stable: no guest per-cpu warps expected = true
  2755. hypervisor features (0x40000001/edx):
  2756. realtime hint: no unbound preemption = true
  2757. extended feature flags (0x80000001/edx):
  2758. SYSCALL and SYSRET instructions = true
  2759. execution disable = true
  2760. 1-GB large page support = true
  2761. RDTSCP = true
  2762. 64-bit extensions technology available = true
  2763. Intel feature flags (0x80000001/ecx):
  2764. LAHF/SAHF supported in 64-bit mode = true
  2765. LZCNT advanced bit manipulation = true
  2766. 3DNow! PREFETCH/PREFETCHW instructions = true
  2767. brand = "Intel(R) Xeon(R) Platinum 8275CL CPU @ 3.00GHz"
  2768. L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
  2769. instruction # entries = 0xff (255)
  2770. instruction associativity = 0x1 (1)
  2771. data # entries = 0xff (255)
  2772. data associativity = 0x1 (1)
  2773. L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
  2774. instruction # entries = 0xff (255)
  2775. instruction associativity = 0x1 (1)
  2776. data # entries = 0xff (255)
  2777. data associativity = 0x1 (1)
  2778. L1 data cache information (0x80000005/ecx):
  2779. line size (bytes) = 0x40 (64)
  2780. lines per tag = 0x1 (1)
  2781. associativity = 0x2 (2)
  2782. size (KB) = 0x40 (64)
  2783. L1 instruction cache information (0x80000005/edx):
  2784. line size (bytes) = 0x40 (64)
  2785. lines per tag = 0x1 (1)
  2786. associativity = 0x2 (2)
  2787. size (KB) = 0x40 (64)
  2788. L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
  2789. instruction # entries = 0x0 (0)
  2790. instruction associativity = L2 off (0)
  2791. data # entries = 0x0 (0)
  2792. data associativity = L2 off (0)
  2793. L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
  2794. instruction # entries = 0x200 (512)
  2795. instruction associativity = 4-way (4)
  2796. data # entries = 0x200 (512)
  2797. data associativity = 4-way (4)
  2798. L2 unified cache information (0x80000006/ecx):
  2799. line size (bytes) = 0x40 (64)
  2800. lines per tag = 0x1 (1)
  2801. associativity = 16-way (8)
  2802. size (KB) = 0x200 (512)
  2803. L3 cache information (0x80000006/edx):
  2804. line size (bytes) = 0x40 (64)
  2805. lines per tag = 0x1 (1)
  2806. associativity = 16-way (8)
  2807. size (in 512KB units) = 0x20 (32)
  2808. RAS Capability (0x80000007/ebx):
  2809. MCA overflow recovery support = false
  2810. SUCCOR support = false
  2811. HWA: hardware assert support = false
  2812. scalable MCA support = false
  2813. Advanced Power Management Features (0x80000007/ecx):
  2814. CmpUnitPwrSampleTimeRatio = 0x0 (0)
  2815. Advanced Power Management Features (0x80000007/edx):
  2816. TS: temperature sensing diode = false
  2817. FID: frequency ID control = false
  2818. VID: voltage ID control = false
  2819. TTP: thermal trip = false
  2820. TM: thermal monitor = false
  2821. STC: software thermal control = false
  2822. 100 MHz multiplier control = false
  2823. hardware P-State control = false
  2824. TscInvariant = false
  2825. CPB: core performance boost = false
  2826. read-only effective frequency interface = false
  2827. processor feedback interface = false
  2828. APM power reporting = false
  2829. connected standby = false
  2830. RAPL: running average power limit = false
  2831. Physical Address and Linear Address Size (0x80000008/eax):
  2832. maximum physical address bits = 0x2e (46)
  2833. maximum linear (virtual) address bits = 0x30 (48)
  2834. maximum guest physical address bits = 0x0 (0)
  2835. Extended Feature Extensions ID (0x80000008/ebx):
  2836. CLZERO instruction = false
  2837. instructions retired count support = false
  2838. always save/restore error pointers = false
  2839. RDPRU instruction = false
  2840. memory bandwidth enforcement = false
  2841. WBNOINVD instruction = false
  2842. IBPB: indirect branch prediction barrier = true
  2843. IBRS: indirect branch restr speculation = true
  2844. STIBP: 1 thr indirect branch predictor = true
  2845. STIBP always on preferred mode = false
  2846. ppin processor id number supported = false
  2847. SSBD: speculative store bypass disable = true
  2848. virtualized SSBD = false
  2849. SSBD fixed in hardware = false
  2850. Size Identifiers (0x80000008/ecx):
  2851. number of CPU cores = 0x1 (1)
  2852. ApicIdCoreIdSize = 0x0 (0)
  2853. performance time-stamp counter size = 0x0 (0)
  2854. Feature Extended Size (0x80000008/edx):
  2855. RDPRU instruction max input support = 0x0 (0)
  2856. (multi-processing synth) = none
  2857. (multi-processing method) = Intel leaf 0xb
  2858. (APIC widths synth): CORE_width=0 SMT_width=0
  2859. (APIC synth): PKG_ID=4 CORE_ID=0 SMT_ID=0
  2860. (uarch synth) = Intel Cascade Lake {Skylake}, 14nm
  2861. (synth) = Intel Scalable (2nd Gen) Bronze/Silver/Gold/Platinum (Cascade Lake B1/L1/R1) {Skylake}, 14nm
  2862. CPU 5:
  2863. vendor_id = "GenuineIntel"
  2864. version information (1/eax):
  2865. processor type = primary processor (0)
  2866. family = 0x6 (6)
  2867. model = 0x5 (5)
  2868. stepping id = 0x7 (7)
  2869. extended family = 0x0 (0)
  2870. extended model = 0x5 (5)
  2871. (family synth) = 0x6 (6)
  2872. (model synth) = 0x55 (85)
  2873. (simple synth) = Intel Core (unknown type) (Skylake / Skylake-X / Cascade Lake / Cascade Lake-X) {Skylake}, 14nm
  2874. miscellaneous (1/ebx):
  2875. process local APIC physical ID = 0x5 (5)
  2876. maximum IDs for CPUs in pkg = 0x0 (0)
  2877. CLFLUSH line size = 0x8 (8)
  2878. brand index = 0x0 (0)
  2879. brand id = 0x00 (0): unknown
  2880. feature information (1/edx):
  2881. x87 FPU on chip = true
  2882. VME: virtual-8086 mode enhancement = true
  2883. DE: debugging extensions = true
  2884. PSE: page size extensions = true
  2885. TSC: time stamp counter = true
  2886. RDMSR and WRMSR support = true
  2887. PAE: physical address extensions = true
  2888. MCE: machine check exception = true
  2889. CMPXCHG8B inst. = true
  2890. APIC on chip = true
  2891. SYSENTER and SYSEXIT = true
  2892. MTRR: memory type range registers = true
  2893. PTE global bit = true
  2894. MCA: machine check architecture = true
  2895. CMOV: conditional move/compare instr = true
  2896. PAT: page attribute table = true
  2897. PSE-36: page size extension = true
  2898. PSN: processor serial number = false
  2899. CLFLUSH instruction = true
  2900. DS: debug store = false
  2901. ACPI: thermal monitor and clock ctrl = false
  2902. MMX Technology = true
  2903. FXSAVE/FXRSTOR = true
  2904. SSE extensions = true
  2905. SSE2 extensions = true
  2906. SS: self snoop = true
  2907. hyper-threading / multi-core supported = false
  2908. TM: therm. monitor = false
  2909. IA64 = false
  2910. PBE: pending break event = false
  2911. feature information (1/ecx):
  2912. PNI/SSE3: Prescott New Instructions = true
  2913. PCLMULDQ instruction = true
  2914. DTES64: 64-bit debug store = false
  2915. MONITOR/MWAIT = false
  2916. CPL-qualified debug store = false
  2917. VMX: virtual machine extensions = true
  2918. SMX: safer mode extensions = false
  2919. Enhanced Intel SpeedStep Technology = false
  2920. TM2: thermal monitor 2 = false
  2921. SSSE3 extensions = true
  2922. context ID: adaptive or shared L1 data = false
  2923. SDBG: IA32_DEBUG_INTERFACE = false
  2924. FMA instruction = true
  2925. CMPXCHG16B instruction = true
  2926. xTPR disable = false
  2927. PDCM: perfmon and debug = false
  2928. PCID: process context identifiers = true
  2929. DCA: direct cache access = false
  2930. SSE4.1 extensions = true
  2931. SSE4.2 extensions = true
  2932. x2APIC: extended xAPIC support = true
  2933. MOVBE instruction = true
  2934. POPCNT instruction = true
  2935. time stamp counter deadline = true
  2936. AES instruction = true
  2937. XSAVE/XSTOR states = true
  2938. OS-enabled XSAVE/XSTOR = true
  2939. AVX: advanced vector extensions = true
  2940. F16C half-precision convert instruction = true
  2941. RDRAND instruction = true
  2942. hypervisor guest status = true
  2943. cache and TLB information (2):
  2944. 0x4d: L3 cache: 16M, 16-way, 64 byte lines
  2945. 0x7d: L2 cache: 2M, 8-way, 64 byte lines
  2946. 0x30: L1 cache: 32K, 8-way, 64 byte lines
  2947. 0x2c: L1 data cache: 32K, 8-way, 64 byte lines
  2948. processor serial number = 0005-0657-0000-0000-0000-0000
  2949. deterministic cache parameters (4):
  2950. --- cache 0 ---
  2951. cache type = data cache (1)
  2952. cache level = 0x1 (1)
  2953. self-initializing cache level = true
  2954. fully associative cache = false
  2955. maximum IDs for CPUs sharing cache = 0x0 (0)
  2956. maximum IDs for cores in pkg = 0x0 (0)
  2957. system coherency line size = 0x40 (64)
  2958. physical line partitions = 0x1 (1)
  2959. ways of associativity = 0x8 (8)
  2960. number of sets = 0x40 (64)
  2961. WBINVD/INVD acts on lower caches = true
  2962. inclusive to lower caches = false
  2963. complex cache indexing = false
  2964. number of sets (s) = 64
  2965. (size synth) = 32768 (32 KB)
  2966. --- cache 1 ---
  2967. cache type = instruction cache (2)
  2968. cache level = 0x1 (1)
  2969. self-initializing cache level = true
  2970. fully associative cache = false
  2971. maximum IDs for CPUs sharing cache = 0x0 (0)
  2972. maximum IDs for cores in pkg = 0x0 (0)
  2973. system coherency line size = 0x40 (64)
  2974. physical line partitions = 0x1 (1)
  2975. ways of associativity = 0x8 (8)
  2976. number of sets = 0x40 (64)
  2977. WBINVD/INVD acts on lower caches = true
  2978. inclusive to lower caches = false
  2979. complex cache indexing = false
  2980. number of sets (s) = 64
  2981. (size synth) = 32768 (32 KB)
  2982. --- cache 2 ---
  2983. cache type = unified cache (3)
  2984. cache level = 0x2 (2)
  2985. self-initializing cache level = true
  2986. fully associative cache = false
  2987. maximum IDs for CPUs sharing cache = 0x0 (0)
  2988. maximum IDs for cores in pkg = 0x0 (0)
  2989. system coherency line size = 0x40 (64)
  2990. physical line partitions = 0x1 (1)
  2991. ways of associativity = 0x10 (16)
  2992. number of sets = 0x1000 (4096)
  2993. WBINVD/INVD acts on lower caches = true
  2994. inclusive to lower caches = false
  2995. complex cache indexing = false
  2996. number of sets (s) = 4096
  2997. (size synth) = 4194304 (4 MB)
  2998. --- cache 3 ---
  2999. cache type = unified cache (3)
  3000. cache level = 0x3 (3)
  3001. self-initializing cache level = true
  3002. fully associative cache = false
  3003. maximum IDs for CPUs sharing cache = 0x0 (0)
  3004. maximum IDs for cores in pkg = 0x0 (0)
  3005. system coherency line size = 0x40 (64)
  3006. physical line partitions = 0x1 (1)
  3007. ways of associativity = 0x10 (16)
  3008. number of sets = 0x4000 (16384)
  3009. WBINVD/INVD acts on lower caches = false
  3010. inclusive to lower caches = true
  3011. complex cache indexing = true
  3012. number of sets (s) = 16384
  3013. (size synth) = 16777216 (16 MB)
  3014. MONITOR/MWAIT (5):
  3015. smallest monitor-line size (bytes) = 0x0 (0)
  3016. largest monitor-line size (bytes) = 0x0 (0)
  3017. enum of Monitor-MWAIT exts supported = true
  3018. supports intrs as break-event for MWAIT = true
  3019. number of C0 sub C-states using MWAIT = 0x0 (0)
  3020. number of C1 sub C-states using MWAIT = 0x0 (0)
  3021. number of C2 sub C-states using MWAIT = 0x0 (0)
  3022. number of C3 sub C-states using MWAIT = 0x0 (0)
  3023. number of C4 sub C-states using MWAIT = 0x0 (0)
  3024. number of C5 sub C-states using MWAIT = 0x0 (0)
  3025. number of C6 sub C-states using MWAIT = 0x0 (0)
  3026. number of C7 sub C-states using MWAIT = 0x0 (0)
  3027. Thermal and Power Management Features (6):
  3028. digital thermometer = false
  3029. Intel Turbo Boost Technology = false
  3030. ARAT always running APIC timer = true
  3031. PLN power limit notification = false
  3032. ECMD extended clock modulation duty = false
  3033. PTM package thermal management = false
  3034. HWP base registers = false
  3035. HWP notification = false
  3036. HWP activity window = false
  3037. HWP energy performance preference = false
  3038. HWP package level request = false
  3039. HDC base registers = false
  3040. Intel Turbo Boost Max Technology 3.0 = false
  3041. HWP capabilities = false
  3042. HWP PECI override = false
  3043. flexible HWP = false
  3044. IA32_HWP_REQUEST MSR fast access mode = false
  3045. HW_FEEDBACK MSRs supported = false
  3046. ignoring idle logical processor HWP req = false
  3047. enhanced hardware feedback interface = false
  3048. digital thermometer thresholds = 0x0 (0)
  3049. hardware coordination feedback = false
  3050. ACNT2 available = false
  3051. performance-energy bias capability = false
  3052. number of enh hardware feedback classes = 0x0 (0)
  3053. performance capability reporting = false
  3054. energy efficiency capability reporting = false
  3055. size of feedback struct (4KB pages) = 0x1 (1)
  3056. index of CPU's row in feedback struct = 0x0 (0)
  3057. extended feature flags (7):
  3058. FSGSBASE instructions = true
  3059. IA32_TSC_ADJUST MSR supported = true
  3060. SGX: Software Guard Extensions supported = false
  3061. BMI1 instructions = true
  3062. HLE hardware lock elision = false
  3063. AVX2: advanced vector extensions 2 = true
  3064. FDP_EXCPTN_ONLY = false
  3065. SMEP supervisor mode exec protection = true
  3066. BMI2 instructions = true
  3067. enhanced REP MOVSB/STOSB = true
  3068. INVPCID instruction = true
  3069. RTM: restricted transactional memory = false
  3070. RDT-CMT/PQoS cache monitoring = false
  3071. deprecated FPU CS/DS = false
  3072. MPX: intel memory protection extensions = true
  3073. RDT-CAT/PQE cache allocation = false
  3074. AVX512F: AVX-512 foundation instructions = true
  3075. AVX512DQ: double & quadword instructions = true
  3076. RDSEED instruction = true
  3077. ADX instructions = true
  3078. SMAP: supervisor mode access prevention = true
  3079. AVX512IFMA: fused multiply add = false
  3080. PCOMMIT instruction = false
  3081. CLFLUSHOPT instruction = true
  3082. CLWB instruction = true
  3083. Intel processor trace = false
  3084. AVX512PF: prefetch instructions = false
  3085. AVX512ER: exponent & reciprocal instrs = false
  3086. AVX512CD: conflict detection instrs = true
  3087. SHA instructions = false
  3088. AVX512BW: byte & word instructions = true
  3089. AVX512VL: vector length = true
  3090. PREFETCHWT1 = false
  3091. AVX512VBMI: vector byte manipulation = false
  3092. UMIP: user-mode instruction prevention = true
  3093. PKU protection keys for user-mode = true
  3094. OSPKE CR4.PKE and RDPKRU/WRPKRU = true
  3095. WAITPKG instructions = false
  3096. AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
  3097. CET_SS: CET shadow stack = false
  3098. GFNI: Galois Field New Instructions = false
  3099. VAES instructions = false
  3100. VPCLMULQDQ instruction = false
  3101. AVX512_VNNI: neural network instructions = true
  3102. AVX512_BITALG: bit count/shiffle = false
  3103. TME: Total Memory Encryption = false
  3104. AVX512: VPOPCNTDQ instruction = false
  3105. 5-level paging = false
  3106. BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
  3107. RDPID: read processor D supported = false
  3108. KL: key locker = false
  3109. CLDEMOTE supports cache line demote = false
  3110. MOVDIRI instruction = false
  3111. MOVDIR64B instruction = false
  3112. ENQCMD instruction = false
  3113. SGX_LC: SGX launch config supported = false
  3114. PKS: supervisor protection keys = false
  3115. AVX512_4VNNIW: neural network instrs = false
  3116. AVX512_4FMAPS: multiply acc single prec = false
  3117. fast short REP MOV = false
  3118. UINTR: user interrupts = false
  3119. AVX512_VP2INTERSECT: intersect mask regs = false
  3120. SRBDS mitigation MSR available = false
  3121. VERW MD_CLEAR microcode support = true
  3122. SERIALIZE instruction = false
  3123. hybrid part = false
  3124. TSXLDTRK: TSX suspend load addr tracking = false
  3125. PCONFIG instruction = false
  3126. LBR: architectural last branch records = false
  3127. CET_IBT: CET indirect branch tracking = false
  3128. AMX-BF16: tile bfloat16 support = false
  3129. AVX512_FP16: fp16 support = false
  3130. AMX-TILE: tile architecture support = false
  3131. AMX-INT8: tile 8-bit integer support = false
  3132. IBRS/IBPB: indirect branch restrictions = true
  3133. STIBP: 1 thr indirect branch predictor = true
  3134. L1D_FLUSH: IA32_FLUSH_CMD MSR = false
  3135. IA32_ARCH_CAPABILITIES MSR = true
  3136. IA32_CORE_CAPABILITIES MSR = false
  3137. SSBD: speculative store bypass disable = true
  3138. Direct Cache Access Parameters (9):
  3139. PLATFORM_DCA_CAP MSR bits = 0
  3140. Architecture Performance Monitoring Features (0xa):
  3141. version ID = 0x2 (2)
  3142. number of counters per logical processor = 0x4 (4)
  3143. bit width of counter = 0x30 (48)
  3144. length of EBX bit vector = 0x7 (7)
  3145. core cycle event not available = false
  3146. instruction retired event not available = false
  3147. reference cycles event not available = false
  3148. last-level cache ref event not available = false
  3149. last-level cache miss event not avail = false
  3150. branch inst retired event not available = false
  3151. branch mispred retired event not avail = false
  3152. fixed counter 0 supported = false
  3153. fixed counter 1 supported = false
  3154. fixed counter 2 supported = false
  3155. fixed counter 3 supported = false
  3156. fixed counter 4 supported = false
  3157. fixed counter 5 supported = false
  3158. fixed counter 6 supported = false
  3159. fixed counter 7 supported = false
  3160. fixed counter 8 supported = false
  3161. fixed counter 9 supported = false
  3162. fixed counter 10 supported = false
  3163. fixed counter 11 supported = false
  3164. fixed counter 12 supported = false
  3165. fixed counter 13 supported = false
  3166. fixed counter 14 supported = false
  3167. fixed counter 15 supported = false
  3168. fixed counter 16 supported = false
  3169. fixed counter 17 supported = false
  3170. fixed counter 18 supported = false
  3171. fixed counter 19 supported = false
  3172. fixed counter 20 supported = false
  3173. fixed counter 21 supported = false
  3174. fixed counter 22 supported = false
  3175. fixed counter 23 supported = false
  3176. fixed counter 24 supported = false
  3177. fixed counter 25 supported = false
  3178. fixed counter 26 supported = false
  3179. fixed counter 27 supported = false
  3180. fixed counter 28 supported = false
  3181. fixed counter 29 supported = false
  3182. fixed counter 30 supported = false
  3183. fixed counter 31 supported = false
  3184. number of fixed counters = 0x3 (3)
  3185. bit width of fixed counters = 0x30 (48)
  3186. anythread deprecation = false
  3187. x2APIC features / processor topology (0xb):
  3188. extended APIC ID = 5
  3189. --- level 0 ---
  3190. level number = 0x0 (0)
  3191. level type = thread (1)
  3192. bit width of level = 0x0 (0)
  3193. number of logical processors at level = 0x1 (1)
  3194. --- level 1 ---
  3195. level number = 0x1 (1)
  3196. level type = core (2)
  3197. bit width of level = 0x0 (0)
  3198. number of logical processors at level = 0x1 (1)
  3199. XSAVE features (0xd/0):
  3200. XCR0 lower 32 bits valid bit field mask = 0x000002ff
  3201. XCR0 upper 32 bits valid bit field mask = 0x00000000
  3202. XCR0 supported: x87 state = true
  3203. XCR0 supported: SSE state = true
  3204. XCR0 supported: AVX state = true
  3205. XCR0 supported: MPX BNDREGS = true
  3206. XCR0 supported: MPX BNDCSR = true
  3207. XCR0 supported: AVX-512 opmask = true
  3208. XCR0 supported: AVX-512 ZMM_Hi256 = true
  3209. XCR0 supported: AVX-512 Hi16_ZMM = true
  3210. IA32_XSS supported: PT state = false
  3211. XCR0 supported: PKRU state = true
  3212. XCR0 supported: CET_U state = false
  3213. XCR0 supported: CET_S state = false
  3214. IA32_XSS supported: HDC state = false
  3215. IA32_XSS supported: UINTR state = false
  3216. LBR supported = false
  3217. IA32_XSS supported: HWP state = false
  3218. XTILECFG supported = false
  3219. XTILEDATA supported = false
  3220. bytes required by fields in XCR0 = 0x00000a88 (2696)
  3221. bytes required by XSAVE/XRSTOR area = 0x00000a88 (2696)
  3222. XSAVE features (0xd/1):
  3223. XSAVEOPT instruction = true
  3224. XSAVEC instruction = true
  3225. XGETBV instruction = true
  3226. XSAVES/XRSTORS instructions = true
  3227. XFD: extended feature disable supported = false
  3228. SAVE area size in bytes = 0x00000a08 (2568)
  3229. IA32_XSS lower 32 bits valid bit field mask = 0x00000000
  3230. IA32_XSS upper 32 bits valid bit field mask = 0x00000000
  3231. AVX/YMM features (0xd/2):
  3232. AVX/YMM save state byte size = 0x00000100 (256)
  3233. AVX/YMM save state byte offset = 0x00000240 (576)
  3234. supported in IA32_XSS or XCR0 = XCR0 (user state)
  3235. 64-byte alignment in compacted XSAVE = false
  3236. XFD faulting supported = false
  3237. MPX BNDREGS features (0xd/3):
  3238. MPX BNDREGS save state byte size = 0x00000040 (64)
  3239. MPX BNDREGS save state byte offset = 0x000003c0 (960)
  3240. supported in IA32_XSS or XCR0 = XCR0 (user state)
  3241. 64-byte alignment in compacted XSAVE = false
  3242. XFD faulting supported = false
  3243. MPX BNDCSR features (0xd/4):
  3244. MPX BNDCSR save state byte size = 0x00000040 (64)
  3245. MPX BNDCSR save state byte offset = 0x00000400 (1024)
  3246. supported in IA32_XSS or XCR0 = XCR0 (user state)
  3247. 64-byte alignment in compacted XSAVE = false
  3248. XFD faulting supported = false
  3249. AVX-512 opmask features (0xd/5):
  3250. AVX-512 opmask save state byte size = 0x00000040 (64)
  3251. AVX-512 opmask save state byte offset = 0x00000440 (1088)
  3252. supported in IA32_XSS or XCR0 = XCR0 (user state)
  3253. 64-byte alignment in compacted XSAVE = false
  3254. XFD faulting supported = false
  3255. AVX-512 ZMM_Hi256 features (0xd/6):
  3256. AVX-512 ZMM_Hi256 save state byte size = 0x00000200 (512)
  3257. AVX-512 ZMM_Hi256 save state byte offset = 0x00000480 (1152)
  3258. supported in IA32_XSS or XCR0 = XCR0 (user state)
  3259. 64-byte alignment in compacted XSAVE = false
  3260. XFD faulting supported = false
  3261. AVX-512 Hi16_ZMM features (0xd/7):
  3262. AVX-512 Hi16_ZMM save state byte size = 0x00000400 (1024)
  3263. AVX-512 Hi16_ZMM save state byte offset = 0x00000680 (1664)
  3264. supported in IA32_XSS or XCR0 = XCR0 (user state)
  3265. 64-byte alignment in compacted XSAVE = false
  3266. XFD faulting supported = false
  3267. PKRU features (0xd/9):
  3268. PKRU save state byte size = 0x00000008 (8)
  3269. PKRU save state byte offset = 0x00000a80 (2688)
  3270. supported in IA32_XSS or XCR0 = XCR0 (user state)
  3271. 64-byte alignment in compacted XSAVE = false
  3272. XFD faulting supported = false
  3273. Quality of Service Monitoring Resource Type (0xf/0):
  3274. Maximum range of RMID = 0
  3275. supports L3 cache QoS monitoring = false
  3276. Resource Director Technology Allocation (0x10/0):
  3277. L3 cache allocation technology supported = false
  3278. L2 cache allocation technology supported = false
  3279. memory bandwidth allocation supported = false
  3280. 0x00000011 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
  3281. Software Guard Extensions (SGX) capability (0x12/0):
  3282. SGX1 supported = false
  3283. SGX2 supported = false
  3284. SGX ENCLV E*VIRTCHILD, ESETCONTEXT = false
  3285. SGX ENCLS ETRACKC, ERDINFO, ELDBC, ELDUC = false
  3286. MISCSELECT.EXINFO supported: #PF & #GP = false
  3287. MISCSELECT.CPINFO supported: #CP = false
  3288. MaxEnclaveSize_Not64 (log2) = 0x0 (0)
  3289. MaxEnclaveSize_64 (log2) = 0x0 (0)
  3290. 0x00000013 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
  3291. Intel Processor Trace (0x14):
  3292. IA32_RTIT_CR3_MATCH is accessible = false
  3293. configurable PSB & cycle-accurate = false
  3294. IP & TraceStop filtering; PT preserve = false
  3295. MTC timing packet; suppress COFI-based = false
  3296. PTWRITE support = false
  3297. power event trace support = false
  3298. ToPA output scheme support = false
  3299. ToPA can hold many output entries = false
  3300. single-range output scheme support = false
  3301. output to trace transport = false
  3302. IP payloads have LIP values & CS = false
  3303. Time Stamp Counter/Core Crystal Clock Information (0x15):
  3304. TSC/clock ratio = 0/0
  3305. nominal core crystal clock = 0 Hz
  3306. Processor Frequency Information (0x16):
  3307. Core Base Frequency (MHz) = 0x0 (0)
  3308. Core Maximum Frequency (MHz) = 0x0 (0)
  3309. Bus (Reference) Frequency (MHz) = 0x0 (0)
  3310. hypervisor_id = "KVMKVMKVM "
  3311. hypervisor features (0x40000001/eax):
  3312. kvmclock available at MSR 0x11 = true
  3313. delays unnecessary for PIO ops = true
  3314. mmu_op = false
  3315. kvmclock available at MSR 0x4b564d00 = true
  3316. async pf enable available by MSR = true
  3317. steal clock supported = true
  3318. guest EOI optimization enabled = true
  3319. guest spinlock optimization enabled = true
  3320. guest TLB flush optimization enabled = true
  3321. async PF VM exit enable available by MSR = false
  3322. guest send IPI optimization enabled = true
  3323. host HLT poll disable at MSR 0x4b564d05 = true
  3324. guest sched yield optimization enabled = true
  3325. guest uses intrs for page ready APF evs = false
  3326. stable: no guest per-cpu warps expected = true
  3327. hypervisor features (0x40000001/edx):
  3328. realtime hint: no unbound preemption = true
  3329. extended feature flags (0x80000001/edx):
  3330. SYSCALL and SYSRET instructions = true
  3331. execution disable = true
  3332. 1-GB large page support = true
  3333. RDTSCP = true
  3334. 64-bit extensions technology available = true
  3335. Intel feature flags (0x80000001/ecx):
  3336. LAHF/SAHF supported in 64-bit mode = true
  3337. LZCNT advanced bit manipulation = true
  3338. 3DNow! PREFETCH/PREFETCHW instructions = true
  3339. brand = "Intel(R) Xeon(R) Platinum 8275CL CPU @ 3.00GHz"
  3340. L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
  3341. instruction # entries = 0xff (255)
  3342. instruction associativity = 0x1 (1)
  3343. data # entries = 0xff (255)
  3344. data associativity = 0x1 (1)
  3345. L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
  3346. instruction # entries = 0xff (255)
  3347. instruction associativity = 0x1 (1)
  3348. data # entries = 0xff (255)
  3349. data associativity = 0x1 (1)
  3350. L1 data cache information (0x80000005/ecx):
  3351. line size (bytes) = 0x40 (64)
  3352. lines per tag = 0x1 (1)
  3353. associativity = 0x2 (2)
  3354. size (KB) = 0x40 (64)
  3355. L1 instruction cache information (0x80000005/edx):
  3356. line size (bytes) = 0x40 (64)
  3357. lines per tag = 0x1 (1)
  3358. associativity = 0x2 (2)
  3359. size (KB) = 0x40 (64)
  3360. L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
  3361. instruction # entries = 0x0 (0)
  3362. instruction associativity = L2 off (0)
  3363. data # entries = 0x0 (0)
  3364. data associativity = L2 off (0)
  3365. L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
  3366. instruction # entries = 0x200 (512)
  3367. instruction associativity = 4-way (4)
  3368. data # entries = 0x200 (512)
  3369. data associativity = 4-way (4)
  3370. L2 unified cache information (0x80000006/ecx):
  3371. line size (bytes) = 0x40 (64)
  3372. lines per tag = 0x1 (1)
  3373. associativity = 16-way (8)
  3374. size (KB) = 0x200 (512)
  3375. L3 cache information (0x80000006/edx):
  3376. line size (bytes) = 0x40 (64)
  3377. lines per tag = 0x1 (1)
  3378. associativity = 16-way (8)
  3379. size (in 512KB units) = 0x20 (32)
  3380. RAS Capability (0x80000007/ebx):
  3381. MCA overflow recovery support = false
  3382. SUCCOR support = false
  3383. HWA: hardware assert support = false
  3384. scalable MCA support = false
  3385. Advanced Power Management Features (0x80000007/ecx):
  3386. CmpUnitPwrSampleTimeRatio = 0x0 (0)
  3387. Advanced Power Management Features (0x80000007/edx):
  3388. TS: temperature sensing diode = false
  3389. FID: frequency ID control = false
  3390. VID: voltage ID control = false
  3391. TTP: thermal trip = false
  3392. TM: thermal monitor = false
  3393. STC: software thermal control = false
  3394. 100 MHz multiplier control = false
  3395. hardware P-State control = false
  3396. TscInvariant = false
  3397. CPB: core performance boost = false
  3398. read-only effective frequency interface = false
  3399. processor feedback interface = false
  3400. APM power reporting = false
  3401. connected standby = false
  3402. RAPL: running average power limit = false
  3403. Physical Address and Linear Address Size (0x80000008/eax):
  3404. maximum physical address bits = 0x2e (46)
  3405. maximum linear (virtual) address bits = 0x30 (48)
  3406. maximum guest physical address bits = 0x0 (0)
  3407. Extended Feature Extensions ID (0x80000008/ebx):
  3408. CLZERO instruction = false
  3409. instructions retired count support = false
  3410. always save/restore error pointers = false
  3411. RDPRU instruction = false
  3412. memory bandwidth enforcement = false
  3413. WBNOINVD instruction = false
  3414. IBPB: indirect branch prediction barrier = true
  3415. IBRS: indirect branch restr speculation = true
  3416. STIBP: 1 thr indirect branch predictor = true
  3417. STIBP always on preferred mode = false
  3418. ppin processor id number supported = false
  3419. SSBD: speculative store bypass disable = true
  3420. virtualized SSBD = false
  3421. SSBD fixed in hardware = false
  3422. Size Identifiers (0x80000008/ecx):
  3423. number of CPU cores = 0x1 (1)
  3424. ApicIdCoreIdSize = 0x0 (0)
  3425. performance time-stamp counter size = 0x0 (0)
  3426. Feature Extended Size (0x80000008/edx):
  3427. RDPRU instruction max input support = 0x0 (0)
  3428. (multi-processing synth) = none
  3429. (multi-processing method) = Intel leaf 0xb
  3430. (APIC widths synth): CORE_width=0 SMT_width=0
  3431. (APIC synth): PKG_ID=5 CORE_ID=0 SMT_ID=0
  3432. (uarch synth) = Intel Cascade Lake {Skylake}, 14nm
  3433. (synth) = Intel Scalable (2nd Gen) Bronze/Silver/Gold/Platinum (Cascade Lake B1/L1/R1) {Skylake}, 14nm
  3434. CPU 6:
  3435. vendor_id = "GenuineIntel"
  3436. version information (1/eax):
  3437. processor type = primary processor (0)
  3438. family = 0x6 (6)
  3439. model = 0x5 (5)
  3440. stepping id = 0x7 (7)
  3441. extended family = 0x0 (0)
  3442. extended model = 0x5 (5)
  3443. (family synth) = 0x6 (6)
  3444. (model synth) = 0x55 (85)
  3445. (simple synth) = Intel Core (unknown type) (Skylake / Skylake-X / Cascade Lake / Cascade Lake-X) {Skylake}, 14nm
  3446. miscellaneous (1/ebx):
  3447. process local APIC physical ID = 0x6 (6)
  3448. maximum IDs for CPUs in pkg = 0x0 (0)
  3449. CLFLUSH line size = 0x8 (8)
  3450. brand index = 0x0 (0)
  3451. brand id = 0x00 (0): unknown
  3452. feature information (1/edx):
  3453. x87 FPU on chip = true
  3454. VME: virtual-8086 mode enhancement = true
  3455. DE: debugging extensions = true
  3456. PSE: page size extensions = true
  3457. TSC: time stamp counter = true
  3458. RDMSR and WRMSR support = true
  3459. PAE: physical address extensions = true
  3460. MCE: machine check exception = true
  3461. CMPXCHG8B inst. = true
  3462. APIC on chip = true
  3463. SYSENTER and SYSEXIT = true
  3464. MTRR: memory type range registers = true
  3465. PTE global bit = true
  3466. MCA: machine check architecture = true
  3467. CMOV: conditional move/compare instr = true
  3468. PAT: page attribute table = true
  3469. PSE-36: page size extension = true
  3470. PSN: processor serial number = false
  3471. CLFLUSH instruction = true
  3472. DS: debug store = false
  3473. ACPI: thermal monitor and clock ctrl = false
  3474. MMX Technology = true
  3475. FXSAVE/FXRSTOR = true
  3476. SSE extensions = true
  3477. SSE2 extensions = true
  3478. SS: self snoop = true
  3479. hyper-threading / multi-core supported = false
  3480. TM: therm. monitor = false
  3481. IA64 = false
  3482. PBE: pending break event = false
  3483. feature information (1/ecx):
  3484. PNI/SSE3: Prescott New Instructions = true
  3485. PCLMULDQ instruction = true
  3486. DTES64: 64-bit debug store = false
  3487. MONITOR/MWAIT = false
  3488. CPL-qualified debug store = false
  3489. VMX: virtual machine extensions = true
  3490. SMX: safer mode extensions = false
  3491. Enhanced Intel SpeedStep Technology = false
  3492. TM2: thermal monitor 2 = false
  3493. SSSE3 extensions = true
  3494. context ID: adaptive or shared L1 data = false
  3495. SDBG: IA32_DEBUG_INTERFACE = false
  3496. FMA instruction = true
  3497. CMPXCHG16B instruction = true
  3498. xTPR disable = false
  3499. PDCM: perfmon and debug = false
  3500. PCID: process context identifiers = true
  3501. DCA: direct cache access = false
  3502. SSE4.1 extensions = true
  3503. SSE4.2 extensions = true
  3504. x2APIC: extended xAPIC support = true
  3505. MOVBE instruction = true
  3506. POPCNT instruction = true
  3507. time stamp counter deadline = true
  3508. AES instruction = true
  3509. XSAVE/XSTOR states = true
  3510. OS-enabled XSAVE/XSTOR = true
  3511. AVX: advanced vector extensions = true
  3512. F16C half-precision convert instruction = true
  3513. RDRAND instruction = true
  3514. hypervisor guest status = true
  3515. cache and TLB information (2):
  3516. 0x4d: L3 cache: 16M, 16-way, 64 byte lines
  3517. 0x7d: L2 cache: 2M, 8-way, 64 byte lines
  3518. 0x30: L1 cache: 32K, 8-way, 64 byte lines
  3519. 0x2c: L1 data cache: 32K, 8-way, 64 byte lines
  3520. processor serial number = 0005-0657-0000-0000-0000-0000
  3521. deterministic cache parameters (4):
  3522. --- cache 0 ---
  3523. cache type = data cache (1)
  3524. cache level = 0x1 (1)
  3525. self-initializing cache level = true
  3526. fully associative cache = false
  3527. maximum IDs for CPUs sharing cache = 0x0 (0)
  3528. maximum IDs for cores in pkg = 0x0 (0)
  3529. system coherency line size = 0x40 (64)
  3530. physical line partitions = 0x1 (1)
  3531. ways of associativity = 0x8 (8)
  3532. number of sets = 0x40 (64)
  3533. WBINVD/INVD acts on lower caches = true
  3534. inclusive to lower caches = false
  3535. complex cache indexing = false
  3536. number of sets (s) = 64
  3537. (size synth) = 32768 (32 KB)
  3538. --- cache 1 ---
  3539. cache type = instruction cache (2)
  3540. cache level = 0x1 (1)
  3541. self-initializing cache level = true
  3542. fully associative cache = false
  3543. maximum IDs for CPUs sharing cache = 0x0 (0)
  3544. maximum IDs for cores in pkg = 0x0 (0)
  3545. system coherency line size = 0x40 (64)
  3546. physical line partitions = 0x1 (1)
  3547. ways of associativity = 0x8 (8)
  3548. number of sets = 0x40 (64)
  3549. WBINVD/INVD acts on lower caches = true
  3550. inclusive to lower caches = false
  3551. complex cache indexing = false
  3552. number of sets (s) = 64
  3553. (size synth) = 32768 (32 KB)
  3554. --- cache 2 ---
  3555. cache type = unified cache (3)
  3556. cache level = 0x2 (2)
  3557. self-initializing cache level = true
  3558. fully associative cache = false
  3559. maximum IDs for CPUs sharing cache = 0x0 (0)
  3560. maximum IDs for cores in pkg = 0x0 (0)
  3561. system coherency line size = 0x40 (64)
  3562. physical line partitions = 0x1 (1)
  3563. ways of associativity = 0x10 (16)
  3564. number of sets = 0x1000 (4096)
  3565. WBINVD/INVD acts on lower caches = true
  3566. inclusive to lower caches = false
  3567. complex cache indexing = false
  3568. number of sets (s) = 4096
  3569. (size synth) = 4194304 (4 MB)
  3570. --- cache 3 ---
  3571. cache type = unified cache (3)
  3572. cache level = 0x3 (3)
  3573. self-initializing cache level = true
  3574. fully associative cache = false
  3575. maximum IDs for CPUs sharing cache = 0x0 (0)
  3576. maximum IDs for cores in pkg = 0x0 (0)
  3577. system coherency line size = 0x40 (64)
  3578. physical line partitions = 0x1 (1)
  3579. ways of associativity = 0x10 (16)
  3580. number of sets = 0x4000 (16384)
  3581. WBINVD/INVD acts on lower caches = false
  3582. inclusive to lower caches = true
  3583. complex cache indexing = true
  3584. number of sets (s) = 16384
  3585. (size synth) = 16777216 (16 MB)
  3586. MONITOR/MWAIT (5):
  3587. smallest monitor-line size (bytes) = 0x0 (0)
  3588. largest monitor-line size (bytes) = 0x0 (0)
  3589. enum of Monitor-MWAIT exts supported = true
  3590. supports intrs as break-event for MWAIT = true
  3591. number of C0 sub C-states using MWAIT = 0x0 (0)
  3592. number of C1 sub C-states using MWAIT = 0x0 (0)
  3593. number of C2 sub C-states using MWAIT = 0x0 (0)
  3594. number of C3 sub C-states using MWAIT = 0x0 (0)
  3595. number of C4 sub C-states using MWAIT = 0x0 (0)
  3596. number of C5 sub C-states using MWAIT = 0x0 (0)
  3597. number of C6 sub C-states using MWAIT = 0x0 (0)
  3598. number of C7 sub C-states using MWAIT = 0x0 (0)
  3599. Thermal and Power Management Features (6):
  3600. digital thermometer = false
  3601. Intel Turbo Boost Technology = false
  3602. ARAT always running APIC timer = true
  3603. PLN power limit notification = false
  3604. ECMD extended clock modulation duty = false
  3605. PTM package thermal management = false
  3606. HWP base registers = false
  3607. HWP notification = false
  3608. HWP activity window = false
  3609. HWP energy performance preference = false
  3610. HWP package level request = false
  3611. HDC base registers = false
  3612. Intel Turbo Boost Max Technology 3.0 = false
  3613. HWP capabilities = false
  3614. HWP PECI override = false
  3615. flexible HWP = false
  3616. IA32_HWP_REQUEST MSR fast access mode = false
  3617. HW_FEEDBACK MSRs supported = false
  3618. ignoring idle logical processor HWP req = false
  3619. enhanced hardware feedback interface = false
  3620. digital thermometer thresholds = 0x0 (0)
  3621. hardware coordination feedback = false
  3622. ACNT2 available = false
  3623. performance-energy bias capability = false
  3624. number of enh hardware feedback classes = 0x0 (0)
  3625. performance capability reporting = false
  3626. energy efficiency capability reporting = false
  3627. size of feedback struct (4KB pages) = 0x1 (1)
  3628. index of CPU's row in feedback struct = 0x0 (0)
  3629. extended feature flags (7):
  3630. FSGSBASE instructions = true
  3631. IA32_TSC_ADJUST MSR supported = true
  3632. SGX: Software Guard Extensions supported = false
  3633. BMI1 instructions = true
  3634. HLE hardware lock elision = false
  3635. AVX2: advanced vector extensions 2 = true
  3636. FDP_EXCPTN_ONLY = false
  3637. SMEP supervisor mode exec protection = true
  3638. BMI2 instructions = true
  3639. enhanced REP MOVSB/STOSB = true
  3640. INVPCID instruction = true
  3641. RTM: restricted transactional memory = false
  3642. RDT-CMT/PQoS cache monitoring = false
  3643. deprecated FPU CS/DS = false
  3644. MPX: intel memory protection extensions = true
  3645. RDT-CAT/PQE cache allocation = false
  3646. AVX512F: AVX-512 foundation instructions = true
  3647. AVX512DQ: double & quadword instructions = true
  3648. RDSEED instruction = true
  3649. ADX instructions = true
  3650. SMAP: supervisor mode access prevention = true
  3651. AVX512IFMA: fused multiply add = false
  3652. PCOMMIT instruction = false
  3653. CLFLUSHOPT instruction = true
  3654. CLWB instruction = true
  3655. Intel processor trace = false
  3656. AVX512PF: prefetch instructions = false
  3657. AVX512ER: exponent & reciprocal instrs = false
  3658. AVX512CD: conflict detection instrs = true
  3659. SHA instructions = false
  3660. AVX512BW: byte & word instructions = true
  3661. AVX512VL: vector length = true
  3662. PREFETCHWT1 = false
  3663. AVX512VBMI: vector byte manipulation = false
  3664. UMIP: user-mode instruction prevention = true
  3665. PKU protection keys for user-mode = true
  3666. OSPKE CR4.PKE and RDPKRU/WRPKRU = true
  3667. WAITPKG instructions = false
  3668. AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
  3669. CET_SS: CET shadow stack = false
  3670. GFNI: Galois Field New Instructions = false
  3671. VAES instructions = false
  3672. VPCLMULQDQ instruction = false
  3673. AVX512_VNNI: neural network instructions = true
  3674. AVX512_BITALG: bit count/shiffle = false
  3675. TME: Total Memory Encryption = false
  3676. AVX512: VPOPCNTDQ instruction = false
  3677. 5-level paging = false
  3678. BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
  3679. RDPID: read processor D supported = false
  3680. KL: key locker = false
  3681. CLDEMOTE supports cache line demote = false
  3682. MOVDIRI instruction = false
  3683. MOVDIR64B instruction = false
  3684. ENQCMD instruction = false
  3685. SGX_LC: SGX launch config supported = false
  3686. PKS: supervisor protection keys = false
  3687. AVX512_4VNNIW: neural network instrs = false
  3688. AVX512_4FMAPS: multiply acc single prec = false
  3689. fast short REP MOV = false
  3690. UINTR: user interrupts = false
  3691. AVX512_VP2INTERSECT: intersect mask regs = false
  3692. SRBDS mitigation MSR available = false
  3693. VERW MD_CLEAR microcode support = true
  3694. SERIALIZE instruction = false
  3695. hybrid part = false
  3696. TSXLDTRK: TSX suspend load addr tracking = false
  3697. PCONFIG instruction = false
  3698. LBR: architectural last branch records = false
  3699. CET_IBT: CET indirect branch tracking = false
  3700. AMX-BF16: tile bfloat16 support = false
  3701. AVX512_FP16: fp16 support = false
  3702. AMX-TILE: tile architecture support = false
  3703. AMX-INT8: tile 8-bit integer support = false
  3704. IBRS/IBPB: indirect branch restrictions = true
  3705. STIBP: 1 thr indirect branch predictor = true
  3706. L1D_FLUSH: IA32_FLUSH_CMD MSR = false
  3707. IA32_ARCH_CAPABILITIES MSR = true
  3708. IA32_CORE_CAPABILITIES MSR = false
  3709. SSBD: speculative store bypass disable = true
  3710. Direct Cache Access Parameters (9):
  3711. PLATFORM_DCA_CAP MSR bits = 0
  3712. Architecture Performance Monitoring Features (0xa):
  3713. version ID = 0x2 (2)
  3714. number of counters per logical processor = 0x4 (4)
  3715. bit width of counter = 0x30 (48)
  3716. length of EBX bit vector = 0x7 (7)
  3717. core cycle event not available = false
  3718. instruction retired event not available = false
  3719. reference cycles event not available = false
  3720. last-level cache ref event not available = false
  3721. last-level cache miss event not avail = false
  3722. branch inst retired event not available = false
  3723. branch mispred retired event not avail = false
  3724. fixed counter 0 supported = false
  3725. fixed counter 1 supported = false
  3726. fixed counter 2 supported = false
  3727. fixed counter 3 supported = false
  3728. fixed counter 4 supported = false
  3729. fixed counter 5 supported = false
  3730. fixed counter 6 supported = false
  3731. fixed counter 7 supported = false
  3732. fixed counter 8 supported = false
  3733. fixed counter 9 supported = false
  3734. fixed counter 10 supported = false
  3735. fixed counter 11 supported = false
  3736. fixed counter 12 supported = false
  3737. fixed counter 13 supported = false
  3738. fixed counter 14 supported = false
  3739. fixed counter 15 supported = false
  3740. fixed counter 16 supported = false
  3741. fixed counter 17 supported = false
  3742. fixed counter 18 supported = false
  3743. fixed counter 19 supported = false
  3744. fixed counter 20 supported = false
  3745. fixed counter 21 supported = false
  3746. fixed counter 22 supported = false
  3747. fixed counter 23 supported = false
  3748. fixed counter 24 supported = false
  3749. fixed counter 25 supported = false
  3750. fixed counter 26 supported = false
  3751. fixed counter 27 supported = false
  3752. fixed counter 28 supported = false
  3753. fixed counter 29 supported = false
  3754. fixed counter 30 supported = false
  3755. fixed counter 31 supported = false
  3756. number of fixed counters = 0x3 (3)
  3757. bit width of fixed counters = 0x30 (48)
  3758. anythread deprecation = false
  3759. x2APIC features / processor topology (0xb):
  3760. extended APIC ID = 6
  3761. --- level 0 ---
  3762. level number = 0x0 (0)
  3763. level type = thread (1)
  3764. bit width of level = 0x0 (0)
  3765. number of logical processors at level = 0x1 (1)
  3766. --- level 1 ---
  3767. level number = 0x1 (1)
  3768. level type = core (2)
  3769. bit width of level = 0x0 (0)
  3770. number of logical processors at level = 0x1 (1)
  3771. XSAVE features (0xd/0):
  3772. XCR0 lower 32 bits valid bit field mask = 0x000002ff
  3773. XCR0 upper 32 bits valid bit field mask = 0x00000000
  3774. XCR0 supported: x87 state = true
  3775. XCR0 supported: SSE state = true
  3776. XCR0 supported: AVX state = true
  3777. XCR0 supported: MPX BNDREGS = true
  3778. XCR0 supported: MPX BNDCSR = true
  3779. XCR0 supported: AVX-512 opmask = true
  3780. XCR0 supported: AVX-512 ZMM_Hi256 = true
  3781. XCR0 supported: AVX-512 Hi16_ZMM = true
  3782. IA32_XSS supported: PT state = false
  3783. XCR0 supported: PKRU state = true
  3784. XCR0 supported: CET_U state = false
  3785. XCR0 supported: CET_S state = false
  3786. IA32_XSS supported: HDC state = false
  3787. IA32_XSS supported: UINTR state = false
  3788. LBR supported = false
  3789. IA32_XSS supported: HWP state = false
  3790. XTILECFG supported = false
  3791. XTILEDATA supported = false
  3792. bytes required by fields in XCR0 = 0x00000a88 (2696)
  3793. bytes required by XSAVE/XRSTOR area = 0x00000a88 (2696)
  3794. XSAVE features (0xd/1):
  3795. XSAVEOPT instruction = true
  3796. XSAVEC instruction = true
  3797. XGETBV instruction = true
  3798. XSAVES/XRSTORS instructions = true
  3799. XFD: extended feature disable supported = false
  3800. SAVE area size in bytes = 0x00000a08 (2568)
  3801. IA32_XSS lower 32 bits valid bit field mask = 0x00000000
  3802. IA32_XSS upper 32 bits valid bit field mask = 0x00000000
  3803. AVX/YMM features (0xd/2):
  3804. AVX/YMM save state byte size = 0x00000100 (256)
  3805. AVX/YMM save state byte offset = 0x00000240 (576)
  3806. supported in IA32_XSS or XCR0 = XCR0 (user state)
  3807. 64-byte alignment in compacted XSAVE = false
  3808. XFD faulting supported = false
  3809. MPX BNDREGS features (0xd/3):
  3810. MPX BNDREGS save state byte size = 0x00000040 (64)
  3811. MPX BNDREGS save state byte offset = 0x000003c0 (960)
  3812. supported in IA32_XSS or XCR0 = XCR0 (user state)
  3813. 64-byte alignment in compacted XSAVE = false
  3814. XFD faulting supported = false
  3815. MPX BNDCSR features (0xd/4):
  3816. MPX BNDCSR save state byte size = 0x00000040 (64)
  3817. MPX BNDCSR save state byte offset = 0x00000400 (1024)
  3818. supported in IA32_XSS or XCR0 = XCR0 (user state)
  3819. 64-byte alignment in compacted XSAVE = false
  3820. XFD faulting supported = false
  3821. AVX-512 opmask features (0xd/5):
  3822. AVX-512 opmask save state byte size = 0x00000040 (64)
  3823. AVX-512 opmask save state byte offset = 0x00000440 (1088)
  3824. supported in IA32_XSS or XCR0 = XCR0 (user state)
  3825. 64-byte alignment in compacted XSAVE = false
  3826. XFD faulting supported = false
  3827. AVX-512 ZMM_Hi256 features (0xd/6):
  3828. AVX-512 ZMM_Hi256 save state byte size = 0x00000200 (512)
  3829. AVX-512 ZMM_Hi256 save state byte offset = 0x00000480 (1152)
  3830. supported in IA32_XSS or XCR0 = XCR0 (user state)
  3831. 64-byte alignment in compacted XSAVE = false
  3832. XFD faulting supported = false
  3833. AVX-512 Hi16_ZMM features (0xd/7):
  3834. AVX-512 Hi16_ZMM save state byte size = 0x00000400 (1024)
  3835. AVX-512 Hi16_ZMM save state byte offset = 0x00000680 (1664)
  3836. supported in IA32_XSS or XCR0 = XCR0 (user state)
  3837. 64-byte alignment in compacted XSAVE = false
  3838. XFD faulting supported = false
  3839. PKRU features (0xd/9):
  3840. PKRU save state byte size = 0x00000008 (8)
  3841. PKRU save state byte offset = 0x00000a80 (2688)
  3842. supported in IA32_XSS or XCR0 = XCR0 (user state)
  3843. 64-byte alignment in compacted XSAVE = false
  3844. XFD faulting supported = false
  3845. Quality of Service Monitoring Resource Type (0xf/0):
  3846. Maximum range of RMID = 0
  3847. supports L3 cache QoS monitoring = false
  3848. Resource Director Technology Allocation (0x10/0):
  3849. L3 cache allocation technology supported = false
  3850. L2 cache allocation technology supported = false
  3851. memory bandwidth allocation supported = false
  3852. 0x00000011 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
  3853. Software Guard Extensions (SGX) capability (0x12/0):
  3854. SGX1 supported = false
  3855. SGX2 supported = false
  3856. SGX ENCLV E*VIRTCHILD, ESETCONTEXT = false
  3857. SGX ENCLS ETRACKC, ERDINFO, ELDBC, ELDUC = false
  3858. MISCSELECT.EXINFO supported: #PF & #GP = false
  3859. MISCSELECT.CPINFO supported: #CP = false
  3860. MaxEnclaveSize_Not64 (log2) = 0x0 (0)
  3861. MaxEnclaveSize_64 (log2) = 0x0 (0)
  3862. 0x00000013 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
  3863. Intel Processor Trace (0x14):
  3864. IA32_RTIT_CR3_MATCH is accessible = false
  3865. configurable PSB & cycle-accurate = false
  3866. IP & TraceStop filtering; PT preserve = false
  3867. MTC timing packet; suppress COFI-based = false
  3868. PTWRITE support = false
  3869. power event trace support = false
  3870. ToPA output scheme support = false
  3871. ToPA can hold many output entries = false
  3872. single-range output scheme support = false
  3873. output to trace transport = false
  3874. IP payloads have LIP values & CS = false
  3875. Time Stamp Counter/Core Crystal Clock Information (0x15):
  3876. TSC/clock ratio = 0/0
  3877. nominal core crystal clock = 0 Hz
  3878. Processor Frequency Information (0x16):
  3879. Core Base Frequency (MHz) = 0x0 (0)
  3880. Core Maximum Frequency (MHz) = 0x0 (0)
  3881. Bus (Reference) Frequency (MHz) = 0x0 (0)
  3882. hypervisor_id = "KVMKVMKVM "
  3883. hypervisor features (0x40000001/eax):
  3884. kvmclock available at MSR 0x11 = true
  3885. delays unnecessary for PIO ops = true
  3886. mmu_op = false
  3887. kvmclock available at MSR 0x4b564d00 = true
  3888. async pf enable available by MSR = true
  3889. steal clock supported = true
  3890. guest EOI optimization enabled = true
  3891. guest spinlock optimization enabled = true
  3892. guest TLB flush optimization enabled = true
  3893. async PF VM exit enable available by MSR = false
  3894. guest send IPI optimization enabled = true
  3895. host HLT poll disable at MSR 0x4b564d05 = true
  3896. guest sched yield optimization enabled = true
  3897. guest uses intrs for page ready APF evs = false
  3898. stable: no guest per-cpu warps expected = true
  3899. hypervisor features (0x40000001/edx):
  3900. realtime hint: no unbound preemption = true
  3901. extended feature flags (0x80000001/edx):
  3902. SYSCALL and SYSRET instructions = true
  3903. execution disable = true
  3904. 1-GB large page support = true
  3905. RDTSCP = true
  3906. 64-bit extensions technology available = true
  3907. Intel feature flags (0x80000001/ecx):
  3908. LAHF/SAHF supported in 64-bit mode = true
  3909. LZCNT advanced bit manipulation = true
  3910. 3DNow! PREFETCH/PREFETCHW instructions = true
  3911. brand = "Intel(R) Xeon(R) Platinum 8275CL CPU @ 3.00GHz"
  3912. L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
  3913. instruction # entries = 0xff (255)
  3914. instruction associativity = 0x1 (1)
  3915. data # entries = 0xff (255)
  3916. data associativity = 0x1 (1)
  3917. L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
  3918. instruction # entries = 0xff (255)
  3919. instruction associativity = 0x1 (1)
  3920. data # entries = 0xff (255)
  3921. data associativity = 0x1 (1)
  3922. L1 data cache information (0x80000005/ecx):
  3923. line size (bytes) = 0x40 (64)
  3924. lines per tag = 0x1 (1)
  3925. associativity = 0x2 (2)
  3926. size (KB) = 0x40 (64)
  3927. L1 instruction cache information (0x80000005/edx):
  3928. line size (bytes) = 0x40 (64)
  3929. lines per tag = 0x1 (1)
  3930. associativity = 0x2 (2)
  3931. size (KB) = 0x40 (64)
  3932. L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
  3933. instruction # entries = 0x0 (0)
  3934. instruction associativity = L2 off (0)
  3935. data # entries = 0x0 (0)
  3936. data associativity = L2 off (0)
  3937. L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
  3938. instruction # entries = 0x200 (512)
  3939. instruction associativity = 4-way (4)
  3940. data # entries = 0x200 (512)
  3941. data associativity = 4-way (4)
  3942. L2 unified cache information (0x80000006/ecx):
  3943. line size (bytes) = 0x40 (64)
  3944. lines per tag = 0x1 (1)
  3945. associativity = 16-way (8)
  3946. size (KB) = 0x200 (512)
  3947. L3 cache information (0x80000006/edx):
  3948. line size (bytes) = 0x40 (64)
  3949. lines per tag = 0x1 (1)
  3950. associativity = 16-way (8)
  3951. size (in 512KB units) = 0x20 (32)
  3952. RAS Capability (0x80000007/ebx):
  3953. MCA overflow recovery support = false
  3954. SUCCOR support = false
  3955. HWA: hardware assert support = false
  3956. scalable MCA support = false
  3957. Advanced Power Management Features (0x80000007/ecx):
  3958. CmpUnitPwrSampleTimeRatio = 0x0 (0)
  3959. Advanced Power Management Features (0x80000007/edx):
  3960. TS: temperature sensing diode = false
  3961. FID: frequency ID control = false
  3962. VID: voltage ID control = false
  3963. TTP: thermal trip = false
  3964. TM: thermal monitor = false
  3965. STC: software thermal control = false
  3966. 100 MHz multiplier control = false
  3967. hardware P-State control = false
  3968. TscInvariant = false
  3969. CPB: core performance boost = false
  3970. read-only effective frequency interface = false
  3971. processor feedback interface = false
  3972. APM power reporting = false
  3973. connected standby = false
  3974. RAPL: running average power limit = false
  3975. Physical Address and Linear Address Size (0x80000008/eax):
  3976. maximum physical address bits = 0x2e (46)
  3977. maximum linear (virtual) address bits = 0x30 (48)
  3978. maximum guest physical address bits = 0x0 (0)
  3979. Extended Feature Extensions ID (0x80000008/ebx):
  3980. CLZERO instruction = false
  3981. instructions retired count support = false
  3982. always save/restore error pointers = false
  3983. RDPRU instruction = false
  3984. memory bandwidth enforcement = false
  3985. WBNOINVD instruction = false
  3986. IBPB: indirect branch prediction barrier = true
  3987. IBRS: indirect branch restr speculation = true
  3988. STIBP: 1 thr indirect branch predictor = true
  3989. STIBP always on preferred mode = false
  3990. ppin processor id number supported = false
  3991. SSBD: speculative store bypass disable = true
  3992. virtualized SSBD = false
  3993. SSBD fixed in hardware = false
  3994. Size Identifiers (0x80000008/ecx):
  3995. number of CPU cores = 0x1 (1)
  3996. ApicIdCoreIdSize = 0x0 (0)
  3997. performance time-stamp counter size = 0x0 (0)
  3998. Feature Extended Size (0x80000008/edx):
  3999. RDPRU instruction max input support = 0x0 (0)
  4000. (multi-processing synth) = none
  4001. (multi-processing method) = Intel leaf 0xb
  4002. (APIC widths synth): CORE_width=0 SMT_width=0
  4003. (APIC synth): PKG_ID=6 CORE_ID=0 SMT_ID=0
  4004. (uarch synth) = Intel Cascade Lake {Skylake}, 14nm
  4005. (synth) = Intel Scalable (2nd Gen) Bronze/Silver/Gold/Platinum (Cascade Lake B1/L1/R1) {Skylake}, 14nm
  4006. CPU 7:
  4007. vendor_id = "GenuineIntel"
  4008. version information (1/eax):
  4009. processor type = primary processor (0)
  4010. family = 0x6 (6)
  4011. model = 0x5 (5)
  4012. stepping id = 0x7 (7)
  4013. extended family = 0x0 (0)
  4014. extended model = 0x5 (5)
  4015. (family synth) = 0x6 (6)
  4016. (model synth) = 0x55 (85)
  4017. (simple synth) = Intel Core (unknown type) (Skylake / Skylake-X / Cascade Lake / Cascade Lake-X) {Skylake}, 14nm
  4018. miscellaneous (1/ebx):
  4019. process local APIC physical ID = 0x7 (7)
  4020. maximum IDs for CPUs in pkg = 0x0 (0)
  4021. CLFLUSH line size = 0x8 (8)
  4022. brand index = 0x0 (0)
  4023. brand id = 0x00 (0): unknown
  4024. feature information (1/edx):
  4025. x87 FPU on chip = true
  4026. VME: virtual-8086 mode enhancement = true
  4027. DE: debugging extensions = true
  4028. PSE: page size extensions = true
  4029. TSC: time stamp counter = true
  4030. RDMSR and WRMSR support = true
  4031. PAE: physical address extensions = true
  4032. MCE: machine check exception = true
  4033. CMPXCHG8B inst. = true
  4034. APIC on chip = true
  4035. SYSENTER and SYSEXIT = true
  4036. MTRR: memory type range registers = true
  4037. PTE global bit = true
  4038. MCA: machine check architecture = true
  4039. CMOV: conditional move/compare instr = true
  4040. PAT: page attribute table = true
  4041. PSE-36: page size extension = true
  4042. PSN: processor serial number = false
  4043. CLFLUSH instruction = true
  4044. DS: debug store = false
  4045. ACPI: thermal monitor and clock ctrl = false
  4046. MMX Technology = true
  4047. FXSAVE/FXRSTOR = true
  4048. SSE extensions = true
  4049. SSE2 extensions = true
  4050. SS: self snoop = true
  4051. hyper-threading / multi-core supported = false
  4052. TM: therm. monitor = false
  4053. IA64 = false
  4054. PBE: pending break event = false
  4055. feature information (1/ecx):
  4056. PNI/SSE3: Prescott New Instructions = true
  4057. PCLMULDQ instruction = true
  4058. DTES64: 64-bit debug store = false
  4059. MONITOR/MWAIT = false
  4060. CPL-qualified debug store = false
  4061. VMX: virtual machine extensions = true
  4062. SMX: safer mode extensions = false
  4063. Enhanced Intel SpeedStep Technology = false
  4064. TM2: thermal monitor 2 = false
  4065. SSSE3 extensions = true
  4066. context ID: adaptive or shared L1 data = false
  4067. SDBG: IA32_DEBUG_INTERFACE = false
  4068. FMA instruction = true
  4069. CMPXCHG16B instruction = true
  4070. xTPR disable = false
  4071. PDCM: perfmon and debug = false
  4072. PCID: process context identifiers = true
  4073. DCA: direct cache access = false
  4074. SSE4.1 extensions = true
  4075. SSE4.2 extensions = true
  4076. x2APIC: extended xAPIC support = true
  4077. MOVBE instruction = true
  4078. POPCNT instruction = true
  4079. time stamp counter deadline = true
  4080. AES instruction = true
  4081. XSAVE/XSTOR states = true
  4082. OS-enabled XSAVE/XSTOR = true
  4083. AVX: advanced vector extensions = true
  4084. F16C half-precision convert instruction = true
  4085. RDRAND instruction = true
  4086. hypervisor guest status = true
  4087. cache and TLB information (2):
  4088. 0x4d: L3 cache: 16M, 16-way, 64 byte lines
  4089. 0x7d: L2 cache: 2M, 8-way, 64 byte lines
  4090. 0x30: L1 cache: 32K, 8-way, 64 byte lines
  4091. 0x2c: L1 data cache: 32K, 8-way, 64 byte lines
  4092. processor serial number = 0005-0657-0000-0000-0000-0000
  4093. deterministic cache parameters (4):
  4094. --- cache 0 ---
  4095. cache type = data cache (1)
  4096. cache level = 0x1 (1)
  4097. self-initializing cache level = true
  4098. fully associative cache = false
  4099. maximum IDs for CPUs sharing cache = 0x0 (0)
  4100. maximum IDs for cores in pkg = 0x0 (0)
  4101. system coherency line size = 0x40 (64)
  4102. physical line partitions = 0x1 (1)
  4103. ways of associativity = 0x8 (8)
  4104. number of sets = 0x40 (64)
  4105. WBINVD/INVD acts on lower caches = true
  4106. inclusive to lower caches = false
  4107. complex cache indexing = false
  4108. number of sets (s) = 64
  4109. (size synth) = 32768 (32 KB)
  4110. --- cache 1 ---
  4111. cache type = instruction cache (2)
  4112. cache level = 0x1 (1)
  4113. self-initializing cache level = true
  4114. fully associative cache = false
  4115. maximum IDs for CPUs sharing cache = 0x0 (0)
  4116. maximum IDs for cores in pkg = 0x0 (0)
  4117. system coherency line size = 0x40 (64)
  4118. physical line partitions = 0x1 (1)
  4119. ways of associativity = 0x8 (8)
  4120. number of sets = 0x40 (64)
  4121. WBINVD/INVD acts on lower caches = true
  4122. inclusive to lower caches = false
  4123. complex cache indexing = false
  4124. number of sets (s) = 64
  4125. (size synth) = 32768 (32 KB)
  4126. --- cache 2 ---
  4127. cache type = unified cache (3)
  4128. cache level = 0x2 (2)
  4129. self-initializing cache level = true
  4130. fully associative cache = false
  4131. maximum IDs for CPUs sharing cache = 0x0 (0)
  4132. maximum IDs for cores in pkg = 0x0 (0)
  4133. system coherency line size = 0x40 (64)
  4134. physical line partitions = 0x1 (1)
  4135. ways of associativity = 0x10 (16)
  4136. number of sets = 0x1000 (4096)
  4137. WBINVD/INVD acts on lower caches = true
  4138. inclusive to lower caches = false
  4139. complex cache indexing = false
  4140. number of sets (s) = 4096
  4141. (size synth) = 4194304 (4 MB)
  4142. --- cache 3 ---
  4143. cache type = unified cache (3)
  4144. cache level = 0x3 (3)
  4145. self-initializing cache level = true
  4146. fully associative cache = false
  4147. maximum IDs for CPUs sharing cache = 0x0 (0)
  4148. maximum IDs for cores in pkg = 0x0 (0)
  4149. system coherency line size = 0x40 (64)
  4150. physical line partitions = 0x1 (1)
  4151. ways of associativity = 0x10 (16)
  4152. number of sets = 0x4000 (16384)
  4153. WBINVD/INVD acts on lower caches = false
  4154. inclusive to lower caches = true
  4155. complex cache indexing = true
  4156. number of sets (s) = 16384
  4157. (size synth) = 16777216 (16 MB)
  4158. MONITOR/MWAIT (5):
  4159. smallest monitor-line size (bytes) = 0x0 (0)
  4160. largest monitor-line size (bytes) = 0x0 (0)
  4161. enum of Monitor-MWAIT exts supported = true
  4162. supports intrs as break-event for MWAIT = true
  4163. number of C0 sub C-states using MWAIT = 0x0 (0)
  4164. number of C1 sub C-states using MWAIT = 0x0 (0)
  4165. number of C2 sub C-states using MWAIT = 0x0 (0)
  4166. number of C3 sub C-states using MWAIT = 0x0 (0)
  4167. number of C4 sub C-states using MWAIT = 0x0 (0)
  4168. number of C5 sub C-states using MWAIT = 0x0 (0)
  4169. number of C6 sub C-states using MWAIT = 0x0 (0)
  4170. number of C7 sub C-states using MWAIT = 0x0 (0)
  4171. Thermal and Power Management Features (6):
  4172. digital thermometer = false
  4173. Intel Turbo Boost Technology = false
  4174. ARAT always running APIC timer = true
  4175. PLN power limit notification = false
  4176. ECMD extended clock modulation duty = false
  4177. PTM package thermal management = false
  4178. HWP base registers = false
  4179. HWP notification = false
  4180. HWP activity window = false
  4181. HWP energy performance preference = false
  4182. HWP package level request = false
  4183. HDC base registers = false
  4184. Intel Turbo Boost Max Technology 3.0 = false
  4185. HWP capabilities = false
  4186. HWP PECI override = false
  4187. flexible HWP = false
  4188. IA32_HWP_REQUEST MSR fast access mode = false
  4189. HW_FEEDBACK MSRs supported = false
  4190. ignoring idle logical processor HWP req = false
  4191. enhanced hardware feedback interface = false
  4192. digital thermometer thresholds = 0x0 (0)
  4193. hardware coordination feedback = false
  4194. ACNT2 available = false
  4195. performance-energy bias capability = false
  4196. number of enh hardware feedback classes = 0x0 (0)
  4197. performance capability reporting = false
  4198. energy efficiency capability reporting = false
  4199. size of feedback struct (4KB pages) = 0x1 (1)
  4200. index of CPU's row in feedback struct = 0x0 (0)
  4201. extended feature flags (7):
  4202. FSGSBASE instructions = true
  4203. IA32_TSC_ADJUST MSR supported = true
  4204. SGX: Software Guard Extensions supported = false
  4205. BMI1 instructions = true
  4206. HLE hardware lock elision = false
  4207. AVX2: advanced vector extensions 2 = true
  4208. FDP_EXCPTN_ONLY = false
  4209. SMEP supervisor mode exec protection = true
  4210. BMI2 instructions = true
  4211. enhanced REP MOVSB/STOSB = true
  4212. INVPCID instruction = true
  4213. RTM: restricted transactional memory = false
  4214. RDT-CMT/PQoS cache monitoring = false
  4215. deprecated FPU CS/DS = false
  4216. MPX: intel memory protection extensions = true
  4217. RDT-CAT/PQE cache allocation = false
  4218. AVX512F: AVX-512 foundation instructions = true
  4219. AVX512DQ: double & quadword instructions = true
  4220. RDSEED instruction = true
  4221. ADX instructions = true
  4222. SMAP: supervisor mode access prevention = true
  4223. AVX512IFMA: fused multiply add = false
  4224. PCOMMIT instruction = false
  4225. CLFLUSHOPT instruction = true
  4226. CLWB instruction = true
  4227. Intel processor trace = false
  4228. AVX512PF: prefetch instructions = false
  4229. AVX512ER: exponent & reciprocal instrs = false
  4230. AVX512CD: conflict detection instrs = true
  4231. SHA instructions = false
  4232. AVX512BW: byte & word instructions = true
  4233. AVX512VL: vector length = true
  4234. PREFETCHWT1 = false
  4235. AVX512VBMI: vector byte manipulation = false
  4236. UMIP: user-mode instruction prevention = true
  4237. PKU protection keys for user-mode = true
  4238. OSPKE CR4.PKE and RDPKRU/WRPKRU = true
  4239. WAITPKG instructions = false
  4240. AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
  4241. CET_SS: CET shadow stack = false
  4242. GFNI: Galois Field New Instructions = false
  4243. VAES instructions = false
  4244. VPCLMULQDQ instruction = false
  4245. AVX512_VNNI: neural network instructions = true
  4246. AVX512_BITALG: bit count/shiffle = false
  4247. TME: Total Memory Encryption = false
  4248. AVX512: VPOPCNTDQ instruction = false
  4249. 5-level paging = false
  4250. BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
  4251. RDPID: read processor D supported = false
  4252. KL: key locker = false
  4253. CLDEMOTE supports cache line demote = false
  4254. MOVDIRI instruction = false
  4255. MOVDIR64B instruction = false
  4256. ENQCMD instruction = false
  4257. SGX_LC: SGX launch config supported = false
  4258. PKS: supervisor protection keys = false
  4259. AVX512_4VNNIW: neural network instrs = false
  4260. AVX512_4FMAPS: multiply acc single prec = false
  4261. fast short REP MOV = false
  4262. UINTR: user interrupts = false
  4263. AVX512_VP2INTERSECT: intersect mask regs = false
  4264. SRBDS mitigation MSR available = false
  4265. VERW MD_CLEAR microcode support = true
  4266. SERIALIZE instruction = false
  4267. hybrid part = false
  4268. TSXLDTRK: TSX suspend load addr tracking = false
  4269. PCONFIG instruction = false
  4270. LBR: architectural last branch records = false
  4271. CET_IBT: CET indirect branch tracking = false
  4272. AMX-BF16: tile bfloat16 support = false
  4273. AVX512_FP16: fp16 support = false
  4274. AMX-TILE: tile architecture support = false
  4275. AMX-INT8: tile 8-bit integer support = false
  4276. IBRS/IBPB: indirect branch restrictions = true
  4277. STIBP: 1 thr indirect branch predictor = true
  4278. L1D_FLUSH: IA32_FLUSH_CMD MSR = false
  4279. IA32_ARCH_CAPABILITIES MSR = true
  4280. IA32_CORE_CAPABILITIES MSR = false
  4281. SSBD: speculative store bypass disable = true
  4282. Direct Cache Access Parameters (9):
  4283. PLATFORM_DCA_CAP MSR bits = 0
  4284. Architecture Performance Monitoring Features (0xa):
  4285. version ID = 0x2 (2)
  4286. number of counters per logical processor = 0x4 (4)
  4287. bit width of counter = 0x30 (48)
  4288. length of EBX bit vector = 0x7 (7)
  4289. core cycle event not available = false
  4290. instruction retired event not available = false
  4291. reference cycles event not available = false
  4292. last-level cache ref event not available = false
  4293. last-level cache miss event not avail = false
  4294. branch inst retired event not available = false
  4295. branch mispred retired event not avail = false
  4296. fixed counter 0 supported = false
  4297. fixed counter 1 supported = false
  4298. fixed counter 2 supported = false
  4299. fixed counter 3 supported = false
  4300. fixed counter 4 supported = false
  4301. fixed counter 5 supported = false
  4302. fixed counter 6 supported = false
  4303. fixed counter 7 supported = false
  4304. fixed counter 8 supported = false
  4305. fixed counter 9 supported = false
  4306. fixed counter 10 supported = false
  4307. fixed counter 11 supported = false
  4308. fixed counter 12 supported = false
  4309. fixed counter 13 supported = false
  4310. fixed counter 14 supported = false
  4311. fixed counter 15 supported = false
  4312. fixed counter 16 supported = false
  4313. fixed counter 17 supported = false
  4314. fixed counter 18 supported = false
  4315. fixed counter 19 supported = false
  4316. fixed counter 20 supported = false
  4317. fixed counter 21 supported = false
  4318. fixed counter 22 supported = false
  4319. fixed counter 23 supported = false
  4320. fixed counter 24 supported = false
  4321. fixed counter 25 supported = false
  4322. fixed counter 26 supported = false
  4323. fixed counter 27 supported = false
  4324. fixed counter 28 supported = false
  4325. fixed counter 29 supported = false
  4326. fixed counter 30 supported = false
  4327. fixed counter 31 supported = false
  4328. number of fixed counters = 0x3 (3)
  4329. bit width of fixed counters = 0x30 (48)
  4330. anythread deprecation = false
  4331. x2APIC features / processor topology (0xb):
  4332. extended APIC ID = 7
  4333. --- level 0 ---
  4334. level number = 0x0 (0)
  4335. level type = thread (1)
  4336. bit width of level = 0x0 (0)
  4337. number of logical processors at level = 0x1 (1)
  4338. --- level 1 ---
  4339. level number = 0x1 (1)
  4340. level type = core (2)
  4341. bit width of level = 0x0 (0)
  4342. number of logical processors at level = 0x1 (1)
  4343. XSAVE features (0xd/0):
  4344. XCR0 lower 32 bits valid bit field mask = 0x000002ff
  4345. XCR0 upper 32 bits valid bit field mask = 0x00000000
  4346. XCR0 supported: x87 state = true
  4347. XCR0 supported: SSE state = true
  4348. XCR0 supported: AVX state = true
  4349. XCR0 supported: MPX BNDREGS = true
  4350. XCR0 supported: MPX BNDCSR = true
  4351. XCR0 supported: AVX-512 opmask = true
  4352. XCR0 supported: AVX-512 ZMM_Hi256 = true
  4353. XCR0 supported: AVX-512 Hi16_ZMM = true
  4354. IA32_XSS supported: PT state = false
  4355. XCR0 supported: PKRU state = true
  4356. XCR0 supported: CET_U state = false
  4357. XCR0 supported: CET_S state = false
  4358. IA32_XSS supported: HDC state = false
  4359. IA32_XSS supported: UINTR state = false
  4360. LBR supported = false
  4361. IA32_XSS supported: HWP state = false
  4362. XTILECFG supported = false
  4363. XTILEDATA supported = false
  4364. bytes required by fields in XCR0 = 0x00000a88 (2696)
  4365. bytes required by XSAVE/XRSTOR area = 0x00000a88 (2696)
  4366. XSAVE features (0xd/1):
  4367. XSAVEOPT instruction = true
  4368. XSAVEC instruction = true
  4369. XGETBV instruction = true
  4370. XSAVES/XRSTORS instructions = true
  4371. XFD: extended feature disable supported = false
  4372. SAVE area size in bytes = 0x00000a08 (2568)
  4373. IA32_XSS lower 32 bits valid bit field mask = 0x00000000
  4374. IA32_XSS upper 32 bits valid bit field mask = 0x00000000
  4375. AVX/YMM features (0xd/2):
  4376. AVX/YMM save state byte size = 0x00000100 (256)
  4377. AVX/YMM save state byte offset = 0x00000240 (576)
  4378. supported in IA32_XSS or XCR0 = XCR0 (user state)
  4379. 64-byte alignment in compacted XSAVE = false
  4380. XFD faulting supported = false
  4381. MPX BNDREGS features (0xd/3):
  4382. MPX BNDREGS save state byte size = 0x00000040 (64)
  4383. MPX BNDREGS save state byte offset = 0x000003c0 (960)
  4384. supported in IA32_XSS or XCR0 = XCR0 (user state)
  4385. 64-byte alignment in compacted XSAVE = false
  4386. XFD faulting supported = false
  4387. MPX BNDCSR features (0xd/4):
  4388. MPX BNDCSR save state byte size = 0x00000040 (64)
  4389. MPX BNDCSR save state byte offset = 0x00000400 (1024)
  4390. supported in IA32_XSS or XCR0 = XCR0 (user state)
  4391. 64-byte alignment in compacted XSAVE = false
  4392. XFD faulting supported = false
  4393. AVX-512 opmask features (0xd/5):
  4394. AVX-512 opmask save state byte size = 0x00000040 (64)
  4395. AVX-512 opmask save state byte offset = 0x00000440 (1088)
  4396. supported in IA32_XSS or XCR0 = XCR0 (user state)
  4397. 64-byte alignment in compacted XSAVE = false
  4398. XFD faulting supported = false
  4399. AVX-512 ZMM_Hi256 features (0xd/6):
  4400. AVX-512 ZMM_Hi256 save state byte size = 0x00000200 (512)
  4401. AVX-512 ZMM_Hi256 save state byte offset = 0x00000480 (1152)
  4402. supported in IA32_XSS or XCR0 = XCR0 (user state)
  4403. 64-byte alignment in compacted XSAVE = false
  4404. XFD faulting supported = false
  4405. AVX-512 Hi16_ZMM features (0xd/7):
  4406. AVX-512 Hi16_ZMM save state byte size = 0x00000400 (1024)
  4407. AVX-512 Hi16_ZMM save state byte offset = 0x00000680 (1664)
  4408. supported in IA32_XSS or XCR0 = XCR0 (user state)
  4409. 64-byte alignment in compacted XSAVE = false
  4410. XFD faulting supported = false
  4411. PKRU features (0xd/9):
  4412. PKRU save state byte size = 0x00000008 (8)
  4413. PKRU save state byte offset = 0x00000a80 (2688)
  4414. supported in IA32_XSS or XCR0 = XCR0 (user state)
  4415. 64-byte alignment in compacted XSAVE = false
  4416. XFD faulting supported = false
  4417. Quality of Service Monitoring Resource Type (0xf/0):
  4418. Maximum range of RMID = 0
  4419. supports L3 cache QoS monitoring = false
  4420. Resource Director Technology Allocation (0x10/0):
  4421. L3 cache allocation technology supported = false
  4422. L2 cache allocation technology supported = false
  4423. memory bandwidth allocation supported = false
  4424. 0x00000011 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
  4425. Software Guard Extensions (SGX) capability (0x12/0):
  4426. SGX1 supported = false
  4427. SGX2 supported = false
  4428. SGX ENCLV E*VIRTCHILD, ESETCONTEXT = false
  4429. SGX ENCLS ETRACKC, ERDINFO, ELDBC, ELDUC = false
  4430. MISCSELECT.EXINFO supported: #PF & #GP = false
  4431. MISCSELECT.CPINFO supported: #CP = false
  4432. MaxEnclaveSize_Not64 (log2) = 0x0 (0)
  4433. MaxEnclaveSize_64 (log2) = 0x0 (0)
  4434. 0x00000013 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
  4435. Intel Processor Trace (0x14):
  4436. IA32_RTIT_CR3_MATCH is accessible = false
  4437. configurable PSB & cycle-accurate = false
  4438. IP & TraceStop filtering; PT preserve = false
  4439. MTC timing packet; suppress COFI-based = false
  4440. PTWRITE support = false
  4441. power event trace support = false
  4442. ToPA output scheme support = false
  4443. ToPA can hold many output entries = false
  4444. single-range output scheme support = false
  4445. output to trace transport = false
  4446. IP payloads have LIP values & CS = false
  4447. Time Stamp Counter/Core Crystal Clock Information (0x15):
  4448. TSC/clock ratio = 0/0
  4449. nominal core crystal clock = 0 Hz
  4450. Processor Frequency Information (0x16):
  4451. Core Base Frequency (MHz) = 0x0 (0)
  4452. Core Maximum Frequency (MHz) = 0x0 (0)
  4453. Bus (Reference) Frequency (MHz) = 0x0 (0)
  4454. hypervisor_id = "KVMKVMKVM "
  4455. hypervisor features (0x40000001/eax):
  4456. kvmclock available at MSR 0x11 = true
  4457. delays unnecessary for PIO ops = true
  4458. mmu_op = false
  4459. kvmclock available at MSR 0x4b564d00 = true
  4460. async pf enable available by MSR = true
  4461. steal clock supported = true
  4462. guest EOI optimization enabled = true
  4463. guest spinlock optimization enabled = true
  4464. guest TLB flush optimization enabled = true
  4465. async PF VM exit enable available by MSR = false
  4466. guest send IPI optimization enabled = true
  4467. host HLT poll disable at MSR 0x4b564d05 = true
  4468. guest sched yield optimization enabled = true
  4469. guest uses intrs for page ready APF evs = false
  4470. stable: no guest per-cpu warps expected = true
  4471. hypervisor features (0x40000001/edx):
  4472. realtime hint: no unbound preemption = true
  4473. extended feature flags (0x80000001/edx):
  4474. SYSCALL and SYSRET instructions = true
  4475. execution disable = true
  4476. 1-GB large page support = true
  4477. RDTSCP = true
  4478. 64-bit extensions technology available = true
  4479. Intel feature flags (0x80000001/ecx):
  4480. LAHF/SAHF supported in 64-bit mode = true
  4481. LZCNT advanced bit manipulation = true
  4482. 3DNow! PREFETCH/PREFETCHW instructions = true
  4483. brand = "Intel(R) Xeon(R) Platinum 8275CL CPU @ 3.00GHz"
  4484. L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
  4485. instruction # entries = 0xff (255)
  4486. instruction associativity = 0x1 (1)
  4487. data # entries = 0xff (255)
  4488. data associativity = 0x1 (1)
  4489. L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
  4490. instruction # entries = 0xff (255)
  4491. instruction associativity = 0x1 (1)
  4492. data # entries = 0xff (255)
  4493. data associativity = 0x1 (1)
  4494. L1 data cache information (0x80000005/ecx):
  4495. line size (bytes) = 0x40 (64)
  4496. lines per tag = 0x1 (1)
  4497. associativity = 0x2 (2)
  4498. size (KB) = 0x40 (64)
  4499. L1 instruction cache information (0x80000005/edx):
  4500. line size (bytes) = 0x40 (64)
  4501. lines per tag = 0x1 (1)
  4502. associativity = 0x2 (2)
  4503. size (KB) = 0x40 (64)
  4504. L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
  4505. instruction # entries = 0x0 (0)
  4506. instruction associativity = L2 off (0)
  4507. data # entries = 0x0 (0)
  4508. data associativity = L2 off (0)
  4509. L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
  4510. instruction # entries = 0x200 (512)
  4511. instruction associativity = 4-way (4)
  4512. data # entries = 0x200 (512)
  4513. data associativity = 4-way (4)
  4514. L2 unified cache information (0x80000006/ecx):
  4515. line size (bytes) = 0x40 (64)
  4516. lines per tag = 0x1 (1)
  4517. associativity = 16-way (8)
  4518. size (KB) = 0x200 (512)
  4519. L3 cache information (0x80000006/edx):
  4520. line size (bytes) = 0x40 (64)
  4521. lines per tag = 0x1 (1)
  4522. associativity = 16-way (8)
  4523. size (in 512KB units) = 0x20 (32)
  4524. RAS Capability (0x80000007/ebx):
  4525. MCA overflow recovery support = false
  4526. SUCCOR support = false
  4527. HWA: hardware assert support = false
  4528. scalable MCA support = false
  4529. Advanced Power Management Features (0x80000007/ecx):
  4530. CmpUnitPwrSampleTimeRatio = 0x0 (0)
  4531. Advanced Power Management Features (0x80000007/edx):
  4532. TS: temperature sensing diode = false
  4533. FID: frequency ID control = false
  4534. VID: voltage ID control = false
  4535. TTP: thermal trip = false
  4536. TM: thermal monitor = false
  4537. STC: software thermal control = false
  4538. 100 MHz multiplier control = false
  4539. hardware P-State control = false
  4540. TscInvariant = false
  4541. CPB: core performance boost = false
  4542. read-only effective frequency interface = false
  4543. processor feedback interface = false
  4544. APM power reporting = false
  4545. connected standby = false
  4546. RAPL: running average power limit = false
  4547. Physical Address and Linear Address Size (0x80000008/eax):
  4548. maximum physical address bits = 0x2e (46)
  4549. maximum linear (virtual) address bits = 0x30 (48)
  4550. maximum guest physical address bits = 0x0 (0)
  4551. Extended Feature Extensions ID (0x80000008/ebx):
  4552. CLZERO instruction = false
  4553. instructions retired count support = false
  4554. always save/restore error pointers = false
  4555. RDPRU instruction = false
  4556. memory bandwidth enforcement = false
  4557. WBNOINVD instruction = false
  4558. IBPB: indirect branch prediction barrier = true
  4559. IBRS: indirect branch restr speculation = true
  4560. STIBP: 1 thr indirect branch predictor = true
  4561. STIBP always on preferred mode = false
  4562. ppin processor id number supported = false
  4563. SSBD: speculative store bypass disable = true
  4564. virtualized SSBD = false
  4565. SSBD fixed in hardware = false
  4566. Size Identifiers (0x80000008/ecx):
  4567. number of CPU cores = 0x1 (1)
  4568. ApicIdCoreIdSize = 0x0 (0)
  4569. performance time-stamp counter size = 0x0 (0)
  4570. Feature Extended Size (0x80000008/edx):
  4571. RDPRU instruction max input support = 0x0 (0)
  4572. (multi-processing synth) = none
  4573. (multi-processing method) = Intel leaf 0xb
  4574. (APIC widths synth): CORE_width=0 SMT_width=0
  4575. (APIC synth): PKG_ID=7 CORE_ID=0 SMT_ID=0
  4576. (uarch synth) = Intel Cascade Lake {Skylake}, 14nm
  4577. (synth) = Intel Scalable (2nd Gen) Bronze/Silver/Gold/Platinum (Cascade Lake B1/L1/R1) {Skylake}, 14nm
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